1/*
2 * AMD Cryptographic Coprocessor (CCP) driver
3 *
4 * Copyright (C) 2013,2017 Advanced Micro Devices, Inc.
5 *
6 * Author: Tom Lendacky <thomas.lendacky@amd.com>
7 * Author: Gary R Hook <gary.hook@amd.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __CCP_DEV_H__
15#define __CCP_DEV_H__
16
17#include <linux/device.h>
18#include <linux/pci.h>
19#include <linux/spinlock.h>
20#include <linux/mutex.h>
21#include <linux/list.h>
22#include <linux/wait.h>
23#include <linux/dmapool.h>
24#include <linux/hw_random.h>
25#include <linux/bitops.h>
26#include <linux/interrupt.h>
27#include <linux/irqreturn.h>
28#include <linux/dmaengine.h>
29
30#include "sp-dev.h"
31
32#define MAX_CCP_NAME_LEN 16
33#define MAX_DMAPOOL_NAME_LEN 32
34
35#define MAX_HW_QUEUES 5
36#define MAX_CMD_QLEN 100
37
38#define TRNG_RETRIES 10
39
40#define CACHE_NONE 0x00
41#define CACHE_WB_NO_ALLOC 0xb7
42
43/****** Register Mappings ******/
44#define Q_MASK_REG 0x000
45#define TRNG_OUT_REG 0x00c
46#define IRQ_MASK_REG 0x040
47#define IRQ_STATUS_REG 0x200
48
49#define DEL_CMD_Q_JOB 0x124
50#define DEL_Q_ACTIVE 0x00000200
51#define DEL_Q_ID_SHIFT 6
52
53#define CMD_REQ0 0x180
54#define CMD_REQ_INCR 0x04
55
56#define CMD_Q_STATUS_BASE 0x210
57#define CMD_Q_INT_STATUS_BASE 0x214
58#define CMD_Q_STATUS_INCR 0x20
59
60#define CMD_Q_CACHE_BASE 0x228
61#define CMD_Q_CACHE_INC 0x20
62
63#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
64#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
65
66/* ------------------------ CCP Version 5 Specifics ------------------------ */
67#define CMD5_QUEUE_MASK_OFFSET 0x00
68#define CMD5_QUEUE_PRIO_OFFSET 0x04
69#define CMD5_REQID_CONFIG_OFFSET 0x08
70#define CMD5_CMD_TIMEOUT_OFFSET 0x10
71#define LSB_PUBLIC_MASK_LO_OFFSET 0x18
72#define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
73#define LSB_PRIVATE_MASK_LO_OFFSET 0x20
74#define LSB_PRIVATE_MASK_HI_OFFSET 0x24
75#define CMD5_PSP_CCP_VERSION 0x100
76
77#define CMD5_Q_CONTROL_BASE 0x0000
78#define CMD5_Q_TAIL_LO_BASE 0x0004
79#define CMD5_Q_HEAD_LO_BASE 0x0008
80#define CMD5_Q_INT_ENABLE_BASE 0x000C
81#define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
82
83#define CMD5_Q_STATUS_BASE 0x0100
84#define CMD5_Q_INT_STATUS_BASE 0x0104
85#define CMD5_Q_DMA_STATUS_BASE 0x0108
86#define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
87#define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
88#define CMD5_Q_ABORT_BASE 0x0114
89#define CMD5_Q_AX_CACHE_BASE 0x0118
90
91#define CMD5_CONFIG_0_OFFSET 0x6000
92#define CMD5_TRNG_CTL_OFFSET 0x6008
93#define CMD5_AES_MASK_OFFSET 0x6010
94#define CMD5_CLK_GATE_CTL_OFFSET 0x603C
95
96/* Address offset between two virtual queue registers */
97#define CMD5_Q_STATUS_INCR 0x1000
98
99/* Bit masks */
100#define CMD5_Q_RUN 0x1
101#define CMD5_Q_HALT 0x2
102#define CMD5_Q_MEM_LOCATION 0x4
103#define CMD5_Q_SIZE 0x1F
104#define CMD5_Q_SHIFT 3
105#define COMMANDS_PER_QUEUE 16
106#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
107 CMD5_Q_SIZE)
108#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109#define Q_DESC_SIZE sizeof(struct ccp5_desc)
110#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
111
112#define INT_COMPLETION 0x1
113#define INT_ERROR 0x2
114#define INT_QUEUE_STOPPED 0x4
115#define INT_EMPTY_QUEUE 0x8
116#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
117
118#define LSB_REGION_WIDTH 5
119#define MAX_LSB_CNT 8
120
121#define LSB_SIZE 16
122#define LSB_ITEM_SIZE 32
123#define PLSB_MAP_SIZE (LSB_SIZE)
124#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
125
126#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
127
128/* ------------------------ CCP Version 3 Specifics ------------------------ */
129#define REQ0_WAIT_FOR_WRITE 0x00000004
130#define REQ0_INT_ON_COMPLETE 0x00000002
131#define REQ0_STOP_ON_COMPLETE 0x00000001
132
133#define REQ0_CMD_Q_SHIFT 9
134#define REQ0_JOBID_SHIFT 3
135
136/****** REQ1 Related Values ******/
137#define REQ1_PROTECT_SHIFT 27
138#define REQ1_ENGINE_SHIFT 23
139#define REQ1_KEY_KSB_SHIFT 2
140
141#define REQ1_EOM 0x00000002
142#define REQ1_INIT 0x00000001
143
144/* AES Related Values */
145#define REQ1_AES_TYPE_SHIFT 21
146#define REQ1_AES_MODE_SHIFT 18
147#define REQ1_AES_ACTION_SHIFT 17
148#define REQ1_AES_CFB_SIZE_SHIFT 10
149
150/* XTS-AES Related Values */
151#define REQ1_XTS_AES_SIZE_SHIFT 10
152
153/* SHA Related Values */
154#define REQ1_SHA_TYPE_SHIFT 21
155
156/* RSA Related Values */
157#define REQ1_RSA_MOD_SIZE_SHIFT 10
158
159/* Pass-Through Related Values */
160#define REQ1_PT_BW_SHIFT 12
161#define REQ1_PT_BS_SHIFT 10
162
163/* ECC Related Values */
164#define REQ1_ECC_AFFINE_CONVERT 0x00200000
165#define REQ1_ECC_FUNCTION_SHIFT 18
166
167/****** REQ4 Related Values ******/
168#define REQ4_KSB_SHIFT 18
169#define REQ4_MEMTYPE_SHIFT 16
170
171/****** REQ6 Related Values ******/
172#define REQ6_MEMTYPE_SHIFT 16
173
174/****** Key Storage Block ******/
175#define KSB_START 77
176#define KSB_END 127
177#define KSB_COUNT (KSB_END - KSB_START + 1)
178#define CCP_SB_BITS 256
179
180#define CCP_JOBID_MASK 0x0000003f
181
182/* ------------------------ General CCP Defines ------------------------ */
183
184#define CCP_DMA_DFLT 0x0
185#define CCP_DMA_PRIV 0x1
186#define CCP_DMA_PUB 0x2
187
188#define CCP_DMAPOOL_MAX_SIZE 64
189#define CCP_DMAPOOL_ALIGN BIT(5)
190
191#define CCP_REVERSE_BUF_SIZE 64
192
193#define CCP_AES_KEY_SB_COUNT 1
194#define CCP_AES_CTX_SB_COUNT 1
195
196#define CCP_XTS_AES_KEY_SB_COUNT 1
197#define CCP5_XTS_AES_KEY_SB_COUNT 2
198#define CCP_XTS_AES_CTX_SB_COUNT 1
199
200#define CCP_DES3_KEY_SB_COUNT 1
201#define CCP_DES3_CTX_SB_COUNT 1
202
203#define CCP_SHA_SB_COUNT 1
204
205#define CCP_RSA_MAX_WIDTH 4096
206#define CCP5_RSA_MAX_WIDTH 16384
207
208#define CCP_PASSTHRU_BLOCKSIZE 256
209#define CCP_PASSTHRU_MASKSIZE 32
210#define CCP_PASSTHRU_SB_COUNT 1
211
212#define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
213#define CCP_ECC_MAX_OPERANDS 6
214#define CCP_ECC_MAX_OUTPUTS 3
215#define CCP_ECC_SRC_BUF_SIZE 448
216#define CCP_ECC_DST_BUF_SIZE 192
217#define CCP_ECC_OPERAND_SIZE 64
218#define CCP_ECC_OUTPUT_SIZE 64
219#define CCP_ECC_RESULT_OFFSET 60
220#define CCP_ECC_RESULT_SUCCESS 0x0001
221
222#define CCP_SB_BYTES 32
223
224struct ccp_op;
225struct ccp_device;
226struct ccp_cmd;
227struct ccp_fns;
228
229struct ccp_dma_cmd {
230 struct list_head entry;
231
232 struct ccp_cmd ccp_cmd;
233};
234
235struct ccp_dma_desc {
236 struct list_head entry;
237
238 struct ccp_device *ccp;
239
240 struct list_head pending;
241 struct list_head active;
242
243 enum dma_status status;
244 struct dma_async_tx_descriptor tx_desc;
245 size_t len;
246};
247
248struct ccp_dma_chan {
249 struct ccp_device *ccp;
250
251 spinlock_t lock;
252 struct list_head created;
253 struct list_head pending;
254 struct list_head active;
255 struct list_head complete;
256
257 struct tasklet_struct cleanup_tasklet;
258
259 enum dma_status status;
260 struct dma_chan dma_chan;
261};
262
263struct ccp_cmd_queue {
264 struct ccp_device *ccp;
265
266 /* Queue identifier */
267 u32 id;
268
269 /* Queue dma pool */
270 struct dma_pool *dma_pool;
271
272 /* Queue base address (not neccessarily aligned)*/
273 struct ccp5_desc *qbase;
274
275 /* Aligned queue start address (per requirement) */
276 struct mutex q_mutex ____cacheline_aligned;
277 unsigned int qidx;
278
279 /* Version 5 has different requirements for queue memory */
280 unsigned int qsize;
281 dma_addr_t qbase_dma;
282 dma_addr_t qdma_tail;
283
284 /* Per-queue reserved storage block(s) */
285 u32 sb_key;
286 u32 sb_ctx;
287
288 /* Bitmap of LSBs that can be accessed by this queue */
289 DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
290 /* Private LSB that is assigned to this queue, or -1 if none.
291 * Bitmap for my private LSB, unused otherwise
292 */
293 int lsb;
294 DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
295
296 /* Queue processing thread */
297 struct task_struct *kthread;
298 unsigned int active;
299 unsigned int suspended;
300
301 /* Number of free command slots available */
302 unsigned int free_slots;
303
304 /* Interrupt masks */
305 u32 int_ok;
306 u32 int_err;
307
308 /* Register addresses for queue */
309 void __iomem *reg_control;
310 void __iomem *reg_tail_lo;
311 void __iomem *reg_head_lo;
312 void __iomem *reg_int_enable;
313 void __iomem *reg_interrupt_status;
314 void __iomem *reg_status;
315 void __iomem *reg_int_status;
316 void __iomem *reg_dma_status;
317 void __iomem *reg_dma_read_status;
318 void __iomem *reg_dma_write_status;
319 u32 qcontrol; /* Cached control register */
320
321 /* Status values from job */
322 u32 int_status;
323 u32 q_status;
324 u32 q_int_status;
325 u32 cmd_error;
326
327 /* Interrupt wait queue */
328 wait_queue_head_t int_queue;
329 unsigned int int_rcvd;
330
331 /* Per-queue Statistics */
332 unsigned long total_ops;
333 unsigned long total_aes_ops;
334 unsigned long total_xts_aes_ops;
335 unsigned long total_3des_ops;
336 unsigned long total_sha_ops;
337 unsigned long total_rsa_ops;
338 unsigned long total_pt_ops;
339 unsigned long total_ecc_ops;
340} ____cacheline_aligned;
341
342struct ccp_device {
343 struct list_head entry;
344
345 struct ccp_vdata *vdata;
346 unsigned int ord;
347 char name[MAX_CCP_NAME_LEN];
348 char rngname[MAX_CCP_NAME_LEN];
349
350 struct device *dev;
351 struct sp_device *sp;
352
353 /* Bus specific device information
354 */
355 void *dev_specific;
356 unsigned int qim;
357 unsigned int irq;
358 bool use_tasklet;
359 struct tasklet_struct irq_tasklet;
360
361 /* I/O area used for device communication. The register mapping
362 * starts at an offset into the mapped bar.
363 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
364 * need to be protected while a command queue thread is accessing
365 * them.
366 */
367 struct mutex req_mutex ____cacheline_aligned;
368 void __iomem *io_regs;
369
370 /* Master lists that all cmds are queued on. Because there can be
371 * more than one CCP command queue that can process a cmd a separate
372 * backlog list is neeeded so that the backlog completion call
373 * completes before the cmd is available for execution.
374 */
375 spinlock_t cmd_lock ____cacheline_aligned;
376 unsigned int cmd_count;
377 struct list_head cmd;
378 struct list_head backlog;
379
380 /* The command queues. These represent the queues available on the
381 * CCP that are available for processing cmds
382 */
383 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
384 unsigned int cmd_q_count;
385
386 /* Support for the CCP True RNG
387 */
388 struct hwrng hwrng;
389 unsigned int hwrng_retries;
390
391 /* Support for the CCP DMA capabilities
392 */
393 struct dma_device dma_dev;
394 struct ccp_dma_chan *ccp_dma_chan;
395 struct kmem_cache *dma_cmd_cache;
396 struct kmem_cache *dma_desc_cache;
397
398 /* A counter used to generate job-ids for cmds submitted to the CCP
399 */
400 atomic_t current_id ____cacheline_aligned;
401
402 /* The v3 CCP uses key storage blocks (SB) to maintain context for
403 * certain operations. To prevent multiple cmds from using the same
404 * SB range a command queue reserves an SB range for the duration of
405 * the cmd. Each queue, will however, reserve 2 SB blocks for
406 * operations that only require single SB entries (eg. AES context/iv
407 * and key) in order to avoid allocation contention. This will reserve
408 * at most 10 SB entries, leaving 40 SB entries available for dynamic
409 * allocation.
410 *
411 * The v5 CCP Local Storage Block (LSB) is broken up into 8
412 * memrory ranges, each of which can be enabled for access by one
413 * or more queues. Device initialization takes this into account,
414 * and attempts to assign one region for exclusive use by each
415 * available queue; the rest are then aggregated as "public" use.
416 * If there are fewer regions than queues, all regions are shared
417 * amongst all queues.
418 */
419 struct mutex sb_mutex ____cacheline_aligned;
420 DECLARE_BITMAP(sb, KSB_COUNT);
421 wait_queue_head_t sb_queue;
422 unsigned int sb_avail;
423 unsigned int sb_count;
424 u32 sb_start;
425
426 /* Bitmap of shared LSBs, if any */
427 DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
428
429 /* Suspend support */
430 unsigned int suspending;
431 wait_queue_head_t suspend_queue;
432
433 /* DMA caching attribute support */
434 unsigned int axcache;
435
436 /* Device Statistics */
437 unsigned long total_interrupts;
438
439 /* DebugFS info */
440 struct dentry *debugfs_instance;
441};
442
443enum ccp_memtype {
444 CCP_MEMTYPE_SYSTEM = 0,
445 CCP_MEMTYPE_SB,
446 CCP_MEMTYPE_LOCAL,
447 CCP_MEMTYPE__LAST,
448};
449#define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
450
451
452struct ccp_dma_info {
453 dma_addr_t address;
454 unsigned int offset;
455 unsigned int length;
456 enum dma_data_direction dir;
457} __packed __aligned(4);
458
459struct ccp_dm_workarea {
460 struct device *dev;
461 struct dma_pool *dma_pool;
462
463 u8 *address;
464 struct ccp_dma_info dma;
465 unsigned int length;
466};
467
468struct ccp_sg_workarea {
469 struct scatterlist *sg;
470 int nents;
471 unsigned int sg_used;
472
473 struct scatterlist *dma_sg;
474 struct device *dma_dev;
475 unsigned int dma_count;
476 enum dma_data_direction dma_dir;
477
478 u64 bytes_left;
479};
480
481struct ccp_data {
482 struct ccp_sg_workarea sg_wa;
483 struct ccp_dm_workarea dm_wa;
484};
485
486struct ccp_mem {
487 enum ccp_memtype type;
488 union {
489 struct ccp_dma_info dma;
490 u32 sb;
491 } u;
492};
493
494struct ccp_aes_op {
495 enum ccp_aes_type type;
496 enum ccp_aes_mode mode;
497 enum ccp_aes_action action;
498 unsigned int size;
499};
500
501struct ccp_xts_aes_op {
502 enum ccp_aes_type type;
503 enum ccp_aes_action action;
504 enum ccp_xts_aes_unit_size unit_size;
505};
506
507struct ccp_des3_op {
508 enum ccp_des3_type type;
509 enum ccp_des3_mode mode;
510 enum ccp_des3_action action;
511};
512
513struct ccp_sha_op {
514 enum ccp_sha_type type;
515 u64 msg_bits;
516};
517
518struct ccp_rsa_op {
519 u32 mod_size;
520 u32 input_len;
521};
522
523struct ccp_passthru_op {
524 enum ccp_passthru_bitwise bit_mod;
525 enum ccp_passthru_byteswap byte_swap;
526};
527
528struct ccp_ecc_op {
529 enum ccp_ecc_function function;
530};
531
532struct ccp_op {
533 struct ccp_cmd_queue *cmd_q;
534
535 u32 jobid;
536 u32 ioc;
537 u32 soc;
538 u32 sb_key;
539 u32 sb_ctx;
540 u32 init;
541 u32 eom;
542
543 struct ccp_mem src;
544 struct ccp_mem dst;
545 struct ccp_mem exp;
546
547 union {
548 struct ccp_aes_op aes;
549 struct ccp_xts_aes_op xts;
550 struct ccp_des3_op des3;
551 struct ccp_sha_op sha;
552 struct ccp_rsa_op rsa;
553 struct ccp_passthru_op passthru;
554 struct ccp_ecc_op ecc;
555 } u;
556};
557
558static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
559{
560 return lower_32_bits(info->address + info->offset);
561}
562
563static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
564{
565 return upper_32_bits(info->address + info->offset) & 0x0000ffff;
566}
567
568/**
569 * descriptor for version 5 CPP commands
570 * 8 32-bit words:
571 * word 0: function; engine; control bits
572 * word 1: length of source data
573 * word 2: low 32 bits of source pointer
574 * word 3: upper 16 bits of source pointer; source memory type
575 * word 4: low 32 bits of destination pointer
576 * word 5: upper 16 bits of destination pointer; destination memory type
577 * word 6: low 32 bits of key pointer
578 * word 7: upper 16 bits of key pointer; key memory type
579 */
580struct dword0 {
581 unsigned int soc:1;
582 unsigned int ioc:1;
583 unsigned int rsvd1:1;
584 unsigned int init:1;
585 unsigned int eom:1; /* AES/SHA only */
586 unsigned int function:15;
587 unsigned int engine:4;
588 unsigned int prot:1;
589 unsigned int rsvd2:7;
590};
591
592struct dword3 {
593 unsigned int src_hi:16;
594 unsigned int src_mem:2;
595 unsigned int lsb_cxt_id:8;
596 unsigned int rsvd1:5;
597 unsigned int fixed:1;
598};
599
600union dword4 {
601 __le32 dst_lo; /* NON-SHA */
602 __le32 sha_len_lo; /* SHA */
603};
604
605union dword5 {
606 struct {
607 unsigned int dst_hi:16;
608 unsigned int dst_mem:2;
609 unsigned int rsvd1:13;
610 unsigned int fixed:1;
611 } fields;
612 __le32 sha_len_hi;
613};
614
615struct dword7 {
616 unsigned int key_hi:16;
617 unsigned int key_mem:2;
618 unsigned int rsvd1:14;
619};
620
621struct ccp5_desc {
622 struct dword0 dw0;
623 __le32 length;
624 __le32 src_lo;
625 struct dword3 dw3;
626 union dword4 dw4;
627 union dword5 dw5;
628 __le32 key_lo;
629 struct dword7 dw7;
630};
631
632void ccp_add_device(struct ccp_device *ccp);
633void ccp_del_device(struct ccp_device *ccp);
634
635extern void ccp_log_error(struct ccp_device *, int);
636
637struct ccp_device *ccp_alloc_struct(struct sp_device *sp);
638bool ccp_queues_suspended(struct ccp_device *ccp);
639int ccp_cmd_queue_thread(void *data);
640int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
641
642int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
643
644int ccp_register_rng(struct ccp_device *ccp);
645void ccp_unregister_rng(struct ccp_device *ccp);
646int ccp_dmaengine_register(struct ccp_device *ccp);
647void ccp_dmaengine_unregister(struct ccp_device *ccp);
648
649void ccp5_debugfs_setup(struct ccp_device *ccp);
650void ccp5_debugfs_destroy(void);
651
652/* Structure for computation functions that are device-specific */
653struct ccp_actions {
654 int (*aes)(struct ccp_op *);
655 int (*xts_aes)(struct ccp_op *);
656 int (*des3)(struct ccp_op *);
657 int (*sha)(struct ccp_op *);
658 int (*rsa)(struct ccp_op *);
659 int (*passthru)(struct ccp_op *);
660 int (*ecc)(struct ccp_op *);
661 u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
662 void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
663 unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
664 int (*init)(struct ccp_device *);
665 void (*destroy)(struct ccp_device *);
666 irqreturn_t (*irqhandler)(int, void *);
667};
668
669extern const struct ccp_vdata ccpv3_platform;
670extern const struct ccp_vdata ccpv3;
671extern const struct ccp_vdata ccpv5a;
672extern const struct ccp_vdata ccpv5b;
673
674#endif
675