| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* Copyright (C) 2003-2006, Advanced Micro Devices, Inc. |
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| 3 | */ |
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| 4 | |
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| 5 | #ifndef _GEODE_AES_H_ |
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| 6 | #define _GEODE_AES_H_ |
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| 7 | |
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| 8 | /* driver logic flags */ |
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| 9 | #define AES_MODE_ECB 0 |
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| 10 | #define AES_MODE_CBC 1 |
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| 11 | |
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| 12 | #define AES_DIR_DECRYPT 0 |
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| 13 | #define AES_DIR_ENCRYPT 1 |
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| 14 | |
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| 15 | #define AES_FLAGS_HIDDENKEY (1 << 0) |
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| 16 | |
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| 17 | /* Register definitions */ |
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| 18 | |
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| 19 | #define AES_CTRLA_REG 0x0000 |
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| 20 | |
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| 21 | #define AES_CTRL_START 0x01 |
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| 22 | #define AES_CTRL_DECRYPT 0x00 |
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| 23 | #define AES_CTRL_ENCRYPT 0x02 |
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| 24 | #define AES_CTRL_WRKEY 0x04 |
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| 25 | #define AES_CTRL_DCA 0x08 |
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| 26 | #define AES_CTRL_SCA 0x10 |
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| 27 | #define AES_CTRL_CBC 0x20 |
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| 28 | |
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| 29 | #define AES_INTR_REG 0x0008 |
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| 30 | |
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| 31 | #define AES_INTRA_PENDING (1 << 16) |
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| 32 | #define AES_INTRB_PENDING (1 << 17) |
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| 33 | |
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| 34 | #define AES_INTR_PENDING (AES_INTRA_PENDING | AES_INTRB_PENDING) |
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| 35 | #define AES_INTR_MASK 0x07 |
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| 36 | |
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| 37 | #define AES_SOURCEA_REG 0x0010 |
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| 38 | #define AES_DSTA_REG 0x0014 |
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| 39 | #define AES_LENA_REG 0x0018 |
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| 40 | #define AES_WRITEKEY0_REG 0x0030 |
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| 41 | #define AES_WRITEIV0_REG 0x0040 |
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| 42 | |
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| 43 | /* A very large counter that is used to gracefully bail out of an |
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| 44 | * operation in case of trouble |
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| 45 | */ |
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| 46 | |
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| 47 | #define AES_OP_TIMEOUT 0x50000 |
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| 48 | |
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| 49 | struct geode_aes_tfm_ctx { |
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| 50 | u8 key[AES_KEYSIZE_128]; |
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| 51 | union { |
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| 52 | struct crypto_skcipher *skcipher; |
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| 53 | struct crypto_cipher *cip; |
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| 54 | } fallback; |
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| 55 | u32 keylen; |
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| 56 | }; |
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| 57 | |
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| 58 | #endif |
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| 59 | |
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