1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Cryptographic API. |
4 | * |
5 | * Support for OMAP AES HW acceleration. |
6 | * |
7 | * Copyright (c) 2010 Nokia Corporation |
8 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> |
9 | * Copyright (c) 2011 Texas Instruments Incorporated |
10 | */ |
11 | |
12 | #define pr_fmt(fmt) "%20s: " fmt, __func__ |
13 | #define prn(num) pr_debug(#num "=%d\n", num) |
14 | #define prx(num) pr_debug(#num "=%x\n", num) |
15 | |
16 | #include <crypto/aes.h> |
17 | #include <crypto/gcm.h> |
18 | #include <crypto/internal/aead.h> |
19 | #include <crypto/internal/engine.h> |
20 | #include <crypto/internal/skcipher.h> |
21 | #include <crypto/scatterwalk.h> |
22 | #include <linux/dma-mapping.h> |
23 | #include <linux/dmaengine.h> |
24 | #include <linux/err.h> |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/io.h> |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> |
30 | #include <linux/of.h> |
31 | #include <linux/of_address.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/scatterlist.h> |
35 | #include <linux/string.h> |
36 | |
37 | #include "omap-crypto.h" |
38 | #include "omap-aes.h" |
39 | |
40 | /* keep registered devices data here */ |
41 | static LIST_HEAD(dev_list); |
42 | static DEFINE_SPINLOCK(list_lock); |
43 | |
44 | static int aes_fallback_sz = 200; |
45 | |
46 | #ifdef DEBUG |
47 | #define omap_aes_read(dd, offset) \ |
48 | ({ \ |
49 | int _read_ret; \ |
50 | _read_ret = __raw_readl(dd->io_base + offset); \ |
51 | pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ |
52 | offset, _read_ret); \ |
53 | _read_ret; \ |
54 | }) |
55 | #else |
56 | inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) |
57 | { |
58 | return __raw_readl(addr: dd->io_base + offset); |
59 | } |
60 | #endif |
61 | |
62 | #ifdef DEBUG |
63 | #define omap_aes_write(dd, offset, value) \ |
64 | do { \ |
65 | pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ |
66 | offset, value); \ |
67 | __raw_writel(value, dd->io_base + offset); \ |
68 | } while (0) |
69 | #else |
70 | inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, |
71 | u32 value) |
72 | { |
73 | __raw_writel(val: value, addr: dd->io_base + offset); |
74 | } |
75 | #endif |
76 | |
77 | static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, |
78 | u32 value, u32 mask) |
79 | { |
80 | u32 val; |
81 | |
82 | val = omap_aes_read(dd, offset); |
83 | val &= ~mask; |
84 | val |= value; |
85 | omap_aes_write(dd, offset, value: val); |
86 | } |
87 | |
88 | static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, |
89 | u32 *value, int count) |
90 | { |
91 | for (; count--; value++, offset += 4) |
92 | omap_aes_write(dd, offset, value: *value); |
93 | } |
94 | |
95 | static int omap_aes_hw_init(struct omap_aes_dev *dd) |
96 | { |
97 | int err; |
98 | |
99 | if (!(dd->flags & FLAGS_INIT)) { |
100 | dd->flags |= FLAGS_INIT; |
101 | dd->err = 0; |
102 | } |
103 | |
104 | err = pm_runtime_resume_and_get(dev: dd->dev); |
105 | if (err < 0) { |
106 | dev_err(dd->dev, "failed to get sync: %d\n" , err); |
107 | return err; |
108 | } |
109 | |
110 | return 0; |
111 | } |
112 | |
113 | void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) |
114 | { |
115 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); |
116 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); |
117 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); |
118 | } |
119 | |
120 | int omap_aes_write_ctrl(struct omap_aes_dev *dd) |
121 | { |
122 | struct omap_aes_reqctx *rctx; |
123 | unsigned int key32; |
124 | int i, err; |
125 | u32 val; |
126 | |
127 | err = omap_aes_hw_init(dd); |
128 | if (err) |
129 | return err; |
130 | |
131 | key32 = dd->ctx->keylen / sizeof(u32); |
132 | |
133 | /* RESET the key as previous HASH keys should not get affected*/ |
134 | if (dd->flags & FLAGS_GCM) |
135 | for (i = 0; i < 0x40; i = i + 4) |
136 | omap_aes_write(dd, offset: i, value: 0x0); |
137 | |
138 | for (i = 0; i < key32; i++) { |
139 | omap_aes_write(dd, AES_REG_KEY(dd, i), |
140 | value: (__force u32)cpu_to_le32(dd->ctx->key[i])); |
141 | } |
142 | |
143 | if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) |
144 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), value: (void *)dd->req->iv, count: 4); |
145 | |
146 | if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { |
147 | rctx = aead_request_ctx(req: dd->aead_req); |
148 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), value: (u32 *)rctx->iv, count: 4); |
149 | } |
150 | |
151 | val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); |
152 | if (dd->flags & FLAGS_CBC) |
153 | val |= AES_REG_CTRL_CBC; |
154 | |
155 | if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) |
156 | val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; |
157 | |
158 | if (dd->flags & FLAGS_GCM) |
159 | val |= AES_REG_CTRL_GCM; |
160 | |
161 | if (dd->flags & FLAGS_ENCRYPT) |
162 | val |= AES_REG_CTRL_DIRECTION; |
163 | |
164 | omap_aes_write_mask(dd, AES_REG_CTRL(dd), value: val, AES_REG_CTRL_MASK); |
165 | |
166 | return 0; |
167 | } |
168 | |
169 | static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) |
170 | { |
171 | u32 mask, val; |
172 | |
173 | val = dd->pdata->dma_start; |
174 | |
175 | if (dd->dma_lch_out != NULL) |
176 | val |= dd->pdata->dma_enable_out; |
177 | if (dd->dma_lch_in != NULL) |
178 | val |= dd->pdata->dma_enable_in; |
179 | |
180 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | |
181 | dd->pdata->dma_start; |
182 | |
183 | omap_aes_write_mask(dd, AES_REG_MASK(dd), value: val, mask); |
184 | |
185 | } |
186 | |
187 | static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) |
188 | { |
189 | omap_aes_write(dd, AES_REG_LENGTH_N(0), value: length); |
190 | omap_aes_write(dd, AES_REG_LENGTH_N(1), value: 0); |
191 | if (dd->flags & FLAGS_GCM) |
192 | omap_aes_write(dd, AES_REG_A_LEN, value: dd->assoc_len); |
193 | |
194 | omap_aes_dma_trigger_omap2(dd, length); |
195 | } |
196 | |
197 | static void omap_aes_dma_stop(struct omap_aes_dev *dd) |
198 | { |
199 | u32 mask; |
200 | |
201 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | |
202 | dd->pdata->dma_start; |
203 | |
204 | omap_aes_write_mask(dd, AES_REG_MASK(dd), value: 0, mask); |
205 | } |
206 | |
207 | struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) |
208 | { |
209 | struct omap_aes_dev *dd; |
210 | |
211 | spin_lock_bh(lock: &list_lock); |
212 | dd = list_first_entry(&dev_list, struct omap_aes_dev, list); |
213 | list_move_tail(list: &dd->list, head: &dev_list); |
214 | rctx->dd = dd; |
215 | spin_unlock_bh(lock: &list_lock); |
216 | |
217 | return dd; |
218 | } |
219 | |
220 | static void omap_aes_dma_out_callback(void *data) |
221 | { |
222 | struct omap_aes_dev *dd = data; |
223 | |
224 | /* dma_lch_out - completed */ |
225 | tasklet_schedule(t: &dd->done_task); |
226 | } |
227 | |
228 | static int omap_aes_dma_init(struct omap_aes_dev *dd) |
229 | { |
230 | int err; |
231 | |
232 | dd->dma_lch_out = NULL; |
233 | dd->dma_lch_in = NULL; |
234 | |
235 | dd->dma_lch_in = dma_request_chan(dev: dd->dev, name: "rx" ); |
236 | if (IS_ERR(ptr: dd->dma_lch_in)) { |
237 | dev_err(dd->dev, "Unable to request in DMA channel\n" ); |
238 | return PTR_ERR(ptr: dd->dma_lch_in); |
239 | } |
240 | |
241 | dd->dma_lch_out = dma_request_chan(dev: dd->dev, name: "tx" ); |
242 | if (IS_ERR(ptr: dd->dma_lch_out)) { |
243 | dev_err(dd->dev, "Unable to request out DMA channel\n" ); |
244 | err = PTR_ERR(ptr: dd->dma_lch_out); |
245 | goto err_dma_out; |
246 | } |
247 | |
248 | return 0; |
249 | |
250 | err_dma_out: |
251 | dma_release_channel(chan: dd->dma_lch_in); |
252 | |
253 | return err; |
254 | } |
255 | |
256 | static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) |
257 | { |
258 | if (dd->pio_only) |
259 | return; |
260 | |
261 | dma_release_channel(chan: dd->dma_lch_out); |
262 | dma_release_channel(chan: dd->dma_lch_in); |
263 | } |
264 | |
265 | static int omap_aes_crypt_dma(struct omap_aes_dev *dd, |
266 | struct scatterlist *in_sg, |
267 | struct scatterlist *out_sg, |
268 | int in_sg_len, int out_sg_len) |
269 | { |
270 | struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc; |
271 | struct dma_slave_config cfg; |
272 | int ret; |
273 | |
274 | if (dd->pio_only) { |
275 | scatterwalk_start(walk: &dd->in_walk, sg: dd->in_sg); |
276 | if (out_sg_len) |
277 | scatterwalk_start(walk: &dd->out_walk, sg: dd->out_sg); |
278 | |
279 | /* Enable DATAIN interrupt and let it take |
280 | care of the rest */ |
281 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), value: 0x2); |
282 | return 0; |
283 | } |
284 | |
285 | dma_sync_sg_for_device(dev: dd->dev, sg: dd->in_sg, nelems: in_sg_len, dir: DMA_TO_DEVICE); |
286 | |
287 | memset(&cfg, 0, sizeof(cfg)); |
288 | |
289 | cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); |
290 | cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); |
291 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
292 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
293 | cfg.src_maxburst = DST_MAXBURST; |
294 | cfg.dst_maxburst = DST_MAXBURST; |
295 | |
296 | /* IN */ |
297 | ret = dmaengine_slave_config(chan: dd->dma_lch_in, config: &cfg); |
298 | if (ret) { |
299 | dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n" , |
300 | ret); |
301 | return ret; |
302 | } |
303 | |
304 | tx_in = dmaengine_prep_slave_sg(chan: dd->dma_lch_in, sgl: in_sg, sg_len: in_sg_len, |
305 | dir: DMA_MEM_TO_DEV, |
306 | flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
307 | if (!tx_in) { |
308 | dev_err(dd->dev, "IN prep_slave_sg() failed\n" ); |
309 | return -EINVAL; |
310 | } |
311 | |
312 | /* No callback necessary */ |
313 | tx_in->callback_param = dd; |
314 | tx_in->callback = NULL; |
315 | |
316 | /* OUT */ |
317 | if (out_sg_len) { |
318 | ret = dmaengine_slave_config(chan: dd->dma_lch_out, config: &cfg); |
319 | if (ret) { |
320 | dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n" , |
321 | ret); |
322 | return ret; |
323 | } |
324 | |
325 | tx_out = dmaengine_prep_slave_sg(chan: dd->dma_lch_out, sgl: out_sg, |
326 | sg_len: out_sg_len, |
327 | dir: DMA_DEV_TO_MEM, |
328 | flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
329 | if (!tx_out) { |
330 | dev_err(dd->dev, "OUT prep_slave_sg() failed\n" ); |
331 | return -EINVAL; |
332 | } |
333 | |
334 | cb_desc = tx_out; |
335 | } else { |
336 | cb_desc = tx_in; |
337 | } |
338 | |
339 | if (dd->flags & FLAGS_GCM) |
340 | cb_desc->callback = omap_aes_gcm_dma_out_callback; |
341 | else |
342 | cb_desc->callback = omap_aes_dma_out_callback; |
343 | cb_desc->callback_param = dd; |
344 | |
345 | |
346 | dmaengine_submit(desc: tx_in); |
347 | if (tx_out) |
348 | dmaengine_submit(desc: tx_out); |
349 | |
350 | dma_async_issue_pending(chan: dd->dma_lch_in); |
351 | if (out_sg_len) |
352 | dma_async_issue_pending(chan: dd->dma_lch_out); |
353 | |
354 | /* start DMA */ |
355 | dd->pdata->trigger(dd, dd->total); |
356 | |
357 | return 0; |
358 | } |
359 | |
360 | int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) |
361 | { |
362 | int err; |
363 | |
364 | pr_debug("total: %zu\n" , dd->total); |
365 | |
366 | if (!dd->pio_only) { |
367 | err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, |
368 | DMA_TO_DEVICE); |
369 | if (!err) { |
370 | dev_err(dd->dev, "dma_map_sg() error\n" ); |
371 | return -EINVAL; |
372 | } |
373 | |
374 | if (dd->out_sg_len) { |
375 | err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, |
376 | DMA_FROM_DEVICE); |
377 | if (!err) { |
378 | dev_err(dd->dev, "dma_map_sg() error\n" ); |
379 | return -EINVAL; |
380 | } |
381 | } |
382 | } |
383 | |
384 | err = omap_aes_crypt_dma(dd, in_sg: dd->in_sg, out_sg: dd->out_sg, in_sg_len: dd->in_sg_len, |
385 | out_sg_len: dd->out_sg_len); |
386 | if (err && !dd->pio_only) { |
387 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
388 | if (dd->out_sg_len) |
389 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, |
390 | DMA_FROM_DEVICE); |
391 | } |
392 | |
393 | return err; |
394 | } |
395 | |
396 | static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) |
397 | { |
398 | struct skcipher_request *req = dd->req; |
399 | |
400 | pr_debug("err: %d\n" , err); |
401 | |
402 | crypto_finalize_skcipher_request(engine: dd->engine, req, err); |
403 | |
404 | pm_runtime_mark_last_busy(dev: dd->dev); |
405 | pm_runtime_put_autosuspend(dev: dd->dev); |
406 | } |
407 | |
408 | int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) |
409 | { |
410 | pr_debug("total: %zu\n" , dd->total); |
411 | |
412 | omap_aes_dma_stop(dd); |
413 | |
414 | |
415 | return 0; |
416 | } |
417 | |
418 | static int omap_aes_handle_queue(struct omap_aes_dev *dd, |
419 | struct skcipher_request *req) |
420 | { |
421 | if (req) |
422 | return crypto_transfer_skcipher_request_to_engine(engine: dd->engine, req); |
423 | |
424 | return 0; |
425 | } |
426 | |
427 | static int omap_aes_prepare_req(struct skcipher_request *req, |
428 | struct omap_aes_dev *dd) |
429 | { |
430 | struct omap_aes_ctx *ctx = crypto_skcipher_ctx( |
431 | tfm: crypto_skcipher_reqtfm(req)); |
432 | struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); |
433 | int ret; |
434 | u16 flags; |
435 | |
436 | /* assign new request to device */ |
437 | dd->req = req; |
438 | dd->total = req->cryptlen; |
439 | dd->total_save = req->cryptlen; |
440 | dd->in_sg = req->src; |
441 | dd->out_sg = req->dst; |
442 | dd->orig_out = req->dst; |
443 | |
444 | flags = OMAP_CRYPTO_COPY_DATA; |
445 | if (req->src == req->dst) |
446 | flags |= OMAP_CRYPTO_FORCE_COPY; |
447 | |
448 | ret = omap_crypto_align_sg(sg: &dd->in_sg, total: dd->total, AES_BLOCK_SIZE, |
449 | new_sg: dd->in_sgl, flags, |
450 | FLAGS_IN_DATA_ST_SHIFT, dd_flags: &dd->flags); |
451 | if (ret) |
452 | return ret; |
453 | |
454 | ret = omap_crypto_align_sg(sg: &dd->out_sg, total: dd->total, AES_BLOCK_SIZE, |
455 | new_sg: &dd->out_sgl, flags: 0, |
456 | FLAGS_OUT_DATA_ST_SHIFT, dd_flags: &dd->flags); |
457 | if (ret) |
458 | return ret; |
459 | |
460 | dd->in_sg_len = sg_nents_for_len(sg: dd->in_sg, len: dd->total); |
461 | if (dd->in_sg_len < 0) |
462 | return dd->in_sg_len; |
463 | |
464 | dd->out_sg_len = sg_nents_for_len(sg: dd->out_sg, len: dd->total); |
465 | if (dd->out_sg_len < 0) |
466 | return dd->out_sg_len; |
467 | |
468 | rctx->mode &= FLAGS_MODE_MASK; |
469 | dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; |
470 | |
471 | dd->ctx = ctx; |
472 | rctx->dd = dd; |
473 | |
474 | return omap_aes_write_ctrl(dd); |
475 | } |
476 | |
477 | static int omap_aes_crypt_req(struct crypto_engine *engine, |
478 | void *areq) |
479 | { |
480 | struct skcipher_request *req = container_of(areq, struct skcipher_request, base); |
481 | struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); |
482 | struct omap_aes_dev *dd = rctx->dd; |
483 | |
484 | if (!dd) |
485 | return -ENODEV; |
486 | |
487 | return omap_aes_prepare_req(req, dd) ?: |
488 | omap_aes_crypt_dma_start(dd); |
489 | } |
490 | |
491 | static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) |
492 | { |
493 | int i; |
494 | |
495 | for (i = 0; i < 4; i++) |
496 | ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); |
497 | } |
498 | |
499 | static void omap_aes_done_task(unsigned long data) |
500 | { |
501 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; |
502 | |
503 | pr_debug("enter done_task\n" ); |
504 | |
505 | if (!dd->pio_only) { |
506 | dma_sync_sg_for_device(dev: dd->dev, sg: dd->out_sg, nelems: dd->out_sg_len, |
507 | dir: DMA_FROM_DEVICE); |
508 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
509 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, |
510 | DMA_FROM_DEVICE); |
511 | omap_aes_crypt_dma_stop(dd); |
512 | } |
513 | |
514 | omap_crypto_cleanup(sg: dd->in_sg, NULL, offset: 0, len: dd->total_save, |
515 | FLAGS_IN_DATA_ST_SHIFT, flags: dd->flags); |
516 | |
517 | omap_crypto_cleanup(sg: dd->out_sg, orig: dd->orig_out, offset: 0, len: dd->total_save, |
518 | FLAGS_OUT_DATA_ST_SHIFT, flags: dd->flags); |
519 | |
520 | /* Update IV output */ |
521 | if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) |
522 | omap_aes_copy_ivout(dd, ivbuf: dd->req->iv); |
523 | |
524 | omap_aes_finish_req(dd, err: 0); |
525 | |
526 | pr_debug("exit\n" ); |
527 | } |
528 | |
529 | static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) |
530 | { |
531 | struct omap_aes_ctx *ctx = crypto_skcipher_ctx( |
532 | tfm: crypto_skcipher_reqtfm(req)); |
533 | struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); |
534 | struct omap_aes_dev *dd; |
535 | int ret; |
536 | |
537 | if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR)) |
538 | return -EINVAL; |
539 | |
540 | pr_debug("nbytes: %d, enc: %d, cbc: %d\n" , req->cryptlen, |
541 | !!(mode & FLAGS_ENCRYPT), |
542 | !!(mode & FLAGS_CBC)); |
543 | |
544 | if (req->cryptlen < aes_fallback_sz) { |
545 | skcipher_request_set_tfm(req: &rctx->fallback_req, tfm: ctx->fallback); |
546 | skcipher_request_set_callback(req: &rctx->fallback_req, |
547 | flags: req->base.flags, |
548 | compl: req->base.complete, |
549 | data: req->base.data); |
550 | skcipher_request_set_crypt(req: &rctx->fallback_req, src: req->src, |
551 | dst: req->dst, cryptlen: req->cryptlen, iv: req->iv); |
552 | |
553 | if (mode & FLAGS_ENCRYPT) |
554 | ret = crypto_skcipher_encrypt(req: &rctx->fallback_req); |
555 | else |
556 | ret = crypto_skcipher_decrypt(req: &rctx->fallback_req); |
557 | return ret; |
558 | } |
559 | dd = omap_aes_find_dev(rctx); |
560 | if (!dd) |
561 | return -ENODEV; |
562 | |
563 | rctx->mode = mode; |
564 | |
565 | return omap_aes_handle_queue(dd, req); |
566 | } |
567 | |
568 | /* ********************** ALG API ************************************ */ |
569 | |
570 | static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, |
571 | unsigned int keylen) |
572 | { |
573 | struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); |
574 | int ret; |
575 | |
576 | if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && |
577 | keylen != AES_KEYSIZE_256) |
578 | return -EINVAL; |
579 | |
580 | pr_debug("enter, keylen: %d\n" , keylen); |
581 | |
582 | memcpy(ctx->key, key, keylen); |
583 | ctx->keylen = keylen; |
584 | |
585 | crypto_skcipher_clear_flags(tfm: ctx->fallback, CRYPTO_TFM_REQ_MASK); |
586 | crypto_skcipher_set_flags(tfm: ctx->fallback, flags: tfm->base.crt_flags & |
587 | CRYPTO_TFM_REQ_MASK); |
588 | |
589 | ret = crypto_skcipher_setkey(tfm: ctx->fallback, key, keylen); |
590 | if (!ret) |
591 | return 0; |
592 | |
593 | return 0; |
594 | } |
595 | |
596 | static int omap_aes_ecb_encrypt(struct skcipher_request *req) |
597 | { |
598 | return omap_aes_crypt(req, FLAGS_ENCRYPT); |
599 | } |
600 | |
601 | static int omap_aes_ecb_decrypt(struct skcipher_request *req) |
602 | { |
603 | return omap_aes_crypt(req, mode: 0); |
604 | } |
605 | |
606 | static int omap_aes_cbc_encrypt(struct skcipher_request *req) |
607 | { |
608 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); |
609 | } |
610 | |
611 | static int omap_aes_cbc_decrypt(struct skcipher_request *req) |
612 | { |
613 | return omap_aes_crypt(req, FLAGS_CBC); |
614 | } |
615 | |
616 | static int omap_aes_ctr_encrypt(struct skcipher_request *req) |
617 | { |
618 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); |
619 | } |
620 | |
621 | static int omap_aes_ctr_decrypt(struct skcipher_request *req) |
622 | { |
623 | return omap_aes_crypt(req, FLAGS_CTR); |
624 | } |
625 | |
626 | static int omap_aes_init_tfm(struct crypto_skcipher *tfm) |
627 | { |
628 | const char *name = crypto_tfm_alg_name(tfm: &tfm->base); |
629 | struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); |
630 | struct crypto_skcipher *blk; |
631 | |
632 | blk = crypto_alloc_skcipher(alg_name: name, type: 0, CRYPTO_ALG_NEED_FALLBACK); |
633 | if (IS_ERR(ptr: blk)) |
634 | return PTR_ERR(ptr: blk); |
635 | |
636 | ctx->fallback = blk; |
637 | |
638 | crypto_skcipher_set_reqsize(skcipher: tfm, reqsize: sizeof(struct omap_aes_reqctx) + |
639 | crypto_skcipher_reqsize(tfm: blk)); |
640 | |
641 | return 0; |
642 | } |
643 | |
644 | static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) |
645 | { |
646 | struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); |
647 | |
648 | if (ctx->fallback) |
649 | crypto_free_skcipher(tfm: ctx->fallback); |
650 | |
651 | ctx->fallback = NULL; |
652 | } |
653 | |
654 | /* ********************** ALGS ************************************ */ |
655 | |
656 | static struct skcipher_engine_alg algs_ecb_cbc[] = { |
657 | { |
658 | .base = { |
659 | .base.cra_name = "ecb(aes)" , |
660 | .base.cra_driver_name = "ecb-aes-omap" , |
661 | .base.cra_priority = 300, |
662 | .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
663 | CRYPTO_ALG_ASYNC | |
664 | CRYPTO_ALG_NEED_FALLBACK, |
665 | .base.cra_blocksize = AES_BLOCK_SIZE, |
666 | .base.cra_ctxsize = sizeof(struct omap_aes_ctx), |
667 | .base.cra_module = THIS_MODULE, |
668 | |
669 | .min_keysize = AES_MIN_KEY_SIZE, |
670 | .max_keysize = AES_MAX_KEY_SIZE, |
671 | .setkey = omap_aes_setkey, |
672 | .encrypt = omap_aes_ecb_encrypt, |
673 | .decrypt = omap_aes_ecb_decrypt, |
674 | .init = omap_aes_init_tfm, |
675 | .exit = omap_aes_exit_tfm, |
676 | }, |
677 | .op.do_one_request = omap_aes_crypt_req, |
678 | }, |
679 | { |
680 | .base = { |
681 | .base.cra_name = "cbc(aes)" , |
682 | .base.cra_driver_name = "cbc-aes-omap" , |
683 | .base.cra_priority = 300, |
684 | .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
685 | CRYPTO_ALG_ASYNC | |
686 | CRYPTO_ALG_NEED_FALLBACK, |
687 | .base.cra_blocksize = AES_BLOCK_SIZE, |
688 | .base.cra_ctxsize = sizeof(struct omap_aes_ctx), |
689 | .base.cra_module = THIS_MODULE, |
690 | |
691 | .min_keysize = AES_MIN_KEY_SIZE, |
692 | .max_keysize = AES_MAX_KEY_SIZE, |
693 | .ivsize = AES_BLOCK_SIZE, |
694 | .setkey = omap_aes_setkey, |
695 | .encrypt = omap_aes_cbc_encrypt, |
696 | .decrypt = omap_aes_cbc_decrypt, |
697 | .init = omap_aes_init_tfm, |
698 | .exit = omap_aes_exit_tfm, |
699 | }, |
700 | .op.do_one_request = omap_aes_crypt_req, |
701 | } |
702 | }; |
703 | |
704 | static struct skcipher_engine_alg algs_ctr[] = { |
705 | { |
706 | .base = { |
707 | .base.cra_name = "ctr(aes)" , |
708 | .base.cra_driver_name = "ctr-aes-omap" , |
709 | .base.cra_priority = 300, |
710 | .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
711 | CRYPTO_ALG_ASYNC | |
712 | CRYPTO_ALG_NEED_FALLBACK, |
713 | .base.cra_blocksize = 1, |
714 | .base.cra_ctxsize = sizeof(struct omap_aes_ctx), |
715 | .base.cra_module = THIS_MODULE, |
716 | |
717 | .min_keysize = AES_MIN_KEY_SIZE, |
718 | .max_keysize = AES_MAX_KEY_SIZE, |
719 | .ivsize = AES_BLOCK_SIZE, |
720 | .setkey = omap_aes_setkey, |
721 | .encrypt = omap_aes_ctr_encrypt, |
722 | .decrypt = omap_aes_ctr_decrypt, |
723 | .init = omap_aes_init_tfm, |
724 | .exit = omap_aes_exit_tfm, |
725 | }, |
726 | .op.do_one_request = omap_aes_crypt_req, |
727 | } |
728 | }; |
729 | |
730 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { |
731 | { |
732 | .algs_list = algs_ecb_cbc, |
733 | .size = ARRAY_SIZE(algs_ecb_cbc), |
734 | }, |
735 | }; |
736 | |
737 | static struct aead_engine_alg algs_aead_gcm[] = { |
738 | { |
739 | .base = { |
740 | .base = { |
741 | .cra_name = "gcm(aes)" , |
742 | .cra_driver_name = "gcm-aes-omap" , |
743 | .cra_priority = 300, |
744 | .cra_flags = CRYPTO_ALG_ASYNC | |
745 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
746 | .cra_blocksize = 1, |
747 | .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), |
748 | .cra_alignmask = 0xf, |
749 | .cra_module = THIS_MODULE, |
750 | }, |
751 | .init = omap_aes_gcm_cra_init, |
752 | .ivsize = GCM_AES_IV_SIZE, |
753 | .maxauthsize = AES_BLOCK_SIZE, |
754 | .setkey = omap_aes_gcm_setkey, |
755 | .setauthsize = omap_aes_gcm_setauthsize, |
756 | .encrypt = omap_aes_gcm_encrypt, |
757 | .decrypt = omap_aes_gcm_decrypt, |
758 | }, |
759 | .op.do_one_request = omap_aes_gcm_crypt_req, |
760 | }, |
761 | { |
762 | .base = { |
763 | .base = { |
764 | .cra_name = "rfc4106(gcm(aes))" , |
765 | .cra_driver_name = "rfc4106-gcm-aes-omap" , |
766 | .cra_priority = 300, |
767 | .cra_flags = CRYPTO_ALG_ASYNC | |
768 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
769 | .cra_blocksize = 1, |
770 | .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), |
771 | .cra_alignmask = 0xf, |
772 | .cra_module = THIS_MODULE, |
773 | }, |
774 | .init = omap_aes_gcm_cra_init, |
775 | .maxauthsize = AES_BLOCK_SIZE, |
776 | .ivsize = GCM_RFC4106_IV_SIZE, |
777 | .setkey = omap_aes_4106gcm_setkey, |
778 | .setauthsize = omap_aes_4106gcm_setauthsize, |
779 | .encrypt = omap_aes_4106gcm_encrypt, |
780 | .decrypt = omap_aes_4106gcm_decrypt, |
781 | }, |
782 | .op.do_one_request = omap_aes_gcm_crypt_req, |
783 | }, |
784 | }; |
785 | |
786 | static struct omap_aes_aead_algs omap_aes_aead_info = { |
787 | .algs_list = algs_aead_gcm, |
788 | .size = ARRAY_SIZE(algs_aead_gcm), |
789 | }; |
790 | |
791 | static const struct omap_aes_pdata omap_aes_pdata_omap2 = { |
792 | .algs_info = omap_aes_algs_info_ecb_cbc, |
793 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), |
794 | .trigger = omap_aes_dma_trigger_omap2, |
795 | .key_ofs = 0x1c, |
796 | .iv_ofs = 0x20, |
797 | .ctrl_ofs = 0x30, |
798 | .data_ofs = 0x34, |
799 | .rev_ofs = 0x44, |
800 | .mask_ofs = 0x48, |
801 | .dma_enable_in = BIT(2), |
802 | .dma_enable_out = BIT(3), |
803 | .dma_start = BIT(5), |
804 | .major_mask = 0xf0, |
805 | .major_shift = 4, |
806 | .minor_mask = 0x0f, |
807 | .minor_shift = 0, |
808 | }; |
809 | |
810 | #ifdef CONFIG_OF |
811 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { |
812 | { |
813 | .algs_list = algs_ecb_cbc, |
814 | .size = ARRAY_SIZE(algs_ecb_cbc), |
815 | }, |
816 | { |
817 | .algs_list = algs_ctr, |
818 | .size = ARRAY_SIZE(algs_ctr), |
819 | }, |
820 | }; |
821 | |
822 | static const struct omap_aes_pdata omap_aes_pdata_omap3 = { |
823 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, |
824 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), |
825 | .trigger = omap_aes_dma_trigger_omap2, |
826 | .key_ofs = 0x1c, |
827 | .iv_ofs = 0x20, |
828 | .ctrl_ofs = 0x30, |
829 | .data_ofs = 0x34, |
830 | .rev_ofs = 0x44, |
831 | .mask_ofs = 0x48, |
832 | .dma_enable_in = BIT(2), |
833 | .dma_enable_out = BIT(3), |
834 | .dma_start = BIT(5), |
835 | .major_mask = 0xf0, |
836 | .major_shift = 4, |
837 | .minor_mask = 0x0f, |
838 | .minor_shift = 0, |
839 | }; |
840 | |
841 | static const struct omap_aes_pdata omap_aes_pdata_omap4 = { |
842 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, |
843 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), |
844 | .aead_algs_info = &omap_aes_aead_info, |
845 | .trigger = omap_aes_dma_trigger_omap4, |
846 | .key_ofs = 0x3c, |
847 | .iv_ofs = 0x40, |
848 | .ctrl_ofs = 0x50, |
849 | .data_ofs = 0x60, |
850 | .rev_ofs = 0x80, |
851 | .mask_ofs = 0x84, |
852 | .irq_status_ofs = 0x8c, |
853 | .irq_enable_ofs = 0x90, |
854 | .dma_enable_in = BIT(5), |
855 | .dma_enable_out = BIT(6), |
856 | .major_mask = 0x0700, |
857 | .major_shift = 8, |
858 | .minor_mask = 0x003f, |
859 | .minor_shift = 0, |
860 | }; |
861 | |
862 | static irqreturn_t omap_aes_irq(int irq, void *dev_id) |
863 | { |
864 | struct omap_aes_dev *dd = dev_id; |
865 | u32 status, i; |
866 | u32 *src, *dst; |
867 | |
868 | status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); |
869 | if (status & AES_REG_IRQ_DATA_IN) { |
870 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), value: 0x0); |
871 | |
872 | BUG_ON(!dd->in_sg); |
873 | |
874 | BUG_ON(_calc_walked(in) > dd->in_sg->length); |
875 | |
876 | src = sg_virt(sg: dd->in_sg) + _calc_walked(in); |
877 | |
878 | for (i = 0; i < AES_BLOCK_WORDS; i++) { |
879 | omap_aes_write(dd, AES_REG_DATA_N(dd, i), value: *src); |
880 | |
881 | scatterwalk_advance(walk: &dd->in_walk, nbytes: 4); |
882 | if (dd->in_sg->length == _calc_walked(in)) { |
883 | dd->in_sg = sg_next(dd->in_sg); |
884 | if (dd->in_sg) { |
885 | scatterwalk_start(walk: &dd->in_walk, |
886 | sg: dd->in_sg); |
887 | src = sg_virt(sg: dd->in_sg) + |
888 | _calc_walked(in); |
889 | } |
890 | } else { |
891 | src++; |
892 | } |
893 | } |
894 | |
895 | /* Clear IRQ status */ |
896 | status &= ~AES_REG_IRQ_DATA_IN; |
897 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), value: status); |
898 | |
899 | /* Enable DATA_OUT interrupt */ |
900 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), value: 0x4); |
901 | |
902 | } else if (status & AES_REG_IRQ_DATA_OUT) { |
903 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), value: 0x0); |
904 | |
905 | BUG_ON(!dd->out_sg); |
906 | |
907 | BUG_ON(_calc_walked(out) > dd->out_sg->length); |
908 | |
909 | dst = sg_virt(sg: dd->out_sg) + _calc_walked(out); |
910 | |
911 | for (i = 0; i < AES_BLOCK_WORDS; i++) { |
912 | *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); |
913 | scatterwalk_advance(walk: &dd->out_walk, nbytes: 4); |
914 | if (dd->out_sg->length == _calc_walked(out)) { |
915 | dd->out_sg = sg_next(dd->out_sg); |
916 | if (dd->out_sg) { |
917 | scatterwalk_start(walk: &dd->out_walk, |
918 | sg: dd->out_sg); |
919 | dst = sg_virt(sg: dd->out_sg) + |
920 | _calc_walked(out); |
921 | } |
922 | } else { |
923 | dst++; |
924 | } |
925 | } |
926 | |
927 | dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); |
928 | |
929 | /* Clear IRQ status */ |
930 | status &= ~AES_REG_IRQ_DATA_OUT; |
931 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), value: status); |
932 | |
933 | if (!dd->total) |
934 | /* All bytes read! */ |
935 | tasklet_schedule(t: &dd->done_task); |
936 | else |
937 | /* Enable DATA_IN interrupt for next block */ |
938 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), value: 0x2); |
939 | } |
940 | |
941 | return IRQ_HANDLED; |
942 | } |
943 | |
944 | static const struct of_device_id omap_aes_of_match[] = { |
945 | { |
946 | .compatible = "ti,omap2-aes" , |
947 | .data = &omap_aes_pdata_omap2, |
948 | }, |
949 | { |
950 | .compatible = "ti,omap3-aes" , |
951 | .data = &omap_aes_pdata_omap3, |
952 | }, |
953 | { |
954 | .compatible = "ti,omap4-aes" , |
955 | .data = &omap_aes_pdata_omap4, |
956 | }, |
957 | {}, |
958 | }; |
959 | MODULE_DEVICE_TABLE(of, omap_aes_of_match); |
960 | |
961 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, |
962 | struct device *dev, struct resource *res) |
963 | { |
964 | struct device_node *node = dev->of_node; |
965 | int err = 0; |
966 | |
967 | dd->pdata = of_device_get_match_data(dev); |
968 | if (!dd->pdata) { |
969 | dev_err(dev, "no compatible OF match\n" ); |
970 | err = -EINVAL; |
971 | goto err; |
972 | } |
973 | |
974 | err = of_address_to_resource(dev: node, index: 0, r: res); |
975 | if (err < 0) { |
976 | dev_err(dev, "can't translate OF node address\n" ); |
977 | err = -EINVAL; |
978 | goto err; |
979 | } |
980 | |
981 | err: |
982 | return err; |
983 | } |
984 | #else |
985 | static const struct of_device_id omap_aes_of_match[] = { |
986 | {}, |
987 | }; |
988 | |
989 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, |
990 | struct device *dev, struct resource *res) |
991 | { |
992 | return -EINVAL; |
993 | } |
994 | #endif |
995 | |
996 | static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, |
997 | struct platform_device *pdev, struct resource *res) |
998 | { |
999 | struct device *dev = &pdev->dev; |
1000 | struct resource *r; |
1001 | int err = 0; |
1002 | |
1003 | /* Get the base address */ |
1004 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1005 | if (!r) { |
1006 | dev_err(dev, "no MEM resource info\n" ); |
1007 | err = -ENODEV; |
1008 | goto err; |
1009 | } |
1010 | memcpy(res, r, sizeof(*res)); |
1011 | |
1012 | /* Only OMAP2/3 can be non-DT */ |
1013 | dd->pdata = &omap_aes_pdata_omap2; |
1014 | |
1015 | err: |
1016 | return err; |
1017 | } |
1018 | |
1019 | static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, |
1020 | char *buf) |
1021 | { |
1022 | return sprintf(buf, fmt: "%d\n" , aes_fallback_sz); |
1023 | } |
1024 | |
1025 | static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, |
1026 | const char *buf, size_t size) |
1027 | { |
1028 | ssize_t status; |
1029 | long value; |
1030 | |
1031 | status = kstrtol(s: buf, base: 0, res: &value); |
1032 | if (status) |
1033 | return status; |
1034 | |
1035 | /* HW accelerator only works with buffers > 9 */ |
1036 | if (value < 9) { |
1037 | dev_err(dev, "minimum fallback size 9\n" ); |
1038 | return -EINVAL; |
1039 | } |
1040 | |
1041 | aes_fallback_sz = value; |
1042 | |
1043 | return size; |
1044 | } |
1045 | |
1046 | static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, |
1047 | char *buf) |
1048 | { |
1049 | struct omap_aes_dev *dd = dev_get_drvdata(dev); |
1050 | |
1051 | return sprintf(buf, fmt: "%d\n" , dd->engine->queue.max_qlen); |
1052 | } |
1053 | |
1054 | static ssize_t queue_len_store(struct device *dev, |
1055 | struct device_attribute *attr, const char *buf, |
1056 | size_t size) |
1057 | { |
1058 | struct omap_aes_dev *dd; |
1059 | ssize_t status; |
1060 | long value; |
1061 | unsigned long flags; |
1062 | |
1063 | status = kstrtol(s: buf, base: 0, res: &value); |
1064 | if (status) |
1065 | return status; |
1066 | |
1067 | if (value < 1) |
1068 | return -EINVAL; |
1069 | |
1070 | /* |
1071 | * Changing the queue size in fly is safe, if size becomes smaller |
1072 | * than current size, it will just not accept new entries until |
1073 | * it has shrank enough. |
1074 | */ |
1075 | spin_lock_bh(lock: &list_lock); |
1076 | list_for_each_entry(dd, &dev_list, list) { |
1077 | spin_lock_irqsave(&dd->lock, flags); |
1078 | dd->engine->queue.max_qlen = value; |
1079 | dd->aead_queue.base.max_qlen = value; |
1080 | spin_unlock_irqrestore(lock: &dd->lock, flags); |
1081 | } |
1082 | spin_unlock_bh(lock: &list_lock); |
1083 | |
1084 | return size; |
1085 | } |
1086 | |
1087 | static DEVICE_ATTR_RW(queue_len); |
1088 | static DEVICE_ATTR_RW(fallback); |
1089 | |
1090 | static struct attribute *omap_aes_attrs[] = { |
1091 | &dev_attr_queue_len.attr, |
1092 | &dev_attr_fallback.attr, |
1093 | NULL, |
1094 | }; |
1095 | |
1096 | static const struct attribute_group omap_aes_attr_group = { |
1097 | .attrs = omap_aes_attrs, |
1098 | }; |
1099 | |
1100 | static int omap_aes_probe(struct platform_device *pdev) |
1101 | { |
1102 | struct device *dev = &pdev->dev; |
1103 | struct omap_aes_dev *dd; |
1104 | struct skcipher_engine_alg *algp; |
1105 | struct aead_engine_alg *aalg; |
1106 | struct resource res; |
1107 | int err = -ENOMEM, i, j, irq = -1; |
1108 | u32 reg; |
1109 | |
1110 | dd = devm_kzalloc(dev, size: sizeof(struct omap_aes_dev), GFP_KERNEL); |
1111 | if (dd == NULL) { |
1112 | dev_err(dev, "unable to alloc data struct.\n" ); |
1113 | goto err_data; |
1114 | } |
1115 | dd->dev = dev; |
1116 | platform_set_drvdata(pdev, data: dd); |
1117 | |
1118 | aead_init_queue(queue: &dd->aead_queue, OMAP_AES_QUEUE_LENGTH); |
1119 | |
1120 | err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, res: &res) : |
1121 | omap_aes_get_res_pdev(dd, pdev, res: &res); |
1122 | if (err) |
1123 | goto err_res; |
1124 | |
1125 | dd->io_base = devm_ioremap_resource(dev, res: &res); |
1126 | if (IS_ERR(ptr: dd->io_base)) { |
1127 | err = PTR_ERR(ptr: dd->io_base); |
1128 | goto err_res; |
1129 | } |
1130 | dd->phys_base = res.start; |
1131 | |
1132 | pm_runtime_use_autosuspend(dev); |
1133 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); |
1134 | |
1135 | pm_runtime_enable(dev); |
1136 | err = pm_runtime_resume_and_get(dev); |
1137 | if (err < 0) { |
1138 | dev_err(dev, "%s: failed to get_sync(%d)\n" , |
1139 | __func__, err); |
1140 | goto err_pm_disable; |
1141 | } |
1142 | |
1143 | omap_aes_dma_stop(dd); |
1144 | |
1145 | reg = omap_aes_read(dd, AES_REG_REV(dd)); |
1146 | |
1147 | pm_runtime_put_sync(dev); |
1148 | |
1149 | dev_info(dev, "OMAP AES hw accel rev: %u.%u\n" , |
1150 | (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, |
1151 | (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); |
1152 | |
1153 | tasklet_init(t: &dd->done_task, func: omap_aes_done_task, data: (unsigned long)dd); |
1154 | |
1155 | err = omap_aes_dma_init(dd); |
1156 | if (err == -EPROBE_DEFER) { |
1157 | goto err_irq; |
1158 | } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { |
1159 | dd->pio_only = 1; |
1160 | |
1161 | irq = platform_get_irq(pdev, 0); |
1162 | if (irq < 0) { |
1163 | err = irq; |
1164 | goto err_irq; |
1165 | } |
1166 | |
1167 | err = devm_request_irq(dev, irq, handler: omap_aes_irq, irqflags: 0, |
1168 | devname: dev_name(dev), dev_id: dd); |
1169 | if (err) { |
1170 | dev_err(dev, "Unable to grab omap-aes IRQ\n" ); |
1171 | goto err_irq; |
1172 | } |
1173 | } |
1174 | |
1175 | spin_lock_init(&dd->lock); |
1176 | |
1177 | INIT_LIST_HEAD(list: &dd->list); |
1178 | spin_lock_bh(lock: &list_lock); |
1179 | list_add_tail(new: &dd->list, head: &dev_list); |
1180 | spin_unlock_bh(lock: &list_lock); |
1181 | |
1182 | /* Initialize crypto engine */ |
1183 | dd->engine = crypto_engine_alloc_init(dev, rt: 1); |
1184 | if (!dd->engine) { |
1185 | err = -ENOMEM; |
1186 | goto err_engine; |
1187 | } |
1188 | |
1189 | err = crypto_engine_start(engine: dd->engine); |
1190 | if (err) |
1191 | goto err_engine; |
1192 | |
1193 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
1194 | if (!dd->pdata->algs_info[i].registered) { |
1195 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { |
1196 | algp = &dd->pdata->algs_info[i].algs_list[j]; |
1197 | |
1198 | pr_debug("reg alg: %s\n" , algp->base.base.cra_name); |
1199 | |
1200 | err = crypto_engine_register_skcipher(alg: algp); |
1201 | if (err) |
1202 | goto err_algs; |
1203 | |
1204 | dd->pdata->algs_info[i].registered++; |
1205 | } |
1206 | } |
1207 | } |
1208 | |
1209 | if (dd->pdata->aead_algs_info && |
1210 | !dd->pdata->aead_algs_info->registered) { |
1211 | for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { |
1212 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; |
1213 | |
1214 | pr_debug("reg alg: %s\n" , aalg->base.base.cra_name); |
1215 | |
1216 | err = crypto_engine_register_aead(alg: aalg); |
1217 | if (err) |
1218 | goto err_aead_algs; |
1219 | |
1220 | dd->pdata->aead_algs_info->registered++; |
1221 | } |
1222 | } |
1223 | |
1224 | err = sysfs_create_group(kobj: &dev->kobj, grp: &omap_aes_attr_group); |
1225 | if (err) { |
1226 | dev_err(dev, "could not create sysfs device attrs\n" ); |
1227 | goto err_aead_algs; |
1228 | } |
1229 | |
1230 | return 0; |
1231 | err_aead_algs: |
1232 | for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { |
1233 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; |
1234 | crypto_engine_unregister_aead(alg: aalg); |
1235 | } |
1236 | err_algs: |
1237 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1238 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) |
1239 | crypto_engine_unregister_skcipher( |
1240 | alg: &dd->pdata->algs_info[i].algs_list[j]); |
1241 | |
1242 | err_engine: |
1243 | if (dd->engine) |
1244 | crypto_engine_exit(engine: dd->engine); |
1245 | |
1246 | omap_aes_dma_cleanup(dd); |
1247 | err_irq: |
1248 | tasklet_kill(t: &dd->done_task); |
1249 | err_pm_disable: |
1250 | pm_runtime_disable(dev); |
1251 | err_res: |
1252 | dd = NULL; |
1253 | err_data: |
1254 | dev_err(dev, "initialization failed.\n" ); |
1255 | return err; |
1256 | } |
1257 | |
1258 | static void omap_aes_remove(struct platform_device *pdev) |
1259 | { |
1260 | struct omap_aes_dev *dd = platform_get_drvdata(pdev); |
1261 | struct aead_engine_alg *aalg; |
1262 | int i, j; |
1263 | |
1264 | spin_lock_bh(lock: &list_lock); |
1265 | list_del(entry: &dd->list); |
1266 | spin_unlock_bh(lock: &list_lock); |
1267 | |
1268 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1269 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { |
1270 | crypto_engine_unregister_skcipher( |
1271 | alg: &dd->pdata->algs_info[i].algs_list[j]); |
1272 | dd->pdata->algs_info[i].registered--; |
1273 | } |
1274 | |
1275 | for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { |
1276 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; |
1277 | crypto_engine_unregister_aead(alg: aalg); |
1278 | dd->pdata->aead_algs_info->registered--; |
1279 | } |
1280 | |
1281 | crypto_engine_exit(engine: dd->engine); |
1282 | |
1283 | tasklet_kill(t: &dd->done_task); |
1284 | omap_aes_dma_cleanup(dd); |
1285 | pm_runtime_disable(dev: dd->dev); |
1286 | |
1287 | sysfs_remove_group(kobj: &dd->dev->kobj, grp: &omap_aes_attr_group); |
1288 | } |
1289 | |
1290 | #ifdef CONFIG_PM_SLEEP |
1291 | static int omap_aes_suspend(struct device *dev) |
1292 | { |
1293 | pm_runtime_put_sync(dev); |
1294 | return 0; |
1295 | } |
1296 | |
1297 | static int omap_aes_resume(struct device *dev) |
1298 | { |
1299 | pm_runtime_get_sync(dev); |
1300 | return 0; |
1301 | } |
1302 | #endif |
1303 | |
1304 | static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); |
1305 | |
1306 | static struct platform_driver omap_aes_driver = { |
1307 | .probe = omap_aes_probe, |
1308 | .remove_new = omap_aes_remove, |
1309 | .driver = { |
1310 | .name = "omap-aes" , |
1311 | .pm = &omap_aes_pm_ops, |
1312 | .of_match_table = omap_aes_of_match, |
1313 | }, |
1314 | }; |
1315 | |
1316 | module_platform_driver(omap_aes_driver); |
1317 | |
1318 | MODULE_DESCRIPTION("OMAP AES hw acceleration support." ); |
1319 | MODULE_LICENSE("GPL v2" ); |
1320 | MODULE_AUTHOR("Dmitry Kasatkin" ); |
1321 | |
1322 | |