1/*
2 * Driver for the Analog Devices AXI-DMAC core
3 *
4 * Copyright 2013-2015 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/err.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_dma.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23
24#include <dt-bindings/dma/axi-dmac.h>
25
26#include "dmaengine.h"
27#include "virt-dma.h"
28
29/*
30 * The AXI-DMAC is a soft IP core that is used in FPGA designs. The core has
31 * various instantiation parameters which decided the exact feature set support
32 * by the core.
33 *
34 * Each channel of the core has a source interface and a destination interface.
35 * The number of channels and the type of the channel interfaces is selected at
36 * configuration time. A interface can either be a connected to a central memory
37 * interconnect, which allows access to system memory, or it can be connected to
38 * a dedicated bus which is directly connected to a data port on a peripheral.
39 * Given that those are configuration options of the core that are selected when
40 * it is instantiated this means that they can not be changed by software at
41 * runtime. By extension this means that each channel is uni-directional. It can
42 * either be device to memory or memory to device, but not both. Also since the
43 * device side is a dedicated data bus only connected to a single peripheral
44 * there is no address than can or needs to be configured for the device side.
45 */
46
47#define AXI_DMAC_REG_IRQ_MASK 0x80
48#define AXI_DMAC_REG_IRQ_PENDING 0x84
49#define AXI_DMAC_REG_IRQ_SOURCE 0x88
50
51#define AXI_DMAC_REG_CTRL 0x400
52#define AXI_DMAC_REG_TRANSFER_ID 0x404
53#define AXI_DMAC_REG_START_TRANSFER 0x408
54#define AXI_DMAC_REG_FLAGS 0x40c
55#define AXI_DMAC_REG_DEST_ADDRESS 0x410
56#define AXI_DMAC_REG_SRC_ADDRESS 0x414
57#define AXI_DMAC_REG_X_LENGTH 0x418
58#define AXI_DMAC_REG_Y_LENGTH 0x41c
59#define AXI_DMAC_REG_DEST_STRIDE 0x420
60#define AXI_DMAC_REG_SRC_STRIDE 0x424
61#define AXI_DMAC_REG_TRANSFER_DONE 0x428
62#define AXI_DMAC_REG_ACTIVE_TRANSFER_ID 0x42c
63#define AXI_DMAC_REG_STATUS 0x430
64#define AXI_DMAC_REG_CURRENT_SRC_ADDR 0x434
65#define AXI_DMAC_REG_CURRENT_DEST_ADDR 0x438
66
67#define AXI_DMAC_CTRL_ENABLE BIT(0)
68#define AXI_DMAC_CTRL_PAUSE BIT(1)
69
70#define AXI_DMAC_IRQ_SOT BIT(0)
71#define AXI_DMAC_IRQ_EOT BIT(1)
72
73#define AXI_DMAC_FLAG_CYCLIC BIT(0)
74
75/* The maximum ID allocated by the hardware is 31 */
76#define AXI_DMAC_SG_UNUSED 32U
77
78struct axi_dmac_sg {
79 dma_addr_t src_addr;
80 dma_addr_t dest_addr;
81 unsigned int x_len;
82 unsigned int y_len;
83 unsigned int dest_stride;
84 unsigned int src_stride;
85 unsigned int id;
86 bool schedule_when_free;
87};
88
89struct axi_dmac_desc {
90 struct virt_dma_desc vdesc;
91 bool cyclic;
92
93 unsigned int num_submitted;
94 unsigned int num_completed;
95 unsigned int num_sgs;
96 struct axi_dmac_sg sg[];
97};
98
99struct axi_dmac_chan {
100 struct virt_dma_chan vchan;
101
102 struct axi_dmac_desc *next_desc;
103 struct list_head active_descs;
104 enum dma_transfer_direction direction;
105
106 unsigned int src_width;
107 unsigned int dest_width;
108 unsigned int src_type;
109 unsigned int dest_type;
110
111 unsigned int max_length;
112 unsigned int align_mask;
113
114 bool hw_cyclic;
115 bool hw_2d;
116};
117
118struct axi_dmac {
119 void __iomem *base;
120 int irq;
121
122 struct clk *clk;
123
124 struct dma_device dma_dev;
125 struct axi_dmac_chan chan;
126
127 struct device_dma_parameters dma_parms;
128};
129
130static struct axi_dmac *chan_to_axi_dmac(struct axi_dmac_chan *chan)
131{
132 return container_of(chan->vchan.chan.device, struct axi_dmac,
133 dma_dev);
134}
135
136static struct axi_dmac_chan *to_axi_dmac_chan(struct dma_chan *c)
137{
138 return container_of(c, struct axi_dmac_chan, vchan.chan);
139}
140
141static struct axi_dmac_desc *to_axi_dmac_desc(struct virt_dma_desc *vdesc)
142{
143 return container_of(vdesc, struct axi_dmac_desc, vdesc);
144}
145
146static void axi_dmac_write(struct axi_dmac *axi_dmac, unsigned int reg,
147 unsigned int val)
148{
149 writel(val, axi_dmac->base + reg);
150}
151
152static int axi_dmac_read(struct axi_dmac *axi_dmac, unsigned int reg)
153{
154 return readl(axi_dmac->base + reg);
155}
156
157static int axi_dmac_src_is_mem(struct axi_dmac_chan *chan)
158{
159 return chan->src_type == AXI_DMAC_BUS_TYPE_AXI_MM;
160}
161
162static int axi_dmac_dest_is_mem(struct axi_dmac_chan *chan)
163{
164 return chan->dest_type == AXI_DMAC_BUS_TYPE_AXI_MM;
165}
166
167static bool axi_dmac_check_len(struct axi_dmac_chan *chan, unsigned int len)
168{
169 if (len == 0 || len > chan->max_length)
170 return false;
171 if ((len & chan->align_mask) != 0) /* Not aligned */
172 return false;
173 return true;
174}
175
176static bool axi_dmac_check_addr(struct axi_dmac_chan *chan, dma_addr_t addr)
177{
178 if ((addr & chan->align_mask) != 0) /* Not aligned */
179 return false;
180 return true;
181}
182
183static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
184{
185 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
186 struct virt_dma_desc *vdesc;
187 struct axi_dmac_desc *desc;
188 struct axi_dmac_sg *sg;
189 unsigned int flags = 0;
190 unsigned int val;
191
192 val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);
193 if (val) /* Queue is full, wait for the next SOT IRQ */
194 return;
195
196 desc = chan->next_desc;
197
198 if (!desc) {
199 vdesc = vchan_next_desc(&chan->vchan);
200 if (!vdesc)
201 return;
202 list_move_tail(&vdesc->node, &chan->active_descs);
203 desc = to_axi_dmac_desc(vdesc);
204 }
205 sg = &desc->sg[desc->num_submitted];
206
207 /* Already queued in cyclic mode. Wait for it to finish */
208 if (sg->id != AXI_DMAC_SG_UNUSED) {
209 sg->schedule_when_free = true;
210 return;
211 }
212
213 desc->num_submitted++;
214 if (desc->num_submitted == desc->num_sgs) {
215 if (desc->cyclic)
216 desc->num_submitted = 0; /* Start again */
217 else
218 chan->next_desc = NULL;
219 } else {
220 chan->next_desc = desc;
221 }
222
223 sg->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);
224
225 if (axi_dmac_dest_is_mem(chan)) {
226 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->dest_addr);
227 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->dest_stride);
228 }
229
230 if (axi_dmac_src_is_mem(chan)) {
231 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->src_addr);
232 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->src_stride);
233 }
234
235 /*
236 * If the hardware supports cyclic transfers and there is no callback to
237 * call and only a single segment, enable hw cyclic mode to avoid
238 * unnecessary interrupts.
239 */
240 if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback &&
241 desc->num_sgs == 1)
242 flags |= AXI_DMAC_FLAG_CYCLIC;
243
244 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1);
245 axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->y_len - 1);
246 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);
247 axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);
248}
249
250static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan)
251{
252 return list_first_entry_or_null(&chan->active_descs,
253 struct axi_dmac_desc, vdesc.node);
254}
255
256static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan,
257 unsigned int completed_transfers)
258{
259 struct axi_dmac_desc *active;
260 struct axi_dmac_sg *sg;
261 bool start_next = false;
262
263 active = axi_dmac_active_desc(chan);
264 if (!active)
265 return false;
266
267 do {
268 sg = &active->sg[active->num_completed];
269 if (sg->id == AXI_DMAC_SG_UNUSED) /* Not yet submitted */
270 break;
271 if (!(BIT(sg->id) & completed_transfers))
272 break;
273 active->num_completed++;
274 sg->id = AXI_DMAC_SG_UNUSED;
275 if (sg->schedule_when_free) {
276 sg->schedule_when_free = false;
277 start_next = true;
278 }
279
280 if (active->cyclic)
281 vchan_cyclic_callback(&active->vdesc);
282
283 if (active->num_completed == active->num_sgs) {
284 if (active->cyclic) {
285 active->num_completed = 0; /* wrap around */
286 } else {
287 list_del(&active->vdesc.node);
288 vchan_cookie_complete(&active->vdesc);
289 active = axi_dmac_active_desc(chan);
290 }
291 }
292 } while (active);
293
294 return start_next;
295}
296
297static irqreturn_t axi_dmac_interrupt_handler(int irq, void *devid)
298{
299 struct axi_dmac *dmac = devid;
300 unsigned int pending;
301 bool start_next = false;
302
303 pending = axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING);
304 if (!pending)
305 return IRQ_NONE;
306
307 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, pending);
308
309 spin_lock(&dmac->chan.vchan.lock);
310 /* One or more transfers have finished */
311 if (pending & AXI_DMAC_IRQ_EOT) {
312 unsigned int completed;
313
314 completed = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
315 start_next = axi_dmac_transfer_done(&dmac->chan, completed);
316 }
317 /* Space has become available in the descriptor queue */
318 if ((pending & AXI_DMAC_IRQ_SOT) || start_next)
319 axi_dmac_start_transfer(&dmac->chan);
320 spin_unlock(&dmac->chan.vchan.lock);
321
322 return IRQ_HANDLED;
323}
324
325static int axi_dmac_terminate_all(struct dma_chan *c)
326{
327 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
328 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
329 unsigned long flags;
330 LIST_HEAD(head);
331
332 spin_lock_irqsave(&chan->vchan.lock, flags);
333 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0);
334 chan->next_desc = NULL;
335 vchan_get_all_descriptors(&chan->vchan, &head);
336 list_splice_tail_init(&chan->active_descs, &head);
337 spin_unlock_irqrestore(&chan->vchan.lock, flags);
338
339 vchan_dma_desc_free_list(&chan->vchan, &head);
340
341 return 0;
342}
343
344static void axi_dmac_synchronize(struct dma_chan *c)
345{
346 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
347
348 vchan_synchronize(&chan->vchan);
349}
350
351static void axi_dmac_issue_pending(struct dma_chan *c)
352{
353 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
354 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
355 unsigned long flags;
356
357 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
358
359 spin_lock_irqsave(&chan->vchan.lock, flags);
360 if (vchan_issue_pending(&chan->vchan))
361 axi_dmac_start_transfer(chan);
362 spin_unlock_irqrestore(&chan->vchan.lock, flags);
363}
364
365static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)
366{
367 struct axi_dmac_desc *desc;
368 unsigned int i;
369
370 desc = kzalloc(struct_size(desc, sg, num_sgs), GFP_NOWAIT);
371 if (!desc)
372 return NULL;
373
374 for (i = 0; i < num_sgs; i++)
375 desc->sg[i].id = AXI_DMAC_SG_UNUSED;
376
377 desc->num_sgs = num_sgs;
378
379 return desc;
380}
381
382static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(
383 struct dma_chan *c, struct scatterlist *sgl,
384 unsigned int sg_len, enum dma_transfer_direction direction,
385 unsigned long flags, void *context)
386{
387 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
388 struct axi_dmac_desc *desc;
389 struct scatterlist *sg;
390 unsigned int i;
391
392 if (direction != chan->direction)
393 return NULL;
394
395 desc = axi_dmac_alloc_desc(sg_len);
396 if (!desc)
397 return NULL;
398
399 for_each_sg(sgl, sg, sg_len, i) {
400 if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) ||
401 !axi_dmac_check_len(chan, sg_dma_len(sg))) {
402 kfree(desc);
403 return NULL;
404 }
405
406 if (direction == DMA_DEV_TO_MEM)
407 desc->sg[i].dest_addr = sg_dma_address(sg);
408 else
409 desc->sg[i].src_addr = sg_dma_address(sg);
410 desc->sg[i].x_len = sg_dma_len(sg);
411 desc->sg[i].y_len = 1;
412 }
413
414 desc->cyclic = false;
415
416 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
417}
418
419static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic(
420 struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
421 size_t period_len, enum dma_transfer_direction direction,
422 unsigned long flags)
423{
424 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
425 struct axi_dmac_desc *desc;
426 unsigned int num_periods, i;
427
428 if (direction != chan->direction)
429 return NULL;
430
431 if (!axi_dmac_check_len(chan, buf_len) ||
432 !axi_dmac_check_addr(chan, buf_addr))
433 return NULL;
434
435 if (period_len == 0 || buf_len % period_len)
436 return NULL;
437
438 num_periods = buf_len / period_len;
439
440 desc = axi_dmac_alloc_desc(num_periods);
441 if (!desc)
442 return NULL;
443
444 for (i = 0; i < num_periods; i++) {
445 if (direction == DMA_DEV_TO_MEM)
446 desc->sg[i].dest_addr = buf_addr;
447 else
448 desc->sg[i].src_addr = buf_addr;
449 desc->sg[i].x_len = period_len;
450 desc->sg[i].y_len = 1;
451 buf_addr += period_len;
452 }
453
454 desc->cyclic = true;
455
456 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
457}
458
459static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
460 struct dma_chan *c, struct dma_interleaved_template *xt,
461 unsigned long flags)
462{
463 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
464 struct axi_dmac_desc *desc;
465 size_t dst_icg, src_icg;
466
467 if (xt->frame_size != 1)
468 return NULL;
469
470 if (xt->dir != chan->direction)
471 return NULL;
472
473 if (axi_dmac_src_is_mem(chan)) {
474 if (!xt->src_inc || !axi_dmac_check_addr(chan, xt->src_start))
475 return NULL;
476 }
477
478 if (axi_dmac_dest_is_mem(chan)) {
479 if (!xt->dst_inc || !axi_dmac_check_addr(chan, xt->dst_start))
480 return NULL;
481 }
482
483 dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
484 src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
485
486 if (chan->hw_2d) {
487 if (!axi_dmac_check_len(chan, xt->sgl[0].size) ||
488 !axi_dmac_check_len(chan, xt->numf))
489 return NULL;
490 if (xt->sgl[0].size + dst_icg > chan->max_length ||
491 xt->sgl[0].size + src_icg > chan->max_length)
492 return NULL;
493 } else {
494 if (dst_icg != 0 || src_icg != 0)
495 return NULL;
496 if (chan->max_length / xt->sgl[0].size < xt->numf)
497 return NULL;
498 if (!axi_dmac_check_len(chan, xt->sgl[0].size * xt->numf))
499 return NULL;
500 }
501
502 desc = axi_dmac_alloc_desc(1);
503 if (!desc)
504 return NULL;
505
506 if (axi_dmac_src_is_mem(chan)) {
507 desc->sg[0].src_addr = xt->src_start;
508 desc->sg[0].src_stride = xt->sgl[0].size + src_icg;
509 }
510
511 if (axi_dmac_dest_is_mem(chan)) {
512 desc->sg[0].dest_addr = xt->dst_start;
513 desc->sg[0].dest_stride = xt->sgl[0].size + dst_icg;
514 }
515
516 if (chan->hw_2d) {
517 desc->sg[0].x_len = xt->sgl[0].size;
518 desc->sg[0].y_len = xt->numf;
519 } else {
520 desc->sg[0].x_len = xt->sgl[0].size * xt->numf;
521 desc->sg[0].y_len = 1;
522 }
523
524 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
525}
526
527static void axi_dmac_free_chan_resources(struct dma_chan *c)
528{
529 vchan_free_chan_resources(to_virt_chan(c));
530}
531
532static void axi_dmac_desc_free(struct virt_dma_desc *vdesc)
533{
534 kfree(container_of(vdesc, struct axi_dmac_desc, vdesc));
535}
536
537/*
538 * The configuration stored in the devicetree matches the configuration
539 * parameters of the peripheral instance and allows the driver to know which
540 * features are implemented and how it should behave.
541 */
542static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
543 struct axi_dmac_chan *chan)
544{
545 u32 val;
546 int ret;
547
548 ret = of_property_read_u32(of_chan, "reg", &val);
549 if (ret)
550 return ret;
551
552 /* We only support 1 channel for now */
553 if (val != 0)
554 return -EINVAL;
555
556 ret = of_property_read_u32(of_chan, "adi,source-bus-type", &val);
557 if (ret)
558 return ret;
559 if (val > AXI_DMAC_BUS_TYPE_FIFO)
560 return -EINVAL;
561 chan->src_type = val;
562
563 ret = of_property_read_u32(of_chan, "adi,destination-bus-type", &val);
564 if (ret)
565 return ret;
566 if (val > AXI_DMAC_BUS_TYPE_FIFO)
567 return -EINVAL;
568 chan->dest_type = val;
569
570 ret = of_property_read_u32(of_chan, "adi,source-bus-width", &val);
571 if (ret)
572 return ret;
573 chan->src_width = val / 8;
574
575 ret = of_property_read_u32(of_chan, "adi,destination-bus-width", &val);
576 if (ret)
577 return ret;
578 chan->dest_width = val / 8;
579
580 ret = of_property_read_u32(of_chan, "adi,length-width", &val);
581 if (ret)
582 return ret;
583
584 if (val >= 32)
585 chan->max_length = UINT_MAX;
586 else
587 chan->max_length = (1ULL << val) - 1;
588
589 chan->align_mask = max(chan->dest_width, chan->src_width) - 1;
590
591 if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
592 chan->direction = DMA_MEM_TO_MEM;
593 else if (!axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
594 chan->direction = DMA_MEM_TO_DEV;
595 else if (axi_dmac_dest_is_mem(chan) && !axi_dmac_src_is_mem(chan))
596 chan->direction = DMA_DEV_TO_MEM;
597 else
598 chan->direction = DMA_DEV_TO_DEV;
599
600 chan->hw_cyclic = of_property_read_bool(of_chan, "adi,cyclic");
601 chan->hw_2d = of_property_read_bool(of_chan, "adi,2d");
602
603 return 0;
604}
605
606static int axi_dmac_probe(struct platform_device *pdev)
607{
608 struct device_node *of_channels, *of_chan;
609 struct dma_device *dma_dev;
610 struct axi_dmac *dmac;
611 struct resource *res;
612 int ret;
613
614 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
615 if (!dmac)
616 return -ENOMEM;
617
618 dmac->irq = platform_get_irq(pdev, 0);
619 if (dmac->irq < 0)
620 return dmac->irq;
621 if (dmac->irq == 0)
622 return -EINVAL;
623
624 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
625 dmac->base = devm_ioremap_resource(&pdev->dev, res);
626 if (IS_ERR(dmac->base))
627 return PTR_ERR(dmac->base);
628
629 dmac->clk = devm_clk_get(&pdev->dev, NULL);
630 if (IS_ERR(dmac->clk))
631 return PTR_ERR(dmac->clk);
632
633 INIT_LIST_HEAD(&dmac->chan.active_descs);
634
635 of_channels = of_get_child_by_name(pdev->dev.of_node, "adi,channels");
636 if (of_channels == NULL)
637 return -ENODEV;
638
639 for_each_child_of_node(of_channels, of_chan) {
640 ret = axi_dmac_parse_chan_dt(of_chan, &dmac->chan);
641 if (ret) {
642 of_node_put(of_chan);
643 of_node_put(of_channels);
644 return -EINVAL;
645 }
646 }
647 of_node_put(of_channels);
648
649 pdev->dev.dma_parms = &dmac->dma_parms;
650 dma_set_max_seg_size(&pdev->dev, dmac->chan.max_length);
651
652 dma_dev = &dmac->dma_dev;
653 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
654 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
655 dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
656 dma_dev->device_tx_status = dma_cookie_status;
657 dma_dev->device_issue_pending = axi_dmac_issue_pending;
658 dma_dev->device_prep_slave_sg = axi_dmac_prep_slave_sg;
659 dma_dev->device_prep_dma_cyclic = axi_dmac_prep_dma_cyclic;
660 dma_dev->device_prep_interleaved_dma = axi_dmac_prep_interleaved;
661 dma_dev->device_terminate_all = axi_dmac_terminate_all;
662 dma_dev->device_synchronize = axi_dmac_synchronize;
663 dma_dev->dev = &pdev->dev;
664 dma_dev->chancnt = 1;
665 dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
666 dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
667 dma_dev->directions = BIT(dmac->chan.direction);
668 dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
669 INIT_LIST_HEAD(&dma_dev->channels);
670
671 dmac->chan.vchan.desc_free = axi_dmac_desc_free;
672 vchan_init(&dmac->chan.vchan, dma_dev);
673
674 ret = clk_prepare_enable(dmac->clk);
675 if (ret < 0)
676 return ret;
677
678 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
679
680 ret = dma_async_device_register(dma_dev);
681 if (ret)
682 goto err_clk_disable;
683
684 ret = of_dma_controller_register(pdev->dev.of_node,
685 of_dma_xlate_by_chan_id, dma_dev);
686 if (ret)
687 goto err_unregister_device;
688
689 ret = request_irq(dmac->irq, axi_dmac_interrupt_handler, IRQF_SHARED,
690 dev_name(&pdev->dev), dmac);
691 if (ret)
692 goto err_unregister_of;
693
694 platform_set_drvdata(pdev, dmac);
695
696 return 0;
697
698err_unregister_of:
699 of_dma_controller_free(pdev->dev.of_node);
700err_unregister_device:
701 dma_async_device_unregister(&dmac->dma_dev);
702err_clk_disable:
703 clk_disable_unprepare(dmac->clk);
704
705 return ret;
706}
707
708static int axi_dmac_remove(struct platform_device *pdev)
709{
710 struct axi_dmac *dmac = platform_get_drvdata(pdev);
711
712 of_dma_controller_free(pdev->dev.of_node);
713 free_irq(dmac->irq, dmac);
714 tasklet_kill(&dmac->chan.vchan.task);
715 dma_async_device_unregister(&dmac->dma_dev);
716 clk_disable_unprepare(dmac->clk);
717
718 return 0;
719}
720
721static const struct of_device_id axi_dmac_of_match_table[] = {
722 { .compatible = "adi,axi-dmac-1.00.a" },
723 { },
724};
725MODULE_DEVICE_TABLE(of, axi_dmac_of_match_table);
726
727static struct platform_driver axi_dmac_driver = {
728 .driver = {
729 .name = "dma-axi-dmac",
730 .of_match_table = axi_dmac_of_match_table,
731 },
732 .probe = axi_dmac_probe,
733 .remove = axi_dmac_remove,
734};
735module_platform_driver(axi_dmac_driver);
736
737MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
738MODULE_DESCRIPTION("DMA controller driver for the AXI-DMAC controller");
739MODULE_LICENSE("GPL v2");
740