1 | /* |
2 | * drivers/dma/fsl_raid.h |
3 | * |
4 | * Freescale RAID Engine device driver |
5 | * |
6 | * Author: |
7 | * Harninder Rai <harninder.rai@freescale.com> |
8 | * Naveen Burmi <naveenburmi@freescale.com> |
9 | * |
10 | * Rewrite: |
11 | * Xuelin Shi <xuelin.shi@freescale.com> |
12 | |
13 | * Copyright (c) 2010-2012 Freescale Semiconductor, Inc. |
14 | * |
15 | * Redistribution and use in source and binary forms, with or without |
16 | * modification, are permitted provided that the following conditions are met: |
17 | * * Redistributions of source code must retain the above copyright |
18 | * notice, this list of conditions and the following disclaimer. |
19 | * * Redistributions in binary form must reproduce the above copyright |
20 | * notice, this list of conditions and the following disclaimer in the |
21 | * documentation and/or other materials provided with the distribution. |
22 | * * Neither the name of Freescale Semiconductor nor the |
23 | * names of its contributors may be used to endorse or promote products |
24 | * derived from this software without specific prior written permission. |
25 | * |
26 | * ALTERNATIVELY, this software may be distributed under the terms of the |
27 | * GNU General Public License ("GPL") as published by the Free Software |
28 | * Foundation, either version 2 of that License or (at your option) any |
29 | * later version. |
30 | * |
31 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
32 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
34 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
41 | * |
42 | */ |
43 | |
44 | #define FSL_RE_MAX_CHANS 4 |
45 | #define FSL_RE_DPAA_MODE BIT(30) |
46 | #define FSL_RE_NON_DPAA_MODE BIT(31) |
47 | #define FSL_RE_GFM_POLY 0x1d000000 |
48 | #define FSL_RE_ADD_JOB(x) ((x) << 16) |
49 | #define FSL_RE_RMVD_JOB(x) ((x) << 16) |
50 | #define FSL_RE_CFG1_CBSI 0x08000000 |
51 | #define FSL_RE_CFG1_CBS0 0x00080000 |
52 | #define FSL_RE_SLOT_FULL_SHIFT 8 |
53 | #define FSL_RE_SLOT_FULL(x) ((x) >> FSL_RE_SLOT_FULL_SHIFT) |
54 | #define FSL_RE_SLOT_AVAIL_SHIFT 8 |
55 | #define FSL_RE_SLOT_AVAIL(x) ((x) >> FSL_RE_SLOT_AVAIL_SHIFT) |
56 | #define FSL_RE_PQ_OPCODE 0x1B |
57 | #define FSL_RE_XOR_OPCODE 0x1A |
58 | #define FSL_RE_MOVE_OPCODE 0x8 |
59 | #define FSL_RE_FRAME_ALIGN 16 |
60 | #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */ |
61 | #define FSL_RE_CACHEABLE_IO 0x0 |
62 | #define FSL_RE_BUFFER_OUTPUT 0x0 |
63 | #define FSL_RE_INTR_ON_ERROR 0x1 |
64 | #define FSL_RE_DATA_DEP 0x1 |
65 | #define FSL_RE_ENABLE_DPI 0x0 |
66 | #define FSL_RE_RING_SIZE 0x400 |
67 | #define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1) |
68 | #define FSL_RE_RING_SIZE_SHIFT 8 |
69 | #define FSL_RE_ADDR_BIT_SHIFT 4 |
70 | #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1) |
71 | #define FSL_RE_ERROR 0x40000000 |
72 | #define FSL_RE_INTR 0x80000000 |
73 | #define FSL_RE_CLR_INTR 0x80000000 |
74 | #define FSL_RE_PAUSE 0x80000000 |
75 | #define FSL_RE_ENABLE 0x80000000 |
76 | #define FSL_RE_REG_LIODN_MASK 0x00000FFF |
77 | |
78 | #define FSL_RE_CDB_OPCODE_MASK 0xF8000000 |
79 | #define FSL_RE_CDB_OPCODE_SHIFT 27 |
80 | #define FSL_RE_CDB_EXCLEN_MASK 0x03000000 |
81 | #define FSL_RE_CDB_EXCLEN_SHIFT 24 |
82 | #define FSL_RE_CDB_EXCLQ1_MASK 0x00F00000 |
83 | #define FSL_RE_CDB_EXCLQ1_SHIFT 20 |
84 | #define FSL_RE_CDB_EXCLQ2_MASK 0x000F0000 |
85 | #define FSL_RE_CDB_EXCLQ2_SHIFT 16 |
86 | #define FSL_RE_CDB_BLKSIZE_MASK 0x0000C000 |
87 | #define FSL_RE_CDB_BLKSIZE_SHIFT 14 |
88 | #define FSL_RE_CDB_CACHE_MASK 0x00003000 |
89 | #define FSL_RE_CDB_CACHE_SHIFT 12 |
90 | #define FSL_RE_CDB_BUFFER_MASK 0x00000800 |
91 | #define FSL_RE_CDB_BUFFER_SHIFT 11 |
92 | #define FSL_RE_CDB_ERROR_MASK 0x00000400 |
93 | #define FSL_RE_CDB_ERROR_SHIFT 10 |
94 | #define FSL_RE_CDB_NRCS_MASK 0x0000003C |
95 | #define FSL_RE_CDB_NRCS_SHIFT 6 |
96 | #define FSL_RE_CDB_DEPEND_MASK 0x00000008 |
97 | #define FSL_RE_CDB_DEPEND_SHIFT 3 |
98 | #define FSL_RE_CDB_DPI_MASK 0x00000004 |
99 | #define FSL_RE_CDB_DPI_SHIFT 2 |
100 | |
101 | /* |
102 | * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes. |
103 | * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes. |
104 | * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block |
105 | * 320+180=500, align to 64bytes, that is 512 bytes. |
106 | */ |
107 | #define FSL_RE_CF_DESC_SIZE 320 |
108 | #define FSL_RE_CF_CDB_SIZE 512 |
109 | #define FSL_RE_CF_CDB_ALIGN 64 |
110 | |
111 | struct fsl_re_ctrl { |
112 | /* General Configuration Registers */ |
113 | __be32 global_config; /* Global Configuration Register */ |
114 | u8 rsvd1[4]; |
115 | __be32 galois_field_config; /* Galois Field Configuration Register */ |
116 | u8 rsvd2[4]; |
117 | __be32 jq_wrr_config; /* WRR Configuration register */ |
118 | u8 rsvd3[4]; |
119 | __be32 crc_config; /* CRC Configuration register */ |
120 | u8 rsvd4[228]; |
121 | __be32 system_reset; /* System Reset Register */ |
122 | u8 rsvd5[252]; |
123 | __be32 global_status; /* Global Status Register */ |
124 | u8 rsvd6[832]; |
125 | __be32 re_liodn_base; /* LIODN Base Register */ |
126 | u8 rsvd7[1712]; |
127 | __be32 re_version_id; /* Version ID register of RE */ |
128 | __be32 re_version_id_2; /* Version ID 2 register of RE */ |
129 | u8 rsvd8[512]; |
130 | __be32 host_config; /* Host I/F Configuration Register */ |
131 | }; |
132 | |
133 | struct fsl_re_chan_cfg { |
134 | /* Registers for JR interface */ |
135 | __be32 jr_config_0; /* Job Queue Configuration 0 Register */ |
136 | __be32 jr_config_1; /* Job Queue Configuration 1 Register */ |
137 | __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */ |
138 | u8 rsvd1[4]; |
139 | __be32 jr_command; /* Job Queue Command Register */ |
140 | u8 rsvd2[4]; |
141 | __be32 jr_status; /* Job Queue Status Register */ |
142 | u8 rsvd3[228]; |
143 | |
144 | /* Input Ring */ |
145 | __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */ |
146 | __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */ |
147 | __be32 inbring_size; /* Inbound Ring Size Register */ |
148 | u8 rsvd4[4]; |
149 | __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */ |
150 | u8 rsvd5[4]; |
151 | __be32 inbring_add_job; /* Inbound Ring Add Job Register */ |
152 | u8 rsvd6[4]; |
153 | __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */ |
154 | u8 rsvd7[220]; |
155 | |
156 | /* Output Ring */ |
157 | __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */ |
158 | __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */ |
159 | __be32 oubring_size; /* Outbound Ring Size Register */ |
160 | u8 rsvd8[4]; |
161 | __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */ |
162 | u8 rsvd9[4]; |
163 | __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */ |
164 | u8 rsvd10[4]; |
165 | __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */ |
166 | }; |
167 | |
168 | /* |
169 | * Command Descriptor Block (CDB) for unicast move command. |
170 | * In RAID Engine terms, memcpy is done through move command |
171 | */ |
172 | struct fsl_re_move_cdb { |
173 | __be32 cdb32; |
174 | }; |
175 | |
176 | /* Data protection/integrity related fields */ |
177 | #define FSL_RE_DPI_APPS_MASK 0xC0000000 |
178 | #define FSL_RE_DPI_APPS_SHIFT 30 |
179 | #define FSL_RE_DPI_REF_MASK 0x30000000 |
180 | #define FSL_RE_DPI_REF_SHIFT 28 |
181 | #define FSL_RE_DPI_GUARD_MASK 0x0C000000 |
182 | #define FSL_RE_DPI_GUARD_SHIFT 26 |
183 | #define FSL_RE_DPI_ATTR_MASK 0x03000000 |
184 | #define FSL_RE_DPI_ATTR_SHIFT 24 |
185 | #define FSL_RE_DPI_META_MASK 0x0000FFFF |
186 | |
187 | struct fsl_re_dpi { |
188 | __be32 dpi32; |
189 | __be32 ref; |
190 | }; |
191 | |
192 | /* |
193 | * CDB for GenQ command. In RAID Engine terminology, XOR is |
194 | * done through this command |
195 | */ |
196 | struct fsl_re_xor_cdb { |
197 | __be32 cdb32; |
198 | u8 gfm[16]; |
199 | struct fsl_re_dpi dpi_dest_spec; |
200 | struct fsl_re_dpi dpi_src_spec[16]; |
201 | }; |
202 | |
203 | /* CDB for no-op command */ |
204 | struct fsl_re_noop_cdb { |
205 | __be32 cdb32; |
206 | }; |
207 | |
208 | /* |
209 | * CDB for GenQQ command. In RAID Engine terminology, P/Q is |
210 | * done through this command |
211 | */ |
212 | struct fsl_re_pq_cdb { |
213 | __be32 cdb32; |
214 | u8 gfm_q1[16]; |
215 | u8 gfm_q2[16]; |
216 | struct fsl_re_dpi dpi_dest_spec[2]; |
217 | struct fsl_re_dpi dpi_src_spec[16]; |
218 | }; |
219 | |
220 | /* Compound frame */ |
221 | #define FSL_RE_CF_ADDR_HIGH_MASK 0x000000FF |
222 | #define FSL_RE_CF_EXT_MASK 0x80000000 |
223 | #define FSL_RE_CF_EXT_SHIFT 31 |
224 | #define FSL_RE_CF_FINAL_MASK 0x40000000 |
225 | #define FSL_RE_CF_FINAL_SHIFT 30 |
226 | #define FSL_RE_CF_LENGTH_MASK 0x000FFFFF |
227 | #define FSL_RE_CF_BPID_MASK 0x00FF0000 |
228 | #define FSL_RE_CF_BPID_SHIFT 16 |
229 | #define FSL_RE_CF_OFFSET_MASK 0x00001FFF |
230 | |
231 | struct fsl_re_cmpnd_frame { |
232 | __be32 addr_high; |
233 | __be32 addr_low; |
234 | __be32 efrl32; |
235 | __be32 rbro32; |
236 | }; |
237 | |
238 | /* Frame descriptor */ |
239 | #define FSL_RE_HWDESC_LIODN_MASK 0x3F000000 |
240 | #define FSL_RE_HWDESC_LIODN_SHIFT 24 |
241 | #define FSL_RE_HWDESC_BPID_MASK 0x00FF0000 |
242 | #define FSL_RE_HWDESC_BPID_SHIFT 16 |
243 | #define FSL_RE_HWDESC_ELIODN_MASK 0x0000F000 |
244 | #define FSL_RE_HWDESC_ELIODN_SHIFT 12 |
245 | #define FSL_RE_HWDESC_FMT_SHIFT 29 |
246 | #define FSL_RE_HWDESC_FMT_MASK (0x3 << FSL_RE_HWDESC_FMT_SHIFT) |
247 | |
248 | struct fsl_re_hw_desc { |
249 | __be32 lbea32; |
250 | __be32 addr_low; |
251 | __be32 fmt32; |
252 | __be32 status; |
253 | }; |
254 | |
255 | /* Raid Engine device private data */ |
256 | struct fsl_re_drv_private { |
257 | u8 total_chans; |
258 | struct dma_device dma_dev; |
259 | struct fsl_re_ctrl *re_regs; |
260 | struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS]; |
261 | struct dma_pool *cf_desc_pool; |
262 | struct dma_pool *hw_desc_pool; |
263 | }; |
264 | |
265 | /* Per job ring data structure */ |
266 | struct fsl_re_chan { |
267 | char name[16]; |
268 | spinlock_t desc_lock; /* queue lock */ |
269 | struct list_head ack_q; /* wait to acked queue */ |
270 | struct list_head active_q; /* already issued on hw, not completed */ |
271 | struct list_head submit_q; |
272 | struct list_head free_q; /* alloc available queue */ |
273 | struct device *dev; |
274 | struct fsl_re_drv_private *re_dev; |
275 | struct dma_chan chan; |
276 | struct fsl_re_chan_cfg *jrregs; |
277 | int irq; |
278 | struct tasklet_struct irqtask; |
279 | u32 alloc_count; |
280 | |
281 | /* hw descriptor ring for inbound queue*/ |
282 | dma_addr_t inb_phys_addr; |
283 | struct fsl_re_hw_desc *inb_ring_virt_addr; |
284 | u32 inb_count; |
285 | |
286 | /* hw descriptor ring for outbound queue */ |
287 | dma_addr_t oub_phys_addr; |
288 | struct fsl_re_hw_desc *oub_ring_virt_addr; |
289 | u32 oub_count; |
290 | }; |
291 | |
292 | /* Async transaction descriptor */ |
293 | struct fsl_re_desc { |
294 | struct dma_async_tx_descriptor async_tx; |
295 | struct list_head node; |
296 | struct fsl_re_hw_desc hwdesc; |
297 | struct fsl_re_chan *re_chan; |
298 | |
299 | /* hwdesc will point to cf_addr */ |
300 | void *cf_addr; |
301 | dma_addr_t cf_paddr; |
302 | |
303 | void *cdb_addr; |
304 | dma_addr_t cdb_paddr; |
305 | int status; |
306 | }; |
307 | |