| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
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| 4 | */ |
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| 5 | #ifndef _IOAT_REGISTERS_H_ |
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| 6 | #define _IOAT_REGISTERS_H_ |
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| 7 | |
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| 8 | #define IOAT_PCI_DMACTRL_OFFSET 0x48 |
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| 9 | #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 |
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| 10 | #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 |
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| 11 | |
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| 12 | #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 |
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| 13 | #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 |
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| 14 | #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 |
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| 15 | #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 |
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| 16 | |
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| 17 | /* MMIO Device Registers */ |
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| 18 | #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ |
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| 19 | |
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| 20 | #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ |
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| 21 | #define IOAT_XFERCAP_4KB 12 |
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| 22 | #define IOAT_XFERCAP_8KB 13 |
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| 23 | #define IOAT_XFERCAP_16KB 14 |
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| 24 | #define IOAT_XFERCAP_32KB 15 |
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| 25 | #define IOAT_XFERCAP_32GB 0 |
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| 26 | |
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| 27 | #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ |
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| 28 | #define IOAT_GENCTRL_DEBUG_EN 0x01 |
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| 29 | |
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| 30 | #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ |
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| 31 | #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ |
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| 32 | #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ |
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| 33 | #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ |
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| 34 | #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ |
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| 35 | |
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| 36 | #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ |
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| 37 | |
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| 38 | #define IOAT_VER_OFFSET 0x08 /* 8-bit */ |
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| 39 | #define IOAT_VER_MAJOR_MASK 0xF0 |
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| 40 | #define IOAT_VER_MINOR_MASK 0x0F |
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| 41 | #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) |
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| 42 | #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) |
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| 43 | |
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| 44 | #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ |
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| 45 | |
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| 46 | #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ |
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| 47 | #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ |
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| 48 | #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ |
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| 49 | |
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| 50 | #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ |
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| 51 | #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 |
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| 52 | #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 |
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| 53 | #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 |
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| 54 | #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 |
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| 55 | |
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| 56 | #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ |
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| 57 | #define IOAT_CAP_PAGE_BREAK 0x00000001 |
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| 58 | #define IOAT_CAP_CRC 0x00000002 |
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| 59 | #define IOAT_CAP_SKIP_MARKER 0x00000004 |
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| 60 | #define IOAT_CAP_DCA 0x00000010 |
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| 61 | #define IOAT_CAP_CRC_MOVE 0x00000020 |
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| 62 | #define IOAT_CAP_FILL_BLOCK 0x00000040 |
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| 63 | #define IOAT_CAP_APIC 0x00000080 |
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| 64 | #define IOAT_CAP_XOR 0x00000100 |
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| 65 | #define IOAT_CAP_PQ 0x00000200 |
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| 66 | #define IOAT_CAP_DWBES 0x00002000 |
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| 67 | #define IOAT_CAP_RAID16SS 0x00020000 |
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| 68 | #define IOAT_CAP_DPS 0x00800000 |
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| 69 | |
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| 70 | #define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ |
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| 71 | |
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| 72 | #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ |
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| 73 | |
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| 74 | /* DMA Channel Registers */ |
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| 75 | #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ |
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| 76 | #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 |
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| 77 | #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 |
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| 78 | #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 |
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| 79 | #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 |
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| 80 | #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 |
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| 81 | #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 |
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| 82 | #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 |
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| 83 | #define IOAT_CHANCTRL_INT_REARM 0x0001 |
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| 84 | #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ |
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| 85 | IOAT_CHANCTRL_ERR_INT_EN |\ |
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| 86 | IOAT_CHANCTRL_ERR_COMPLETION_EN |\ |
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| 87 | IOAT_CHANCTRL_ANY_ERR_ABORT_EN) |
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| 88 | |
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| 89 | #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ |
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| 90 | #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ |
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| 91 | #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ |
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| 92 | |
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| 93 | #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ |
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| 94 | #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) |
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| 95 | #define IOAT_CHANSTS_SOFT_ERR 0x10ULL |
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| 96 | #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL |
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| 97 | #define IOAT_CHANSTS_STATUS 0x7ULL |
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| 98 | #define IOAT_CHANSTS_ACTIVE 0x0 |
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| 99 | #define IOAT_CHANSTS_DONE 0x1 |
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| 100 | #define IOAT_CHANSTS_SUSPENDED 0x2 |
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| 101 | #define IOAT_CHANSTS_HALTED 0x3 |
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| 102 | |
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| 103 | |
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| 104 | |
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| 105 | #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ |
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| 106 | |
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| 107 | #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ |
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| 108 | #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 |
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| 109 | #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ |
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| 110 | |
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| 111 | /* CB DCA Memory Space Registers */ |
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| 112 | #define IOAT_DCAOFFSET_OFFSET 0x14 |
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| 113 | /* CB_BAR + IOAT_DCAOFFSET value */ |
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| 114 | #define IOAT_DCA_VER_OFFSET 0x00 |
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| 115 | #define IOAT_DCA_VER_MAJOR_MASK 0xF0 |
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| 116 | #define IOAT_DCA_VER_MINOR_MASK 0x0F |
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| 117 | |
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| 118 | #define IOAT_DCA_COMP_OFFSET 0x02 |
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| 119 | #define IOAT_DCA_COMP_V1 0x1 |
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| 120 | |
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| 121 | #define IOAT_FSB_CAPABILITY_OFFSET 0x04 |
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| 122 | #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 |
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| 123 | |
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| 124 | #define IOAT_PCI_CAPABILITY_OFFSET 0x06 |
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| 125 | #define IOAT_PCI_CAPABILITY_MEMWR 0x1 |
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| 126 | |
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| 127 | #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 |
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| 128 | #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 |
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| 129 | |
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| 130 | #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A |
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| 131 | #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 |
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| 132 | |
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| 133 | #define IOAT_APICID_TAG_MAP_OFFSET 0x0C |
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| 134 | #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F |
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| 135 | #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 |
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| 136 | #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 |
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| 137 | #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 |
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| 138 | #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 |
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| 139 | #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 |
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| 140 | #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 |
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| 141 | #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 |
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| 142 | #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 |
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| 143 | #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 |
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| 144 | #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 |
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| 145 | |
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| 146 | #define IOAT_DCA_GREQID_OFFSET 0x10 |
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| 147 | #define IOAT_DCA_GREQID_SIZE 0x04 |
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| 148 | #define IOAT_DCA_GREQID_MASK 0xFFFF |
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| 149 | #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 |
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| 150 | #define IOAT_DCA_GREQID_VALID 0x20000000 |
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| 151 | #define IOAT_DCA_GREQID_LASTID 0x80000000 |
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| 152 | |
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| 153 | #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 |
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| 154 | #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 |
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| 155 | |
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| 156 | #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A |
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| 157 | #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 |
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| 158 | |
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| 159 | #define IOAT3_CSI_CONTROL_OFFSET 0x0C |
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| 160 | #define IOAT3_CSI_CONTROL_PREFETCH 0x1 |
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| 161 | |
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| 162 | #define IOAT3_PCI_CONTROL_OFFSET 0x0E |
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| 163 | #define IOAT3_PCI_CONTROL_MEMWR 0x1 |
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| 164 | |
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| 165 | #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 |
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| 166 | #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 |
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| 167 | #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 |
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| 168 | |
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| 169 | #define IOAT3_DCA_GREQID_OFFSET 0x02 |
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| 170 | |
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| 171 | #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ |
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| 172 | #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ |
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| 173 | #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ |
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| 174 | ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) |
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| 175 | #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C |
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| 176 | #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 |
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| 177 | #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ |
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| 178 | ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) |
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| 179 | #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 |
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| 180 | #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 |
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| 181 | #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ |
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| 182 | ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) |
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| 183 | |
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| 184 | #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ |
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| 185 | #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ |
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| 186 | #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ |
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| 187 | ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) |
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| 188 | #define IOAT_CHANCMD_RESET 0x20 |
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| 189 | #define IOAT_CHANCMD_RESUME 0x10 |
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| 190 | #define IOAT_CHANCMD_ABORT 0x08 |
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| 191 | #define IOAT_CHANCMD_SUSPEND 0x04 |
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| 192 | #define IOAT_CHANCMD_APPEND 0x02 |
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| 193 | #define IOAT_CHANCMD_START 0x01 |
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| 194 | |
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| 195 | #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ |
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| 196 | #define IOAT_CHANCMP_OFFSET_LOW 0x18 |
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| 197 | #define IOAT_CHANCMP_OFFSET_HIGH 0x1C |
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| 198 | |
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| 199 | #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ |
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| 200 | #define IOAT_CDAR_OFFSET_LOW 0x20 |
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| 201 | #define IOAT_CDAR_OFFSET_HIGH 0x24 |
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| 202 | |
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| 203 | #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ |
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| 204 | #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 |
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| 205 | #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 |
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| 206 | #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 |
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| 207 | #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 |
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| 208 | #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 |
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| 209 | #define IOAT_CHANERR_CHANCMD_ERR 0x0020 |
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| 210 | #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 |
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| 211 | #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 |
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| 212 | #define IOAT_CHANERR_READ_DATA_ERR 0x0100 |
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| 213 | #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 |
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| 214 | #define IOAT_CHANERR_CONTROL_ERR 0x0400 |
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| 215 | #define IOAT_CHANERR_LENGTH_ERR 0x0800 |
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| 216 | #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 |
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| 217 | #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 |
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| 218 | #define IOAT_CHANERR_SOFT_ERR 0x4000 |
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| 219 | #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 |
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| 220 | #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 |
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| 221 | #define IOAT_CHANERR_XOR_Q_ERR 0x20000 |
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| 222 | #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 |
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| 223 | |
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| 224 | #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) |
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| 225 | #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \ |
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| 226 | IOAT_CHANERR_WRITE_DATA_ERR) |
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| 227 | |
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| 228 | #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ |
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| 229 | |
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| 230 | #define IOAT_CHAN_DRSCTL_OFFSET 0xB6 |
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| 231 | #define IOAT_CHAN_DRSZ_4KB 0x0000 |
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| 232 | #define IOAT_CHAN_DRSZ_8KB 0x0001 |
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| 233 | #define IOAT_CHAN_DRSZ_2MB 0x0009 |
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| 234 | #define IOAT_CHAN_DRS_EN 0x0100 |
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| 235 | #define IOAT_CHAN_DRS_AUTOWRAP 0x0200 |
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| 236 | |
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| 237 | #define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC |
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| 238 | #define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 |
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| 239 | #define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 |
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| 240 | |
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| 241 | #define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 |
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| 242 | #define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ |
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| 243 | #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ |
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| 244 | #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ |
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| 245 | |
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| 246 | #define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 |
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| 247 | #define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ |
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| 248 | #define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ |
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| 249 | #define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ |
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| 250 | |
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| 251 | #endif /* _IOAT_REGISTERS_H_ */ |
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| 252 | |
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