1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4//
5// Refer to drivers/dma/imx-sdma.c
6
7#include <linux/init.h>
8#include <linux/types.h>
9#include <linux/mm.h>
10#include <linux/interrupt.h>
11#include <linux/clk.h>
12#include <linux/wait.h>
13#include <linux/sched.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/dma-mapping.h>
17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/dmaengine.h>
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/stmp_device.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/of_dma.h>
26#include <linux/list.h>
27
28#include <asm/irq.h>
29
30#include "dmaengine.h"
31
32/*
33 * NOTE: The term "PIO" throughout the mxs-dma implementation means
34 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
35 * dma can program the controller registers of peripheral devices.
36 */
37
38#define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
39#define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
40
41#define HW_APBHX_CTRL0 0x000
42#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
43#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
44#define BP_APBH_CTRL0_RESET_CHANNEL 16
45#define HW_APBHX_CTRL1 0x010
46#define HW_APBHX_CTRL2 0x020
47#define HW_APBHX_CHANNEL_CTRL 0x030
48#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
49/*
50 * The offset of NXTCMDAR register is different per both dma type and version,
51 * while stride for each channel is all the same 0x70.
52 */
53#define HW_APBHX_CHn_NXTCMDAR(d, n) \
54 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
55#define HW_APBHX_CHn_SEMA(d, n) \
56 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
57#define HW_APBHX_CHn_BAR(d, n) \
58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
59#define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
60
61/*
62 * ccw bits definitions
63 *
64 * COMMAND: 0..1 (2)
65 * CHAIN: 2 (1)
66 * IRQ: 3 (1)
67 * NAND_LOCK: 4 (1) - not implemented
68 * NAND_WAIT4READY: 5 (1) - not implemented
69 * DEC_SEM: 6 (1)
70 * WAIT4END: 7 (1)
71 * HALT_ON_TERMINATE: 8 (1)
72 * TERMINATE_FLUSH: 9 (1)
73 * RESERVED: 10..11 (2)
74 * PIO_NUM: 12..15 (4)
75 */
76#define BP_CCW_COMMAND 0
77#define BM_CCW_COMMAND (3 << 0)
78#define CCW_CHAIN (1 << 2)
79#define CCW_IRQ (1 << 3)
80#define CCW_DEC_SEM (1 << 6)
81#define CCW_WAIT4END (1 << 7)
82#define CCW_HALT_ON_TERM (1 << 8)
83#define CCW_TERM_FLUSH (1 << 9)
84#define BP_CCW_PIO_NUM 12
85#define BM_CCW_PIO_NUM (0xf << 12)
86
87#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
88
89#define MXS_DMA_CMD_NO_XFER 0
90#define MXS_DMA_CMD_WRITE 1
91#define MXS_DMA_CMD_READ 2
92#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
93
94struct mxs_dma_ccw {
95 u32 next;
96 u16 bits;
97 u16 xfer_bytes;
98#define MAX_XFER_BYTES 0xff00
99 u32 bufaddr;
100#define MXS_PIO_WORDS 16
101 u32 pio_words[MXS_PIO_WORDS];
102};
103
104#define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
105#define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
106
107struct mxs_dma_chan {
108 struct mxs_dma_engine *mxs_dma;
109 struct dma_chan chan;
110 struct dma_async_tx_descriptor desc;
111 struct tasklet_struct tasklet;
112 unsigned int chan_irq;
113 struct mxs_dma_ccw *ccw;
114 dma_addr_t ccw_phys;
115 int desc_count;
116 enum dma_status status;
117 unsigned int flags;
118 bool reset;
119#define MXS_DMA_SG_LOOP (1 << 0)
120#define MXS_DMA_USE_SEMAPHORE (1 << 1)
121};
122
123#define MXS_DMA_CHANNELS 16
124#define MXS_DMA_CHANNELS_MASK 0xffff
125
126enum mxs_dma_devtype {
127 MXS_DMA_APBH,
128 MXS_DMA_APBX,
129};
130
131enum mxs_dma_id {
132 IMX23_DMA,
133 IMX28_DMA,
134};
135
136struct mxs_dma_engine {
137 enum mxs_dma_id dev_id;
138 enum mxs_dma_devtype type;
139 void __iomem *base;
140 struct clk *clk;
141 struct dma_device dma_device;
142 struct device_dma_parameters dma_parms;
143 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
144 struct platform_device *pdev;
145 unsigned int nr_channels;
146};
147
148struct mxs_dma_type {
149 enum mxs_dma_id id;
150 enum mxs_dma_devtype type;
151};
152
153static struct mxs_dma_type mxs_dma_types[] = {
154 {
155 .id = IMX23_DMA,
156 .type = MXS_DMA_APBH,
157 }, {
158 .id = IMX23_DMA,
159 .type = MXS_DMA_APBX,
160 }, {
161 .id = IMX28_DMA,
162 .type = MXS_DMA_APBH,
163 }, {
164 .id = IMX28_DMA,
165 .type = MXS_DMA_APBX,
166 }
167};
168
169static const struct platform_device_id mxs_dma_ids[] = {
170 {
171 .name = "imx23-dma-apbh",
172 .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
173 }, {
174 .name = "imx23-dma-apbx",
175 .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
176 }, {
177 .name = "imx28-dma-apbh",
178 .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
179 }, {
180 .name = "imx28-dma-apbx",
181 .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
182 }, {
183 /* end of list */
184 }
185};
186
187static const struct of_device_id mxs_dma_dt_ids[] = {
188 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
189 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
190 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
191 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
192 { /* sentinel */ }
193};
194MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
195
196static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
197{
198 return container_of(chan, struct mxs_dma_chan, chan);
199}
200
201static void mxs_dma_reset_chan(struct dma_chan *chan)
202{
203 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
204 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
205 int chan_id = mxs_chan->chan.chan_id;
206
207 /*
208 * mxs dma channel resets can cause a channel stall. To recover from a
209 * channel stall, we have to reset the whole DMA engine. To avoid this,
210 * we use cyclic DMA with semaphores, that are enhanced in
211 * mxs_dma_int_handler. To reset the channel, we can simply stop writing
212 * into the semaphore counter.
213 */
214 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
215 mxs_chan->flags & MXS_DMA_SG_LOOP) {
216 mxs_chan->reset = true;
217 } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
218 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
219 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
220 } else {
221 unsigned long elapsed = 0;
222 const unsigned long max_wait = 50000; /* 50ms */
223 void __iomem *reg_dbg1 = mxs_dma->base +
224 HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
225
226 /*
227 * On i.MX28 APBX, the DMA channel can stop working if we reset
228 * the channel while it is in READ_FLUSH (0x08) state.
229 * We wait here until we leave the state. Then we trigger the
230 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
231 * because of this.
232 */
233 while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
234 udelay(100);
235 elapsed += 100;
236 }
237
238 if (elapsed >= max_wait)
239 dev_err(&mxs_chan->mxs_dma->pdev->dev,
240 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
241 chan_id);
242
243 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
244 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
245 }
246
247 mxs_chan->status = DMA_COMPLETE;
248}
249
250static void mxs_dma_enable_chan(struct dma_chan *chan)
251{
252 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
253 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
254 int chan_id = mxs_chan->chan.chan_id;
255
256 /* set cmd_addr up */
257 writel(mxs_chan->ccw_phys,
258 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
259
260 /* write 1 to SEMA to kick off the channel */
261 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
262 mxs_chan->flags & MXS_DMA_SG_LOOP) {
263 /* A cyclic DMA consists of at least 2 segments, so initialize
264 * the semaphore with 2 so we have enough time to add 1 to the
265 * semaphore if we need to */
266 writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
267 } else {
268 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
269 }
270 mxs_chan->reset = false;
271}
272
273static void mxs_dma_disable_chan(struct dma_chan *chan)
274{
275 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
276
277 mxs_chan->status = DMA_COMPLETE;
278}
279
280static int mxs_dma_pause_chan(struct dma_chan *chan)
281{
282 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
283 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
284 int chan_id = mxs_chan->chan.chan_id;
285
286 /* freeze the channel */
287 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
288 writel(1 << chan_id,
289 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
290 else
291 writel(1 << chan_id,
292 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
293
294 mxs_chan->status = DMA_PAUSED;
295 return 0;
296}
297
298static int mxs_dma_resume_chan(struct dma_chan *chan)
299{
300 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
301 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
302 int chan_id = mxs_chan->chan.chan_id;
303
304 /* unfreeze the channel */
305 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
306 writel(1 << chan_id,
307 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
308 else
309 writel(1 << chan_id,
310 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
311
312 mxs_chan->status = DMA_IN_PROGRESS;
313 return 0;
314}
315
316static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
317{
318 return dma_cookie_assign(tx);
319}
320
321static void mxs_dma_tasklet(unsigned long data)
322{
323 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
324
325 dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL);
326}
327
328static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
329{
330 int i;
331
332 for (i = 0; i != mxs_dma->nr_channels; ++i)
333 if (mxs_dma->mxs_chans[i].chan_irq == irq)
334 return i;
335
336 return -EINVAL;
337}
338
339static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
340{
341 struct mxs_dma_engine *mxs_dma = dev_id;
342 struct mxs_dma_chan *mxs_chan;
343 u32 completed;
344 u32 err;
345 int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
346
347 if (chan < 0)
348 return IRQ_NONE;
349
350 /* completion status */
351 completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
352 completed = (completed >> chan) & 0x1;
353
354 /* Clear interrupt */
355 writel((1 << chan),
356 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
357
358 /* error status */
359 err = readl(mxs_dma->base + HW_APBHX_CTRL2);
360 err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
361
362 /*
363 * error status bit is in the upper 16 bits, error irq bit in the lower
364 * 16 bits. We transform it into a simpler error code:
365 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
366 */
367 err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
368
369 /* Clear error irq */
370 writel((1 << chan),
371 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
372
373 /*
374 * When both completion and error of termination bits set at the
375 * same time, we do not take it as an error. IOW, it only becomes
376 * an error we need to handle here in case of either it's a bus
377 * error or a termination error with no completion. 0x01 is termination
378 * error, so we can subtract err & completed to get the real error case.
379 */
380 err -= err & completed;
381
382 mxs_chan = &mxs_dma->mxs_chans[chan];
383
384 if (err) {
385 dev_dbg(mxs_dma->dma_device.dev,
386 "%s: error in channel %d\n", __func__,
387 chan);
388 mxs_chan->status = DMA_ERROR;
389 mxs_dma_reset_chan(&mxs_chan->chan);
390 } else if (mxs_chan->status != DMA_COMPLETE) {
391 if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
392 mxs_chan->status = DMA_IN_PROGRESS;
393 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
394 writel(1, mxs_dma->base +
395 HW_APBHX_CHn_SEMA(mxs_dma, chan));
396 } else {
397 mxs_chan->status = DMA_COMPLETE;
398 }
399 }
400
401 if (mxs_chan->status == DMA_COMPLETE) {
402 if (mxs_chan->reset)
403 return IRQ_HANDLED;
404 dma_cookie_complete(&mxs_chan->desc);
405 }
406
407 /* schedule tasklet on this channel */
408 tasklet_schedule(&mxs_chan->tasklet);
409
410 return IRQ_HANDLED;
411}
412
413static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
414{
415 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
416 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
417 int ret;
418
419 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
420 CCW_BLOCK_SIZE,
421 &mxs_chan->ccw_phys, GFP_KERNEL);
422 if (!mxs_chan->ccw) {
423 ret = -ENOMEM;
424 goto err_alloc;
425 }
426
427 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
428 0, "mxs-dma", mxs_dma);
429 if (ret)
430 goto err_irq;
431
432 ret = clk_prepare_enable(mxs_dma->clk);
433 if (ret)
434 goto err_clk;
435
436 mxs_dma_reset_chan(chan);
437
438 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
439 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
440
441 /* the descriptor is ready */
442 async_tx_ack(&mxs_chan->desc);
443
444 return 0;
445
446err_clk:
447 free_irq(mxs_chan->chan_irq, mxs_dma);
448err_irq:
449 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
450 mxs_chan->ccw, mxs_chan->ccw_phys);
451err_alloc:
452 return ret;
453}
454
455static void mxs_dma_free_chan_resources(struct dma_chan *chan)
456{
457 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
458 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
459
460 mxs_dma_disable_chan(chan);
461
462 free_irq(mxs_chan->chan_irq, mxs_dma);
463
464 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
465 mxs_chan->ccw, mxs_chan->ccw_phys);
466
467 clk_disable_unprepare(mxs_dma->clk);
468}
469
470/*
471 * How to use the flags for ->device_prep_slave_sg() :
472 * [1] If there is only one DMA command in the DMA chain, the code should be:
473 * ......
474 * ->device_prep_slave_sg(DMA_CTRL_ACK);
475 * ......
476 * [2] If there are two DMA commands in the DMA chain, the code should be
477 * ......
478 * ->device_prep_slave_sg(0);
479 * ......
480 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
481 * ......
482 * [3] If there are more than two DMA commands in the DMA chain, the code
483 * should be:
484 * ......
485 * ->device_prep_slave_sg(0); // First
486 * ......
487 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
488 * ......
489 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
490 * ......
491 */
492static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
493 struct dma_chan *chan, struct scatterlist *sgl,
494 unsigned int sg_len, enum dma_transfer_direction direction,
495 unsigned long flags, void *context)
496{
497 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
498 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
499 struct mxs_dma_ccw *ccw;
500 struct scatterlist *sg;
501 u32 i, j;
502 u32 *pio;
503 bool append = flags & DMA_PREP_INTERRUPT;
504 int idx = append ? mxs_chan->desc_count : 0;
505
506 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
507 return NULL;
508
509 if (sg_len + (append ? idx : 0) > NUM_CCW) {
510 dev_err(mxs_dma->dma_device.dev,
511 "maximum number of sg exceeded: %d > %d\n",
512 sg_len, NUM_CCW);
513 goto err_out;
514 }
515
516 mxs_chan->status = DMA_IN_PROGRESS;
517 mxs_chan->flags = 0;
518
519 /*
520 * If the sg is prepared with append flag set, the sg
521 * will be appended to the last prepared sg.
522 */
523 if (append) {
524 BUG_ON(idx < 1);
525 ccw = &mxs_chan->ccw[idx - 1];
526 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
527 ccw->bits |= CCW_CHAIN;
528 ccw->bits &= ~CCW_IRQ;
529 ccw->bits &= ~CCW_DEC_SEM;
530 } else {
531 idx = 0;
532 }
533
534 if (direction == DMA_TRANS_NONE) {
535 ccw = &mxs_chan->ccw[idx++];
536 pio = (u32 *) sgl;
537
538 for (j = 0; j < sg_len;)
539 ccw->pio_words[j++] = *pio++;
540
541 ccw->bits = 0;
542 ccw->bits |= CCW_IRQ;
543 ccw->bits |= CCW_DEC_SEM;
544 if (flags & DMA_CTRL_ACK)
545 ccw->bits |= CCW_WAIT4END;
546 ccw->bits |= CCW_HALT_ON_TERM;
547 ccw->bits |= CCW_TERM_FLUSH;
548 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
549 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
550 } else {
551 for_each_sg(sgl, sg, sg_len, i) {
552 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
553 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
554 sg_dma_len(sg), MAX_XFER_BYTES);
555 goto err_out;
556 }
557
558 ccw = &mxs_chan->ccw[idx++];
559
560 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
561 ccw->bufaddr = sg->dma_address;
562 ccw->xfer_bytes = sg_dma_len(sg);
563
564 ccw->bits = 0;
565 ccw->bits |= CCW_CHAIN;
566 ccw->bits |= CCW_HALT_ON_TERM;
567 ccw->bits |= CCW_TERM_FLUSH;
568 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
569 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
570 COMMAND);
571
572 if (i + 1 == sg_len) {
573 ccw->bits &= ~CCW_CHAIN;
574 ccw->bits |= CCW_IRQ;
575 ccw->bits |= CCW_DEC_SEM;
576 if (flags & DMA_CTRL_ACK)
577 ccw->bits |= CCW_WAIT4END;
578 }
579 }
580 }
581 mxs_chan->desc_count = idx;
582
583 return &mxs_chan->desc;
584
585err_out:
586 mxs_chan->status = DMA_ERROR;
587 return NULL;
588}
589
590static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
591 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
592 size_t period_len, enum dma_transfer_direction direction,
593 unsigned long flags)
594{
595 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
596 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
597 u32 num_periods = buf_len / period_len;
598 u32 i = 0, buf = 0;
599
600 if (mxs_chan->status == DMA_IN_PROGRESS)
601 return NULL;
602
603 mxs_chan->status = DMA_IN_PROGRESS;
604 mxs_chan->flags |= MXS_DMA_SG_LOOP;
605 mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
606
607 if (num_periods > NUM_CCW) {
608 dev_err(mxs_dma->dma_device.dev,
609 "maximum number of sg exceeded: %d > %d\n",
610 num_periods, NUM_CCW);
611 goto err_out;
612 }
613
614 if (period_len > MAX_XFER_BYTES) {
615 dev_err(mxs_dma->dma_device.dev,
616 "maximum period size exceeded: %zu > %d\n",
617 period_len, MAX_XFER_BYTES);
618 goto err_out;
619 }
620
621 while (buf < buf_len) {
622 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
623
624 if (i + 1 == num_periods)
625 ccw->next = mxs_chan->ccw_phys;
626 else
627 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
628
629 ccw->bufaddr = dma_addr;
630 ccw->xfer_bytes = period_len;
631
632 ccw->bits = 0;
633 ccw->bits |= CCW_CHAIN;
634 ccw->bits |= CCW_IRQ;
635 ccw->bits |= CCW_HALT_ON_TERM;
636 ccw->bits |= CCW_TERM_FLUSH;
637 ccw->bits |= CCW_DEC_SEM;
638 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
639 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
640
641 dma_addr += period_len;
642 buf += period_len;
643
644 i++;
645 }
646 mxs_chan->desc_count = i;
647
648 return &mxs_chan->desc;
649
650err_out:
651 mxs_chan->status = DMA_ERROR;
652 return NULL;
653}
654
655static int mxs_dma_terminate_all(struct dma_chan *chan)
656{
657 mxs_dma_reset_chan(chan);
658 mxs_dma_disable_chan(chan);
659
660 return 0;
661}
662
663static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
664 dma_cookie_t cookie, struct dma_tx_state *txstate)
665{
666 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
667 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
668 u32 residue = 0;
669
670 if (mxs_chan->status == DMA_IN_PROGRESS &&
671 mxs_chan->flags & MXS_DMA_SG_LOOP) {
672 struct mxs_dma_ccw *last_ccw;
673 u32 bar;
674
675 last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
676 residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
677
678 bar = readl(mxs_dma->base +
679 HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
680 residue -= bar;
681 }
682
683 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
684 residue);
685
686 return mxs_chan->status;
687}
688
689static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
690{
691 int ret;
692
693 ret = clk_prepare_enable(mxs_dma->clk);
694 if (ret)
695 return ret;
696
697 ret = stmp_reset_block(mxs_dma->base);
698 if (ret)
699 goto err_out;
700
701 /* enable apbh burst */
702 if (dma_is_apbh(mxs_dma)) {
703 writel(BM_APBH_CTRL0_APB_BURST_EN,
704 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
705 writel(BM_APBH_CTRL0_APB_BURST8_EN,
706 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
707 }
708
709 /* enable irq for all the channels */
710 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
711 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
712
713err_out:
714 clk_disable_unprepare(mxs_dma->clk);
715 return ret;
716}
717
718struct mxs_dma_filter_param {
719 struct device_node *of_node;
720 unsigned int chan_id;
721};
722
723static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
724{
725 struct mxs_dma_filter_param *param = fn_param;
726 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
727 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
728 int chan_irq;
729
730 if (mxs_dma->dma_device.dev->of_node != param->of_node)
731 return false;
732
733 if (chan->chan_id != param->chan_id)
734 return false;
735
736 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
737 if (chan_irq < 0)
738 return false;
739
740 mxs_chan->chan_irq = chan_irq;
741
742 return true;
743}
744
745static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
746 struct of_dma *ofdma)
747{
748 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
749 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
750 struct mxs_dma_filter_param param;
751
752 if (dma_spec->args_count != 1)
753 return NULL;
754
755 param.of_node = ofdma->of_node;
756 param.chan_id = dma_spec->args[0];
757
758 if (param.chan_id >= mxs_dma->nr_channels)
759 return NULL;
760
761 return dma_request_channel(mask, mxs_dma_filter_fn, &param);
762}
763
764static int __init mxs_dma_probe(struct platform_device *pdev)
765{
766 struct device_node *np = pdev->dev.of_node;
767 const struct platform_device_id *id_entry;
768 const struct of_device_id *of_id;
769 const struct mxs_dma_type *dma_type;
770 struct mxs_dma_engine *mxs_dma;
771 struct resource *iores;
772 int ret, i;
773
774 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
775 if (!mxs_dma)
776 return -ENOMEM;
777
778 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
779 if (ret) {
780 dev_err(&pdev->dev, "failed to read dma-channels\n");
781 return ret;
782 }
783
784 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
785 if (of_id)
786 id_entry = of_id->data;
787 else
788 id_entry = platform_get_device_id(pdev);
789
790 dma_type = (struct mxs_dma_type *)id_entry->driver_data;
791 mxs_dma->type = dma_type->type;
792 mxs_dma->dev_id = dma_type->id;
793
794 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
796 if (IS_ERR(mxs_dma->base))
797 return PTR_ERR(mxs_dma->base);
798
799 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
800 if (IS_ERR(mxs_dma->clk))
801 return PTR_ERR(mxs_dma->clk);
802
803 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
804 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
805
806 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
807
808 /* Initialize channel parameters */
809 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
810 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
811
812 mxs_chan->mxs_dma = mxs_dma;
813 mxs_chan->chan.device = &mxs_dma->dma_device;
814 dma_cookie_init(&mxs_chan->chan);
815
816 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
817 (unsigned long) mxs_chan);
818
819
820 /* Add the channel to mxs_chan list */
821 list_add_tail(&mxs_chan->chan.device_node,
822 &mxs_dma->dma_device.channels);
823 }
824
825 ret = mxs_dma_init(mxs_dma);
826 if (ret)
827 return ret;
828
829 mxs_dma->pdev = pdev;
830 mxs_dma->dma_device.dev = &pdev->dev;
831
832 /* mxs_dma gets 65535 bytes maximum sg size */
833 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
834 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
835
836 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
837 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
838 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
839 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
840 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
841 mxs_dma->dma_device.device_pause = mxs_dma_pause_chan;
842 mxs_dma->dma_device.device_resume = mxs_dma_resume_chan;
843 mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all;
844 mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
845 mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
846 mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
847 mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
848 mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan;
849
850 ret = dmaenginem_async_device_register(&mxs_dma->dma_device);
851 if (ret) {
852 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
853 return ret;
854 }
855
856 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
857 if (ret) {
858 dev_err(mxs_dma->dma_device.dev,
859 "failed to register controller\n");
860 }
861
862 dev_info(mxs_dma->dma_device.dev, "initialized\n");
863
864 return 0;
865}
866
867static struct platform_driver mxs_dma_driver = {
868 .driver = {
869 .name = "mxs-dma",
870 .of_match_table = mxs_dma_dt_ids,
871 },
872 .id_table = mxs_dma_ids,
873};
874
875static int __init mxs_dma_module_init(void)
876{
877 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
878}
879subsys_initcall(mxs_dma_module_init);
880