1/*
2 *
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
5 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
6 *
7 * License terms: GPL V2.0.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 *
18 * DMA Router driver for STM32 DMA MUX
19 *
20 * Based on TI DMA Crossbar driver
21 *
22 */
23
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/of_device.h>
30#include <linux/of_dma.h>
31#include <linux/pm_runtime.h>
32#include <linux/reset.h>
33#include <linux/slab.h>
34#include <linux/spinlock.h>
35
36#define STM32_DMAMUX_CCR(x) (0x4 * (x))
37#define STM32_DMAMUX_MAX_DMA_REQUESTS 32
38#define STM32_DMAMUX_MAX_REQUESTS 255
39
40struct stm32_dmamux {
41 u32 master;
42 u32 request;
43 u32 chan_id;
44};
45
46struct stm32_dmamux_data {
47 struct dma_router dmarouter;
48 struct clk *clk;
49 struct reset_control *rst;
50 void __iomem *iomem;
51 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
52 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
53 spinlock_t lock; /* Protects register access */
54 unsigned long *dma_inuse; /* Used DMA channel */
55 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
56 * [0] holds number of DMA Masters.
57 * To be kept at very end end of this structure
58 */
59};
60
61static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
62{
63 return readl_relaxed(iomem + reg);
64}
65
66static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
67{
68 writel_relaxed(val, iomem + reg);
69}
70
71static void stm32_dmamux_free(struct device *dev, void *route_data)
72{
73 struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
74 struct stm32_dmamux *mux = route_data;
75 unsigned long flags;
76
77 /* Clear dma request */
78 spin_lock_irqsave(&dmamux->lock, flags);
79
80 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
81 clear_bit(mux->chan_id, dmamux->dma_inuse);
82
83 pm_runtime_put_sync(dev);
84
85 spin_unlock_irqrestore(&dmamux->lock, flags);
86
87 dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
88 mux->request, mux->master, mux->chan_id);
89
90 kfree(mux);
91}
92
93static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
94 struct of_dma *ofdma)
95{
96 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
97 struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
98 struct stm32_dmamux *mux;
99 u32 i, min, max;
100 int ret;
101 unsigned long flags;
102
103 if (dma_spec->args_count != 3) {
104 dev_err(&pdev->dev, "invalid number of dma mux args\n");
105 return ERR_PTR(-EINVAL);
106 }
107
108 if (dma_spec->args[0] > dmamux->dmamux_requests) {
109 dev_err(&pdev->dev, "invalid mux request number: %d\n",
110 dma_spec->args[0]);
111 return ERR_PTR(-EINVAL);
112 }
113
114 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
115 if (!mux)
116 return ERR_PTR(-ENOMEM);
117
118 spin_lock_irqsave(&dmamux->lock, flags);
119 mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
120 dmamux->dma_requests);
121
122 if (mux->chan_id == dmamux->dma_requests) {
123 spin_unlock_irqrestore(&dmamux->lock, flags);
124 dev_err(&pdev->dev, "Run out of free DMA requests\n");
125 ret = -ENOMEM;
126 goto error_chan_id;
127 }
128 set_bit(mux->chan_id, dmamux->dma_inuse);
129 spin_unlock_irqrestore(&dmamux->lock, flags);
130
131 /* Look for DMA Master */
132 for (i = 1, min = 0, max = dmamux->dma_reqs[i];
133 i <= dmamux->dma_reqs[0];
134 min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
135 if (mux->chan_id < max)
136 break;
137 mux->master = i - 1;
138
139 /* The of_node_put() will be done in of_dma_router_xlate function */
140 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
141 if (!dma_spec->np) {
142 dev_err(&pdev->dev, "can't get dma master\n");
143 ret = -EINVAL;
144 goto error;
145 }
146
147 /* Set dma request */
148 spin_lock_irqsave(&dmamux->lock, flags);
149 ret = pm_runtime_get_sync(&pdev->dev);
150 if (ret < 0) {
151 spin_unlock_irqrestore(&dmamux->lock, flags);
152 goto error;
153 }
154 spin_unlock_irqrestore(&dmamux->lock, flags);
155
156 mux->request = dma_spec->args[0];
157
158 /* craft DMA spec */
159 dma_spec->args[3] = dma_spec->args[2];
160 dma_spec->args[2] = dma_spec->args[1];
161 dma_spec->args[1] = 0;
162 dma_spec->args[0] = mux->chan_id - min;
163 dma_spec->args_count = 4;
164
165 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
166 mux->request);
167 dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
168 mux->request, mux->master, mux->chan_id);
169
170 return mux;
171
172error:
173 clear_bit(mux->chan_id, dmamux->dma_inuse);
174
175error_chan_id:
176 kfree(mux);
177 return ERR_PTR(ret);
178}
179
180static const struct of_device_id stm32_stm32dma_master_match[] = {
181 { .compatible = "st,stm32-dma", },
182 {},
183};
184
185static int stm32_dmamux_probe(struct platform_device *pdev)
186{
187 struct device_node *node = pdev->dev.of_node;
188 const struct of_device_id *match;
189 struct device_node *dma_node;
190 struct stm32_dmamux_data *stm32_dmamux;
191 struct resource *res;
192 void __iomem *iomem;
193 int i, count, ret;
194 u32 dma_req;
195
196 if (!node)
197 return -ENODEV;
198
199 count = device_property_read_u32_array(&pdev->dev, "dma-masters",
200 NULL, 0);
201 if (count < 0) {
202 dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
203 return -ENODEV;
204 }
205
206 stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
207 sizeof(u32) * (count + 1), GFP_KERNEL);
208 if (!stm32_dmamux)
209 return -ENOMEM;
210
211 dma_req = 0;
212 for (i = 1; i <= count; i++) {
213 dma_node = of_parse_phandle(node, "dma-masters", i - 1);
214
215 match = of_match_node(stm32_stm32dma_master_match, dma_node);
216 if (!match) {
217 dev_err(&pdev->dev, "DMA master is not supported\n");
218 of_node_put(dma_node);
219 return -EINVAL;
220 }
221
222 if (of_property_read_u32(dma_node, "dma-requests",
223 &stm32_dmamux->dma_reqs[i])) {
224 dev_info(&pdev->dev,
225 "Missing MUX output information, using %u.\n",
226 STM32_DMAMUX_MAX_DMA_REQUESTS);
227 stm32_dmamux->dma_reqs[i] =
228 STM32_DMAMUX_MAX_DMA_REQUESTS;
229 }
230 dma_req += stm32_dmamux->dma_reqs[i];
231 of_node_put(dma_node);
232 }
233
234 if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
235 dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
236 return -ENODEV;
237 }
238
239 stm32_dmamux->dma_requests = dma_req;
240 stm32_dmamux->dma_reqs[0] = count;
241 stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,
242 BITS_TO_LONGS(dma_req),
243 sizeof(unsigned long),
244 GFP_KERNEL);
245 if (!stm32_dmamux->dma_inuse)
246 return -ENOMEM;
247
248 if (device_property_read_u32(&pdev->dev, "dma-requests",
249 &stm32_dmamux->dmamux_requests)) {
250 stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
251 dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
252 stm32_dmamux->dmamux_requests);
253 }
254 pm_runtime_get_noresume(&pdev->dev);
255
256 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
257 iomem = devm_ioremap_resource(&pdev->dev, res);
258 if (IS_ERR(iomem))
259 return PTR_ERR(iomem);
260
261 spin_lock_init(&stm32_dmamux->lock);
262
263 stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
264 if (IS_ERR(stm32_dmamux->clk)) {
265 ret = PTR_ERR(stm32_dmamux->clk);
266 if (ret == -EPROBE_DEFER)
267 dev_info(&pdev->dev, "Missing controller clock\n");
268 return ret;
269 }
270
271 stm32_dmamux->rst = devm_reset_control_get(&pdev->dev, NULL);
272 if (!IS_ERR(stm32_dmamux->rst)) {
273 reset_control_assert(stm32_dmamux->rst);
274 udelay(2);
275 reset_control_deassert(stm32_dmamux->rst);
276 }
277
278 stm32_dmamux->iomem = iomem;
279 stm32_dmamux->dmarouter.dev = &pdev->dev;
280 stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
281
282 platform_set_drvdata(pdev, stm32_dmamux);
283 pm_runtime_set_active(&pdev->dev);
284 pm_runtime_enable(&pdev->dev);
285
286 if (!IS_ERR(stm32_dmamux->clk)) {
287 ret = clk_prepare_enable(stm32_dmamux->clk);
288 if (ret < 0) {
289 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
290 return ret;
291 }
292 }
293
294 pm_runtime_get_noresume(&pdev->dev);
295
296 /* Reset the dmamux */
297 for (i = 0; i < stm32_dmamux->dma_requests; i++)
298 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
299
300 pm_runtime_put(&pdev->dev);
301
302 return of_dma_router_register(node, stm32_dmamux_route_allocate,
303 &stm32_dmamux->dmarouter);
304}
305
306#ifdef CONFIG_PM
307static int stm32_dmamux_runtime_suspend(struct device *dev)
308{
309 struct platform_device *pdev =
310 container_of(dev, struct platform_device, dev);
311 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
312
313 clk_disable_unprepare(stm32_dmamux->clk);
314
315 return 0;
316}
317
318static int stm32_dmamux_runtime_resume(struct device *dev)
319{
320 struct platform_device *pdev =
321 container_of(dev, struct platform_device, dev);
322 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
323 int ret;
324
325 ret = clk_prepare_enable(stm32_dmamux->clk);
326 if (ret) {
327 dev_err(&pdev->dev, "failed to prepare_enable clock\n");
328 return ret;
329 }
330
331 return 0;
332}
333#endif
334
335static const struct dev_pm_ops stm32_dmamux_pm_ops = {
336 SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
337 stm32_dmamux_runtime_resume, NULL)
338};
339
340static const struct of_device_id stm32_dmamux_match[] = {
341 { .compatible = "st,stm32h7-dmamux" },
342 {},
343};
344
345static struct platform_driver stm32_dmamux_driver = {
346 .probe = stm32_dmamux_probe,
347 .driver = {
348 .name = "stm32-dmamux",
349 .of_match_table = stm32_dmamux_match,
350 .pm = &stm32_dmamux_pm_ops,
351 },
352};
353
354static int __init stm32_dmamux_init(void)
355{
356 return platform_driver_register(&stm32_dmamux_driver);
357}
358arch_initcall(stm32_dmamux_init);
359
360MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
361MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
362MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
363MODULE_LICENSE("GPL v2");
364