1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * DMA driver for Xilinx Video DMA Engine |
4 | * |
5 | * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. |
6 | * |
7 | * Based on the Freescale DMA driver. |
8 | * |
9 | * Description: |
10 | * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP |
11 | * core that provides high-bandwidth direct memory access between memory |
12 | * and AXI4-Stream type video target peripherals. The core provides efficient |
13 | * two dimensional DMA operations with independent asynchronous read (S2MM) |
14 | * and write (MM2S) channel operation. It can be configured to have either |
15 | * one channel or two channels. If configured as two channels, one is to |
16 | * transmit to the video device (MM2S) and another is to receive from the |
17 | * video device (S2MM). Initialization, status, interrupt and management |
18 | * registers are accessed through an AXI4-Lite slave interface. |
19 | * |
20 | * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that |
21 | * provides high-bandwidth one dimensional direct memory access between memory |
22 | * and AXI4-Stream target peripherals. It supports one receive and one |
23 | * transmit channel, both of them optional at synthesis time. |
24 | * |
25 | * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory |
26 | * Access (DMA) between a memory-mapped source address and a memory-mapped |
27 | * destination address. |
28 | * |
29 | * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft |
30 | * Xilinx IP that provides high-bandwidth direct memory access between |
31 | * memory and AXI4-Stream target peripherals. It provides scatter gather |
32 | * (SG) interface with multiple channels independent configuration support. |
33 | * |
34 | */ |
35 | |
36 | #include <linux/bitops.h> |
37 | #include <linux/dmapool.h> |
38 | #include <linux/dma/xilinx_dma.h> |
39 | #include <linux/init.h> |
40 | #include <linux/interrupt.h> |
41 | #include <linux/io.h> |
42 | #include <linux/iopoll.h> |
43 | #include <linux/module.h> |
44 | #include <linux/of.h> |
45 | #include <linux/of_dma.h> |
46 | #include <linux/of_irq.h> |
47 | #include <linux/platform_device.h> |
48 | #include <linux/slab.h> |
49 | #include <linux/clk.h> |
50 | #include <linux/io-64-nonatomic-lo-hi.h> |
51 | |
52 | #include "../dmaengine.h" |
53 | |
54 | /* Register/Descriptor Offsets */ |
55 | #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 |
56 | #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 |
57 | #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 |
58 | #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 |
59 | |
60 | /* Control Registers */ |
61 | #define XILINX_DMA_REG_DMACR 0x0000 |
62 | #define XILINX_DMA_DMACR_DELAY_MAX 0xff |
63 | #define XILINX_DMA_DMACR_DELAY_SHIFT 24 |
64 | #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff |
65 | #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 |
66 | #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) |
67 | #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) |
68 | #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) |
69 | #define XILINX_DMA_DMACR_MASTER_SHIFT 8 |
70 | #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 |
71 | #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) |
72 | #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) |
73 | #define XILINX_DMA_DMACR_RESET BIT(2) |
74 | #define XILINX_DMA_DMACR_CIRC_EN BIT(1) |
75 | #define XILINX_DMA_DMACR_RUNSTOP BIT(0) |
76 | #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) |
77 | #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) |
78 | #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) |
79 | #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) |
80 | |
81 | #define XILINX_DMA_REG_DMASR 0x0004 |
82 | #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) |
83 | #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) |
84 | #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) |
85 | #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) |
86 | #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) |
87 | #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) |
88 | #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) |
89 | #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) |
90 | #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) |
91 | #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) |
92 | #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) |
93 | #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) |
94 | #define XILINX_DMA_DMASR_SG_MASK BIT(3) |
95 | #define XILINX_DMA_DMASR_IDLE BIT(1) |
96 | #define XILINX_DMA_DMASR_HALTED BIT(0) |
97 | #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) |
98 | #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) |
99 | |
100 | #define XILINX_DMA_REG_CURDESC 0x0008 |
101 | #define XILINX_DMA_REG_TAILDESC 0x0010 |
102 | #define XILINX_DMA_REG_REG_INDEX 0x0014 |
103 | #define XILINX_DMA_REG_FRMSTORE 0x0018 |
104 | #define XILINX_DMA_REG_THRESHOLD 0x001c |
105 | #define XILINX_DMA_REG_FRMPTR_STS 0x0024 |
106 | #define XILINX_DMA_REG_PARK_PTR 0x0028 |
107 | #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 |
108 | #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) |
109 | #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 |
110 | #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) |
111 | #define XILINX_DMA_REG_VDMA_VERSION 0x002c |
112 | |
113 | /* Register Direct Mode Registers */ |
114 | #define XILINX_DMA_REG_VSIZE 0x0000 |
115 | #define XILINX_DMA_REG_HSIZE 0x0004 |
116 | |
117 | #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 |
118 | #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 |
119 | #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 |
120 | |
121 | #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) |
122 | #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) |
123 | |
124 | #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec |
125 | #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) |
126 | |
127 | /* HW specific definitions */ |
128 | #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 |
129 | #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 |
130 | #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 |
131 | |
132 | #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ |
133 | (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ |
134 | XILINX_DMA_DMASR_DLY_CNT_IRQ | \ |
135 | XILINX_DMA_DMASR_ERR_IRQ) |
136 | |
137 | #define XILINX_DMA_DMASR_ALL_ERR_MASK \ |
138 | (XILINX_DMA_DMASR_EOL_LATE_ERR | \ |
139 | XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
140 | XILINX_DMA_DMASR_SG_DEC_ERR | \ |
141 | XILINX_DMA_DMASR_SG_SLV_ERR | \ |
142 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
143 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
144 | XILINX_DMA_DMASR_DMA_DEC_ERR | \ |
145 | XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ |
146 | XILINX_DMA_DMASR_DMA_INT_ERR) |
147 | |
148 | /* |
149 | * Recoverable errors are DMA Internal error, SOF Early, EOF Early |
150 | * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC |
151 | * is enabled in the h/w system. |
152 | */ |
153 | #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ |
154 | (XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
155 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
156 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
157 | XILINX_DMA_DMASR_DMA_INT_ERR) |
158 | |
159 | /* Axi VDMA Flush on Fsync bits */ |
160 | #define XILINX_DMA_FLUSH_S2MM 3 |
161 | #define XILINX_DMA_FLUSH_MM2S 2 |
162 | #define XILINX_DMA_FLUSH_BOTH 1 |
163 | |
164 | /* Delay loop counter to prevent hardware failure */ |
165 | #define XILINX_DMA_LOOP_COUNT 1000000 |
166 | |
167 | /* AXI DMA Specific Registers/Offsets */ |
168 | #define XILINX_DMA_REG_SRCDSTADDR 0x18 |
169 | #define XILINX_DMA_REG_BTT 0x28 |
170 | |
171 | /* AXI DMA Specific Masks/Bit fields */ |
172 | #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 |
173 | #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 |
174 | #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 |
175 | #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) |
176 | #define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) |
177 | #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) |
178 | #define XILINX_DMA_CR_COALESCE_SHIFT 16 |
179 | #define XILINX_DMA_CR_DELAY_SHIFT 24 |
180 | #define XILINX_DMA_BD_SOP BIT(27) |
181 | #define XILINX_DMA_BD_EOP BIT(26) |
182 | #define XILINX_DMA_BD_COMP_MASK BIT(31) |
183 | #define XILINX_DMA_COALESCE_MAX 255 |
184 | #define XILINX_DMA_NUM_DESCS 512 |
185 | #define XILINX_DMA_NUM_APP_WORDS 5 |
186 | |
187 | /* AXI CDMA Specific Registers/Offsets */ |
188 | #define XILINX_CDMA_REG_SRCADDR 0x18 |
189 | #define XILINX_CDMA_REG_DSTADDR 0x20 |
190 | |
191 | /* AXI CDMA Specific Masks */ |
192 | #define XILINX_CDMA_CR_SGMODE BIT(3) |
193 | |
194 | #define xilinx_prep_dma_addr_t(addr) \ |
195 | ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) |
196 | |
197 | /* AXI MCDMA Specific Registers/Offsets */ |
198 | #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 |
199 | #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 |
200 | #define XILINX_MCDMA_CHEN_OFFSET 0x0008 |
201 | #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 |
202 | #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 |
203 | #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 |
204 | #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) |
205 | #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) |
206 | #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) |
207 | #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) |
208 | |
209 | /* AXI MCDMA Specific Masks/Shifts */ |
210 | #define XILINX_MCDMA_COALESCE_SHIFT 16 |
211 | #define XILINX_MCDMA_COALESCE_MAX 24 |
212 | #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) |
213 | #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) |
214 | #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) |
215 | #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) |
216 | #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) |
217 | #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) |
218 | #define XILINX_MCDMA_BD_EOP BIT(30) |
219 | #define XILINX_MCDMA_BD_SOP BIT(31) |
220 | |
221 | /** |
222 | * struct xilinx_vdma_desc_hw - Hardware Descriptor |
223 | * @next_desc: Next Descriptor Pointer @0x00 |
224 | * @pad1: Reserved @0x04 |
225 | * @buf_addr: Buffer address @0x08 |
226 | * @buf_addr_msb: MSB of Buffer address @0x0C |
227 | * @vsize: Vertical Size @0x10 |
228 | * @hsize: Horizontal Size @0x14 |
229 | * @stride: Number of bytes between the first |
230 | * pixels of each horizontal line @0x18 |
231 | */ |
232 | struct xilinx_vdma_desc_hw { |
233 | u32 next_desc; |
234 | u32 pad1; |
235 | u32 buf_addr; |
236 | u32 buf_addr_msb; |
237 | u32 vsize; |
238 | u32 hsize; |
239 | u32 stride; |
240 | } __aligned(64); |
241 | |
242 | /** |
243 | * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA |
244 | * @next_desc: Next Descriptor Pointer @0x00 |
245 | * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 |
246 | * @buf_addr: Buffer address @0x08 |
247 | * @buf_addr_msb: MSB of Buffer address @0x0C |
248 | * @reserved1: Reserved @0x10 |
249 | * @reserved2: Reserved @0x14 |
250 | * @control: Control field @0x18 |
251 | * @status: Status field @0x1C |
252 | * @app: APP Fields @0x20 - 0x30 |
253 | */ |
254 | struct xilinx_axidma_desc_hw { |
255 | u32 next_desc; |
256 | u32 next_desc_msb; |
257 | u32 buf_addr; |
258 | u32 buf_addr_msb; |
259 | u32 reserved1; |
260 | u32 reserved2; |
261 | u32 control; |
262 | u32 status; |
263 | u32 app[XILINX_DMA_NUM_APP_WORDS]; |
264 | } __aligned(64); |
265 | |
266 | /** |
267 | * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA |
268 | * @next_desc: Next Descriptor Pointer @0x00 |
269 | * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 |
270 | * @buf_addr: Buffer address @0x08 |
271 | * @buf_addr_msb: MSB of Buffer address @0x0C |
272 | * @rsvd: Reserved field @0x10 |
273 | * @control: Control Information field @0x14 |
274 | * @status: Status field @0x18 |
275 | * @sideband_status: Status of sideband signals @0x1C |
276 | * @app: APP Fields @0x20 - 0x30 |
277 | */ |
278 | struct xilinx_aximcdma_desc_hw { |
279 | u32 next_desc; |
280 | u32 next_desc_msb; |
281 | u32 buf_addr; |
282 | u32 buf_addr_msb; |
283 | u32 rsvd; |
284 | u32 control; |
285 | u32 status; |
286 | u32 sideband_status; |
287 | u32 app[XILINX_DMA_NUM_APP_WORDS]; |
288 | } __aligned(64); |
289 | |
290 | /** |
291 | * struct xilinx_cdma_desc_hw - Hardware Descriptor |
292 | * @next_desc: Next Descriptor Pointer @0x00 |
293 | * @next_desc_msb: Next Descriptor Pointer MSB @0x04 |
294 | * @src_addr: Source address @0x08 |
295 | * @src_addr_msb: Source address MSB @0x0C |
296 | * @dest_addr: Destination address @0x10 |
297 | * @dest_addr_msb: Destination address MSB @0x14 |
298 | * @control: Control field @0x18 |
299 | * @status: Status field @0x1C |
300 | */ |
301 | struct xilinx_cdma_desc_hw { |
302 | u32 next_desc; |
303 | u32 next_desc_msb; |
304 | u32 src_addr; |
305 | u32 src_addr_msb; |
306 | u32 dest_addr; |
307 | u32 dest_addr_msb; |
308 | u32 control; |
309 | u32 status; |
310 | } __aligned(64); |
311 | |
312 | /** |
313 | * struct xilinx_vdma_tx_segment - Descriptor segment |
314 | * @hw: Hardware descriptor |
315 | * @node: Node in the descriptor segments list |
316 | * @phys: Physical address of segment |
317 | */ |
318 | struct xilinx_vdma_tx_segment { |
319 | struct xilinx_vdma_desc_hw hw; |
320 | struct list_head node; |
321 | dma_addr_t phys; |
322 | } __aligned(64); |
323 | |
324 | /** |
325 | * struct xilinx_axidma_tx_segment - Descriptor segment |
326 | * @hw: Hardware descriptor |
327 | * @node: Node in the descriptor segments list |
328 | * @phys: Physical address of segment |
329 | */ |
330 | struct xilinx_axidma_tx_segment { |
331 | struct xilinx_axidma_desc_hw hw; |
332 | struct list_head node; |
333 | dma_addr_t phys; |
334 | } __aligned(64); |
335 | |
336 | /** |
337 | * struct xilinx_aximcdma_tx_segment - Descriptor segment |
338 | * @hw: Hardware descriptor |
339 | * @node: Node in the descriptor segments list |
340 | * @phys: Physical address of segment |
341 | */ |
342 | struct xilinx_aximcdma_tx_segment { |
343 | struct xilinx_aximcdma_desc_hw hw; |
344 | struct list_head node; |
345 | dma_addr_t phys; |
346 | } __aligned(64); |
347 | |
348 | /** |
349 | * struct xilinx_cdma_tx_segment - Descriptor segment |
350 | * @hw: Hardware descriptor |
351 | * @node: Node in the descriptor segments list |
352 | * @phys: Physical address of segment |
353 | */ |
354 | struct xilinx_cdma_tx_segment { |
355 | struct xilinx_cdma_desc_hw hw; |
356 | struct list_head node; |
357 | dma_addr_t phys; |
358 | } __aligned(64); |
359 | |
360 | /** |
361 | * struct xilinx_dma_tx_descriptor - Per Transaction structure |
362 | * @async_tx: Async transaction descriptor |
363 | * @segments: TX segments list |
364 | * @node: Node in the channel descriptors list |
365 | * @cyclic: Check for cyclic transfers. |
366 | * @err: Whether the descriptor has an error. |
367 | * @residue: Residue of the completed descriptor |
368 | */ |
369 | struct xilinx_dma_tx_descriptor { |
370 | struct dma_async_tx_descriptor async_tx; |
371 | struct list_head segments; |
372 | struct list_head node; |
373 | bool cyclic; |
374 | bool err; |
375 | u32 residue; |
376 | }; |
377 | |
378 | /** |
379 | * struct xilinx_dma_chan - Driver specific DMA channel structure |
380 | * @xdev: Driver specific device structure |
381 | * @ctrl_offset: Control registers offset |
382 | * @desc_offset: TX descriptor registers offset |
383 | * @lock: Descriptor operation lock |
384 | * @pending_list: Descriptors waiting |
385 | * @active_list: Descriptors ready to submit |
386 | * @done_list: Complete descriptors |
387 | * @free_seg_list: Free descriptors |
388 | * @common: DMA common channel |
389 | * @desc_pool: Descriptors pool |
390 | * @dev: The dma device |
391 | * @irq: Channel IRQ |
392 | * @id: Channel ID |
393 | * @direction: Transfer direction |
394 | * @num_frms: Number of frames |
395 | * @has_sg: Support scatter transfers |
396 | * @cyclic: Check for cyclic transfers. |
397 | * @genlock: Support genlock mode |
398 | * @err: Channel has errors |
399 | * @idle: Check for channel idle |
400 | * @terminating: Check for channel being synchronized by user |
401 | * @tasklet: Cleanup work after irq |
402 | * @config: Device configuration info |
403 | * @flush_on_fsync: Flush on Frame sync |
404 | * @desc_pendingcount: Descriptor pending count |
405 | * @ext_addr: Indicates 64 bit addressing is supported by dma channel |
406 | * @desc_submitcount: Descriptor h/w submitted count |
407 | * @seg_v: Statically allocated segments base |
408 | * @seg_mv: Statically allocated segments base for MCDMA |
409 | * @seg_p: Physical allocated segments base |
410 | * @cyclic_seg_v: Statically allocated segment base for cyclic transfers |
411 | * @cyclic_seg_p: Physical allocated segments base for cyclic dma |
412 | * @start_transfer: Differentiate b/w DMA IP's transfer |
413 | * @stop_transfer: Differentiate b/w DMA IP's quiesce |
414 | * @tdest: TDEST value for mcdma |
415 | * @has_vflip: S2MM vertical flip |
416 | * @irq_delay: Interrupt delay timeout |
417 | */ |
418 | struct xilinx_dma_chan { |
419 | struct xilinx_dma_device *xdev; |
420 | u32 ctrl_offset; |
421 | u32 desc_offset; |
422 | spinlock_t lock; |
423 | struct list_head pending_list; |
424 | struct list_head active_list; |
425 | struct list_head done_list; |
426 | struct list_head free_seg_list; |
427 | struct dma_chan common; |
428 | struct dma_pool *desc_pool; |
429 | struct device *dev; |
430 | int irq; |
431 | int id; |
432 | enum dma_transfer_direction direction; |
433 | int num_frms; |
434 | bool has_sg; |
435 | bool cyclic; |
436 | bool genlock; |
437 | bool err; |
438 | bool idle; |
439 | bool terminating; |
440 | struct tasklet_struct tasklet; |
441 | struct xilinx_vdma_config config; |
442 | bool flush_on_fsync; |
443 | u32 desc_pendingcount; |
444 | bool ext_addr; |
445 | u32 desc_submitcount; |
446 | struct xilinx_axidma_tx_segment *seg_v; |
447 | struct xilinx_aximcdma_tx_segment *seg_mv; |
448 | dma_addr_t seg_p; |
449 | struct xilinx_axidma_tx_segment *cyclic_seg_v; |
450 | dma_addr_t cyclic_seg_p; |
451 | void (*start_transfer)(struct xilinx_dma_chan *chan); |
452 | int (*stop_transfer)(struct xilinx_dma_chan *chan); |
453 | u16 tdest; |
454 | bool has_vflip; |
455 | u8 irq_delay; |
456 | }; |
457 | |
458 | /** |
459 | * enum xdma_ip_type - DMA IP type. |
460 | * |
461 | * @XDMA_TYPE_AXIDMA: Axi dma ip. |
462 | * @XDMA_TYPE_CDMA: Axi cdma ip. |
463 | * @XDMA_TYPE_VDMA: Axi vdma ip. |
464 | * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. |
465 | * |
466 | */ |
467 | enum xdma_ip_type { |
468 | XDMA_TYPE_AXIDMA = 0, |
469 | XDMA_TYPE_CDMA, |
470 | XDMA_TYPE_VDMA, |
471 | XDMA_TYPE_AXIMCDMA |
472 | }; |
473 | |
474 | struct xilinx_dma_config { |
475 | enum xdma_ip_type dmatype; |
476 | int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, |
477 | struct clk **tx_clk, struct clk **txs_clk, |
478 | struct clk **rx_clk, struct clk **rxs_clk); |
479 | irqreturn_t (*irq_handler)(int irq, void *data); |
480 | const int max_channels; |
481 | }; |
482 | |
483 | /** |
484 | * struct xilinx_dma_device - DMA device structure |
485 | * @regs: I/O mapped base address |
486 | * @dev: Device Structure |
487 | * @common: DMA device structure |
488 | * @chan: Driver specific DMA channel |
489 | * @flush_on_fsync: Flush on frame sync |
490 | * @ext_addr: Indicates 64 bit addressing is supported by dma device |
491 | * @pdev: Platform device structure pointer |
492 | * @dma_config: DMA config structure |
493 | * @axi_clk: DMA Axi4-lite interace clock |
494 | * @tx_clk: DMA mm2s clock |
495 | * @txs_clk: DMA mm2s stream clock |
496 | * @rx_clk: DMA s2mm clock |
497 | * @rxs_clk: DMA s2mm stream clock |
498 | * @s2mm_chan_id: DMA s2mm channel identifier |
499 | * @mm2s_chan_id: DMA mm2s channel identifier |
500 | * @max_buffer_len: Max buffer length |
501 | * @has_axistream_connected: AXI DMA connected to AXI Stream IP |
502 | */ |
503 | struct xilinx_dma_device { |
504 | void __iomem *regs; |
505 | struct device *dev; |
506 | struct dma_device common; |
507 | struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; |
508 | u32 flush_on_fsync; |
509 | bool ext_addr; |
510 | struct platform_device *pdev; |
511 | const struct xilinx_dma_config *dma_config; |
512 | struct clk *axi_clk; |
513 | struct clk *tx_clk; |
514 | struct clk *txs_clk; |
515 | struct clk *rx_clk; |
516 | struct clk *rxs_clk; |
517 | u32 s2mm_chan_id; |
518 | u32 mm2s_chan_id; |
519 | u32 max_buffer_len; |
520 | bool has_axistream_connected; |
521 | }; |
522 | |
523 | /* Macros */ |
524 | #define to_xilinx_chan(chan) \ |
525 | container_of(chan, struct xilinx_dma_chan, common) |
526 | #define to_dma_tx_descriptor(tx) \ |
527 | container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) |
528 | #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ |
529 | readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ |
530 | val, cond, delay_us, timeout_us) |
531 | |
532 | /* IO accessors */ |
533 | static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) |
534 | { |
535 | return ioread32(chan->xdev->regs + reg); |
536 | } |
537 | |
538 | static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) |
539 | { |
540 | iowrite32(value, chan->xdev->regs + reg); |
541 | } |
542 | |
543 | static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, |
544 | u32 value) |
545 | { |
546 | dma_write(chan, reg: chan->desc_offset + reg, value); |
547 | } |
548 | |
549 | static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) |
550 | { |
551 | return dma_read(chan, reg: chan->ctrl_offset + reg); |
552 | } |
553 | |
554 | static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, |
555 | u32 value) |
556 | { |
557 | dma_write(chan, reg: chan->ctrl_offset + reg, value); |
558 | } |
559 | |
560 | static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, |
561 | u32 clr) |
562 | { |
563 | dma_ctrl_write(chan, reg, value: dma_ctrl_read(chan, reg) & ~clr); |
564 | } |
565 | |
566 | static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, |
567 | u32 set) |
568 | { |
569 | dma_ctrl_write(chan, reg, value: dma_ctrl_read(chan, reg) | set); |
570 | } |
571 | |
572 | /** |
573 | * vdma_desc_write_64 - 64-bit descriptor write |
574 | * @chan: Driver specific VDMA channel |
575 | * @reg: Register to write |
576 | * @value_lsb: lower address of the descriptor. |
577 | * @value_msb: upper address of the descriptor. |
578 | * |
579 | * Since vdma driver is trying to write to a register offset which is not a |
580 | * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits |
581 | * instead of a single 64 bit register write. |
582 | */ |
583 | static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, |
584 | u32 value_lsb, u32 value_msb) |
585 | { |
586 | /* Write the lsb 32 bits*/ |
587 | writel(val: value_lsb, addr: chan->xdev->regs + chan->desc_offset + reg); |
588 | |
589 | /* Write the msb 32 bits */ |
590 | writel(val: value_msb, addr: chan->xdev->regs + chan->desc_offset + reg + 4); |
591 | } |
592 | |
593 | static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) |
594 | { |
595 | lo_hi_writeq(val: value, addr: chan->xdev->regs + chan->ctrl_offset + reg); |
596 | } |
597 | |
598 | static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, |
599 | dma_addr_t addr) |
600 | { |
601 | if (chan->ext_addr) |
602 | dma_writeq(chan, reg, value: addr); |
603 | else |
604 | dma_ctrl_write(chan, reg, value: addr); |
605 | } |
606 | |
607 | static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, |
608 | struct xilinx_axidma_desc_hw *hw, |
609 | dma_addr_t buf_addr, size_t sg_used, |
610 | size_t period_len) |
611 | { |
612 | if (chan->ext_addr) { |
613 | hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); |
614 | hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + |
615 | period_len); |
616 | } else { |
617 | hw->buf_addr = buf_addr + sg_used + period_len; |
618 | } |
619 | } |
620 | |
621 | static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, |
622 | struct xilinx_aximcdma_desc_hw *hw, |
623 | dma_addr_t buf_addr, size_t sg_used) |
624 | { |
625 | if (chan->ext_addr) { |
626 | hw->buf_addr = lower_32_bits(buf_addr + sg_used); |
627 | hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); |
628 | } else { |
629 | hw->buf_addr = buf_addr + sg_used; |
630 | } |
631 | } |
632 | |
633 | /** |
634 | * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length |
635 | * @tx: async transaction descriptor |
636 | * @payload_len: metadata payload length |
637 | * @max_len: metadata max length |
638 | * Return: The app field pointer. |
639 | */ |
640 | static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, |
641 | size_t *payload_len, size_t *max_len) |
642 | { |
643 | struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); |
644 | struct xilinx_axidma_tx_segment *seg; |
645 | |
646 | *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; |
647 | seg = list_first_entry(&desc->segments, |
648 | struct xilinx_axidma_tx_segment, node); |
649 | return seg->hw.app; |
650 | } |
651 | |
652 | static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { |
653 | .get_ptr = xilinx_dma_get_metadata_ptr, |
654 | }; |
655 | |
656 | /* ----------------------------------------------------------------------------- |
657 | * Descriptors and segments alloc and free |
658 | */ |
659 | |
660 | /** |
661 | * xilinx_vdma_alloc_tx_segment - Allocate transaction segment |
662 | * @chan: Driver specific DMA channel |
663 | * |
664 | * Return: The allocated segment on success and NULL on failure. |
665 | */ |
666 | static struct xilinx_vdma_tx_segment * |
667 | xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
668 | { |
669 | struct xilinx_vdma_tx_segment *segment; |
670 | dma_addr_t phys; |
671 | |
672 | segment = dma_pool_zalloc(pool: chan->desc_pool, GFP_ATOMIC, handle: &phys); |
673 | if (!segment) |
674 | return NULL; |
675 | |
676 | segment->phys = phys; |
677 | |
678 | return segment; |
679 | } |
680 | |
681 | /** |
682 | * xilinx_cdma_alloc_tx_segment - Allocate transaction segment |
683 | * @chan: Driver specific DMA channel |
684 | * |
685 | * Return: The allocated segment on success and NULL on failure. |
686 | */ |
687 | static struct xilinx_cdma_tx_segment * |
688 | xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
689 | { |
690 | struct xilinx_cdma_tx_segment *segment; |
691 | dma_addr_t phys; |
692 | |
693 | segment = dma_pool_zalloc(pool: chan->desc_pool, GFP_ATOMIC, handle: &phys); |
694 | if (!segment) |
695 | return NULL; |
696 | |
697 | segment->phys = phys; |
698 | |
699 | return segment; |
700 | } |
701 | |
702 | /** |
703 | * xilinx_axidma_alloc_tx_segment - Allocate transaction segment |
704 | * @chan: Driver specific DMA channel |
705 | * |
706 | * Return: The allocated segment on success and NULL on failure. |
707 | */ |
708 | static struct xilinx_axidma_tx_segment * |
709 | xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
710 | { |
711 | struct xilinx_axidma_tx_segment *segment = NULL; |
712 | unsigned long flags; |
713 | |
714 | spin_lock_irqsave(&chan->lock, flags); |
715 | if (!list_empty(head: &chan->free_seg_list)) { |
716 | segment = list_first_entry(&chan->free_seg_list, |
717 | struct xilinx_axidma_tx_segment, |
718 | node); |
719 | list_del(entry: &segment->node); |
720 | } |
721 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
722 | |
723 | if (!segment) |
724 | dev_dbg(chan->dev, "Could not find free tx segment\n" ); |
725 | |
726 | return segment; |
727 | } |
728 | |
729 | /** |
730 | * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment |
731 | * @chan: Driver specific DMA channel |
732 | * |
733 | * Return: The allocated segment on success and NULL on failure. |
734 | */ |
735 | static struct xilinx_aximcdma_tx_segment * |
736 | xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
737 | { |
738 | struct xilinx_aximcdma_tx_segment *segment = NULL; |
739 | unsigned long flags; |
740 | |
741 | spin_lock_irqsave(&chan->lock, flags); |
742 | if (!list_empty(head: &chan->free_seg_list)) { |
743 | segment = list_first_entry(&chan->free_seg_list, |
744 | struct xilinx_aximcdma_tx_segment, |
745 | node); |
746 | list_del(entry: &segment->node); |
747 | } |
748 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
749 | |
750 | return segment; |
751 | } |
752 | |
753 | static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) |
754 | { |
755 | u32 next_desc = hw->next_desc; |
756 | u32 next_desc_msb = hw->next_desc_msb; |
757 | |
758 | memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw)); |
759 | |
760 | hw->next_desc = next_desc; |
761 | hw->next_desc_msb = next_desc_msb; |
762 | } |
763 | |
764 | static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) |
765 | { |
766 | u32 next_desc = hw->next_desc; |
767 | u32 next_desc_msb = hw->next_desc_msb; |
768 | |
769 | memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); |
770 | |
771 | hw->next_desc = next_desc; |
772 | hw->next_desc_msb = next_desc_msb; |
773 | } |
774 | |
775 | /** |
776 | * xilinx_dma_free_tx_segment - Free transaction segment |
777 | * @chan: Driver specific DMA channel |
778 | * @segment: DMA transaction segment |
779 | */ |
780 | static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, |
781 | struct xilinx_axidma_tx_segment *segment) |
782 | { |
783 | xilinx_dma_clean_hw_desc(hw: &segment->hw); |
784 | |
785 | list_add_tail(new: &segment->node, head: &chan->free_seg_list); |
786 | } |
787 | |
788 | /** |
789 | * xilinx_mcdma_free_tx_segment - Free transaction segment |
790 | * @chan: Driver specific DMA channel |
791 | * @segment: DMA transaction segment |
792 | */ |
793 | static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, |
794 | struct xilinx_aximcdma_tx_segment * |
795 | segment) |
796 | { |
797 | xilinx_mcdma_clean_hw_desc(hw: &segment->hw); |
798 | |
799 | list_add_tail(new: &segment->node, head: &chan->free_seg_list); |
800 | } |
801 | |
802 | /** |
803 | * xilinx_cdma_free_tx_segment - Free transaction segment |
804 | * @chan: Driver specific DMA channel |
805 | * @segment: DMA transaction segment |
806 | */ |
807 | static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, |
808 | struct xilinx_cdma_tx_segment *segment) |
809 | { |
810 | dma_pool_free(pool: chan->desc_pool, vaddr: segment, addr: segment->phys); |
811 | } |
812 | |
813 | /** |
814 | * xilinx_vdma_free_tx_segment - Free transaction segment |
815 | * @chan: Driver specific DMA channel |
816 | * @segment: DMA transaction segment |
817 | */ |
818 | static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, |
819 | struct xilinx_vdma_tx_segment *segment) |
820 | { |
821 | dma_pool_free(pool: chan->desc_pool, vaddr: segment, addr: segment->phys); |
822 | } |
823 | |
824 | /** |
825 | * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor |
826 | * @chan: Driver specific DMA channel |
827 | * |
828 | * Return: The allocated descriptor on success and NULL on failure. |
829 | */ |
830 | static struct xilinx_dma_tx_descriptor * |
831 | xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) |
832 | { |
833 | struct xilinx_dma_tx_descriptor *desc; |
834 | |
835 | desc = kzalloc(size: sizeof(*desc), GFP_NOWAIT); |
836 | if (!desc) |
837 | return NULL; |
838 | |
839 | INIT_LIST_HEAD(list: &desc->segments); |
840 | |
841 | return desc; |
842 | } |
843 | |
844 | /** |
845 | * xilinx_dma_free_tx_descriptor - Free transaction descriptor |
846 | * @chan: Driver specific DMA channel |
847 | * @desc: DMA transaction descriptor |
848 | */ |
849 | static void |
850 | xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, |
851 | struct xilinx_dma_tx_descriptor *desc) |
852 | { |
853 | struct xilinx_vdma_tx_segment *segment, *next; |
854 | struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; |
855 | struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; |
856 | struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; |
857 | |
858 | if (!desc) |
859 | return; |
860 | |
861 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
862 | list_for_each_entry_safe(segment, next, &desc->segments, node) { |
863 | list_del(entry: &segment->node); |
864 | xilinx_vdma_free_tx_segment(chan, segment); |
865 | } |
866 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
867 | list_for_each_entry_safe(cdma_segment, cdma_next, |
868 | &desc->segments, node) { |
869 | list_del(entry: &cdma_segment->node); |
870 | xilinx_cdma_free_tx_segment(chan, segment: cdma_segment); |
871 | } |
872 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
873 | list_for_each_entry_safe(axidma_segment, axidma_next, |
874 | &desc->segments, node) { |
875 | list_del(entry: &axidma_segment->node); |
876 | xilinx_dma_free_tx_segment(chan, segment: axidma_segment); |
877 | } |
878 | } else { |
879 | list_for_each_entry_safe(aximcdma_segment, aximcdma_next, |
880 | &desc->segments, node) { |
881 | list_del(entry: &aximcdma_segment->node); |
882 | xilinx_mcdma_free_tx_segment(chan, segment: aximcdma_segment); |
883 | } |
884 | } |
885 | |
886 | kfree(objp: desc); |
887 | } |
888 | |
889 | /* Required functions */ |
890 | |
891 | /** |
892 | * xilinx_dma_free_desc_list - Free descriptors list |
893 | * @chan: Driver specific DMA channel |
894 | * @list: List to parse and delete the descriptor |
895 | */ |
896 | static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, |
897 | struct list_head *list) |
898 | { |
899 | struct xilinx_dma_tx_descriptor *desc, *next; |
900 | |
901 | list_for_each_entry_safe(desc, next, list, node) { |
902 | list_del(entry: &desc->node); |
903 | xilinx_dma_free_tx_descriptor(chan, desc); |
904 | } |
905 | } |
906 | |
907 | /** |
908 | * xilinx_dma_free_descriptors - Free channel descriptors |
909 | * @chan: Driver specific DMA channel |
910 | */ |
911 | static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) |
912 | { |
913 | unsigned long flags; |
914 | |
915 | spin_lock_irqsave(&chan->lock, flags); |
916 | |
917 | xilinx_dma_free_desc_list(chan, list: &chan->pending_list); |
918 | xilinx_dma_free_desc_list(chan, list: &chan->done_list); |
919 | xilinx_dma_free_desc_list(chan, list: &chan->active_list); |
920 | |
921 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
922 | } |
923 | |
924 | /** |
925 | * xilinx_dma_free_chan_resources - Free channel resources |
926 | * @dchan: DMA channel |
927 | */ |
928 | static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) |
929 | { |
930 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
931 | unsigned long flags; |
932 | |
933 | dev_dbg(chan->dev, "Free all channel resources.\n" ); |
934 | |
935 | xilinx_dma_free_descriptors(chan); |
936 | |
937 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
938 | spin_lock_irqsave(&chan->lock, flags); |
939 | INIT_LIST_HEAD(list: &chan->free_seg_list); |
940 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
941 | |
942 | /* Free memory that is allocated for BD */ |
943 | dma_free_coherent(dev: chan->dev, size: sizeof(*chan->seg_v) * |
944 | XILINX_DMA_NUM_DESCS, cpu_addr: chan->seg_v, |
945 | dma_handle: chan->seg_p); |
946 | |
947 | /* Free Memory that is allocated for cyclic DMA Mode */ |
948 | dma_free_coherent(dev: chan->dev, size: sizeof(*chan->cyclic_seg_v), |
949 | cpu_addr: chan->cyclic_seg_v, dma_handle: chan->cyclic_seg_p); |
950 | } |
951 | |
952 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { |
953 | spin_lock_irqsave(&chan->lock, flags); |
954 | INIT_LIST_HEAD(list: &chan->free_seg_list); |
955 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
956 | |
957 | /* Free memory that is allocated for BD */ |
958 | dma_free_coherent(dev: chan->dev, size: sizeof(*chan->seg_mv) * |
959 | XILINX_DMA_NUM_DESCS, cpu_addr: chan->seg_mv, |
960 | dma_handle: chan->seg_p); |
961 | } |
962 | |
963 | if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && |
964 | chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { |
965 | dma_pool_destroy(pool: chan->desc_pool); |
966 | chan->desc_pool = NULL; |
967 | } |
968 | |
969 | } |
970 | |
971 | /** |
972 | * xilinx_dma_get_residue - Compute residue for a given descriptor |
973 | * @chan: Driver specific dma channel |
974 | * @desc: dma transaction descriptor |
975 | * |
976 | * Return: The number of residue bytes for the descriptor. |
977 | */ |
978 | static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, |
979 | struct xilinx_dma_tx_descriptor *desc) |
980 | { |
981 | struct xilinx_cdma_tx_segment *cdma_seg; |
982 | struct xilinx_axidma_tx_segment *axidma_seg; |
983 | struct xilinx_aximcdma_tx_segment *aximcdma_seg; |
984 | struct xilinx_cdma_desc_hw *cdma_hw; |
985 | struct xilinx_axidma_desc_hw *axidma_hw; |
986 | struct xilinx_aximcdma_desc_hw *aximcdma_hw; |
987 | struct list_head *entry; |
988 | u32 residue = 0; |
989 | |
990 | list_for_each(entry, &desc->segments) { |
991 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
992 | cdma_seg = list_entry(entry, |
993 | struct xilinx_cdma_tx_segment, |
994 | node); |
995 | cdma_hw = &cdma_seg->hw; |
996 | residue += (cdma_hw->control - cdma_hw->status) & |
997 | chan->xdev->max_buffer_len; |
998 | } else if (chan->xdev->dma_config->dmatype == |
999 | XDMA_TYPE_AXIDMA) { |
1000 | axidma_seg = list_entry(entry, |
1001 | struct xilinx_axidma_tx_segment, |
1002 | node); |
1003 | axidma_hw = &axidma_seg->hw; |
1004 | residue += (axidma_hw->control - axidma_hw->status) & |
1005 | chan->xdev->max_buffer_len; |
1006 | } else { |
1007 | aximcdma_seg = |
1008 | list_entry(entry, |
1009 | struct xilinx_aximcdma_tx_segment, |
1010 | node); |
1011 | aximcdma_hw = &aximcdma_seg->hw; |
1012 | residue += |
1013 | (aximcdma_hw->control - aximcdma_hw->status) & |
1014 | chan->xdev->max_buffer_len; |
1015 | } |
1016 | } |
1017 | |
1018 | return residue; |
1019 | } |
1020 | |
1021 | /** |
1022 | * xilinx_dma_chan_handle_cyclic - Cyclic dma callback |
1023 | * @chan: Driver specific dma channel |
1024 | * @desc: dma transaction descriptor |
1025 | * @flags: flags for spin lock |
1026 | */ |
1027 | static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, |
1028 | struct xilinx_dma_tx_descriptor *desc, |
1029 | unsigned long *flags) |
1030 | { |
1031 | struct dmaengine_desc_callback cb; |
1032 | |
1033 | dmaengine_desc_get_callback(tx: &desc->async_tx, cb: &cb); |
1034 | if (dmaengine_desc_callback_valid(cb: &cb)) { |
1035 | spin_unlock_irqrestore(lock: &chan->lock, flags: *flags); |
1036 | dmaengine_desc_callback_invoke(cb: &cb, NULL); |
1037 | spin_lock_irqsave(&chan->lock, *flags); |
1038 | } |
1039 | } |
1040 | |
1041 | /** |
1042 | * xilinx_dma_chan_desc_cleanup - Clean channel descriptors |
1043 | * @chan: Driver specific DMA channel |
1044 | */ |
1045 | static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) |
1046 | { |
1047 | struct xilinx_dma_tx_descriptor *desc, *next; |
1048 | unsigned long flags; |
1049 | |
1050 | spin_lock_irqsave(&chan->lock, flags); |
1051 | |
1052 | list_for_each_entry_safe(desc, next, &chan->done_list, node) { |
1053 | struct dmaengine_result result; |
1054 | |
1055 | if (desc->cyclic) { |
1056 | xilinx_dma_chan_handle_cyclic(chan, desc, flags: &flags); |
1057 | break; |
1058 | } |
1059 | |
1060 | /* Remove from the list of running transactions */ |
1061 | list_del(entry: &desc->node); |
1062 | |
1063 | if (unlikely(desc->err)) { |
1064 | if (chan->direction == DMA_DEV_TO_MEM) |
1065 | result.result = DMA_TRANS_READ_FAILED; |
1066 | else |
1067 | result.result = DMA_TRANS_WRITE_FAILED; |
1068 | } else { |
1069 | result.result = DMA_TRANS_NOERROR; |
1070 | } |
1071 | |
1072 | result.residue = desc->residue; |
1073 | |
1074 | /* Run the link descriptor callback function */ |
1075 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
1076 | dmaengine_desc_get_callback_invoke(tx: &desc->async_tx, result: &result); |
1077 | spin_lock_irqsave(&chan->lock, flags); |
1078 | |
1079 | /* Run any dependencies, then free the descriptor */ |
1080 | dma_run_dependencies(tx: &desc->async_tx); |
1081 | xilinx_dma_free_tx_descriptor(chan, desc); |
1082 | |
1083 | /* |
1084 | * While we ran a callback the user called a terminate function, |
1085 | * which takes care of cleaning up any remaining descriptors |
1086 | */ |
1087 | if (chan->terminating) |
1088 | break; |
1089 | } |
1090 | |
1091 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
1092 | } |
1093 | |
1094 | /** |
1095 | * xilinx_dma_do_tasklet - Schedule completion tasklet |
1096 | * @t: Pointer to the Xilinx DMA channel structure |
1097 | */ |
1098 | static void xilinx_dma_do_tasklet(struct tasklet_struct *t) |
1099 | { |
1100 | struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); |
1101 | |
1102 | xilinx_dma_chan_desc_cleanup(chan); |
1103 | } |
1104 | |
1105 | /** |
1106 | * xilinx_dma_alloc_chan_resources - Allocate channel resources |
1107 | * @dchan: DMA channel |
1108 | * |
1109 | * Return: '0' on success and failure value on error |
1110 | */ |
1111 | static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) |
1112 | { |
1113 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
1114 | int i; |
1115 | |
1116 | /* Has this channel already been allocated? */ |
1117 | if (chan->desc_pool) |
1118 | return 0; |
1119 | |
1120 | /* |
1121 | * We need the descriptor to be aligned to 64bytes |
1122 | * for meeting Xilinx VDMA specification requirement. |
1123 | */ |
1124 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
1125 | /* Allocate the buffer descriptors. */ |
1126 | chan->seg_v = dma_alloc_coherent(dev: chan->dev, |
1127 | size: sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, |
1128 | dma_handle: &chan->seg_p, GFP_KERNEL); |
1129 | if (!chan->seg_v) { |
1130 | dev_err(chan->dev, |
1131 | "unable to allocate channel %d descriptors\n" , |
1132 | chan->id); |
1133 | return -ENOMEM; |
1134 | } |
1135 | /* |
1136 | * For cyclic DMA mode we need to program the tail Descriptor |
1137 | * register with a value which is not a part of the BD chain |
1138 | * so allocating a desc segment during channel allocation for |
1139 | * programming tail descriptor. |
1140 | */ |
1141 | chan->cyclic_seg_v = dma_alloc_coherent(dev: chan->dev, |
1142 | size: sizeof(*chan->cyclic_seg_v), |
1143 | dma_handle: &chan->cyclic_seg_p, |
1144 | GFP_KERNEL); |
1145 | if (!chan->cyclic_seg_v) { |
1146 | dev_err(chan->dev, |
1147 | "unable to allocate desc segment for cyclic DMA\n" ); |
1148 | dma_free_coherent(dev: chan->dev, size: sizeof(*chan->seg_v) * |
1149 | XILINX_DMA_NUM_DESCS, cpu_addr: chan->seg_v, |
1150 | dma_handle: chan->seg_p); |
1151 | return -ENOMEM; |
1152 | } |
1153 | chan->cyclic_seg_v->phys = chan->cyclic_seg_p; |
1154 | |
1155 | for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { |
1156 | chan->seg_v[i].hw.next_desc = |
1157 | lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * |
1158 | ((i + 1) % XILINX_DMA_NUM_DESCS)); |
1159 | chan->seg_v[i].hw.next_desc_msb = |
1160 | upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * |
1161 | ((i + 1) % XILINX_DMA_NUM_DESCS)); |
1162 | chan->seg_v[i].phys = chan->seg_p + |
1163 | sizeof(*chan->seg_v) * i; |
1164 | list_add_tail(new: &chan->seg_v[i].node, |
1165 | head: &chan->free_seg_list); |
1166 | } |
1167 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { |
1168 | /* Allocate the buffer descriptors. */ |
1169 | chan->seg_mv = dma_alloc_coherent(dev: chan->dev, |
1170 | size: sizeof(*chan->seg_mv) * |
1171 | XILINX_DMA_NUM_DESCS, |
1172 | dma_handle: &chan->seg_p, GFP_KERNEL); |
1173 | if (!chan->seg_mv) { |
1174 | dev_err(chan->dev, |
1175 | "unable to allocate channel %d descriptors\n" , |
1176 | chan->id); |
1177 | return -ENOMEM; |
1178 | } |
1179 | for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { |
1180 | chan->seg_mv[i].hw.next_desc = |
1181 | lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * |
1182 | ((i + 1) % XILINX_DMA_NUM_DESCS)); |
1183 | chan->seg_mv[i].hw.next_desc_msb = |
1184 | upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * |
1185 | ((i + 1) % XILINX_DMA_NUM_DESCS)); |
1186 | chan->seg_mv[i].phys = chan->seg_p + |
1187 | sizeof(*chan->seg_mv) * i; |
1188 | list_add_tail(new: &chan->seg_mv[i].node, |
1189 | head: &chan->free_seg_list); |
1190 | } |
1191 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
1192 | chan->desc_pool = dma_pool_create(name: "xilinx_cdma_desc_pool" , |
1193 | dev: chan->dev, |
1194 | size: sizeof(struct xilinx_cdma_tx_segment), |
1195 | align: __alignof__(struct xilinx_cdma_tx_segment), |
1196 | allocation: 0); |
1197 | } else { |
1198 | chan->desc_pool = dma_pool_create(name: "xilinx_vdma_desc_pool" , |
1199 | dev: chan->dev, |
1200 | size: sizeof(struct xilinx_vdma_tx_segment), |
1201 | align: __alignof__(struct xilinx_vdma_tx_segment), |
1202 | allocation: 0); |
1203 | } |
1204 | |
1205 | if (!chan->desc_pool && |
1206 | ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && |
1207 | chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { |
1208 | dev_err(chan->dev, |
1209 | "unable to allocate channel %d descriptor pool\n" , |
1210 | chan->id); |
1211 | return -ENOMEM; |
1212 | } |
1213 | |
1214 | dma_cookie_init(chan: dchan); |
1215 | |
1216 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
1217 | /* For AXI DMA resetting once channel will reset the |
1218 | * other channel as well so enable the interrupts here. |
1219 | */ |
1220 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
1221 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
1222 | } |
1223 | |
1224 | if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) |
1225 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
1226 | XILINX_CDMA_CR_SGMODE); |
1227 | |
1228 | return 0; |
1229 | } |
1230 | |
1231 | /** |
1232 | * xilinx_dma_calc_copysize - Calculate the amount of data to copy |
1233 | * @chan: Driver specific DMA channel |
1234 | * @size: Total data that needs to be copied |
1235 | * @done: Amount of data that has been already copied |
1236 | * |
1237 | * Return: Amount of data that has to be copied |
1238 | */ |
1239 | static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, |
1240 | int size, int done) |
1241 | { |
1242 | size_t copy; |
1243 | |
1244 | copy = min_t(size_t, size - done, |
1245 | chan->xdev->max_buffer_len); |
1246 | |
1247 | if ((copy + done < size) && |
1248 | chan->xdev->common.copy_align) { |
1249 | /* |
1250 | * If this is not the last descriptor, make sure |
1251 | * the next one will be properly aligned |
1252 | */ |
1253 | copy = rounddown(copy, |
1254 | (1 << chan->xdev->common.copy_align)); |
1255 | } |
1256 | return copy; |
1257 | } |
1258 | |
1259 | /** |
1260 | * xilinx_dma_tx_status - Get DMA transaction status |
1261 | * @dchan: DMA channel |
1262 | * @cookie: Transaction identifier |
1263 | * @txstate: Transaction state |
1264 | * |
1265 | * Return: DMA transaction status |
1266 | */ |
1267 | static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, |
1268 | dma_cookie_t cookie, |
1269 | struct dma_tx_state *txstate) |
1270 | { |
1271 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
1272 | struct xilinx_dma_tx_descriptor *desc; |
1273 | enum dma_status ret; |
1274 | unsigned long flags; |
1275 | u32 residue = 0; |
1276 | |
1277 | ret = dma_cookie_status(chan: dchan, cookie, state: txstate); |
1278 | if (ret == DMA_COMPLETE || !txstate) |
1279 | return ret; |
1280 | |
1281 | spin_lock_irqsave(&chan->lock, flags); |
1282 | if (!list_empty(head: &chan->active_list)) { |
1283 | desc = list_last_entry(&chan->active_list, |
1284 | struct xilinx_dma_tx_descriptor, node); |
1285 | /* |
1286 | * VDMA and simple mode do not support residue reporting, so the |
1287 | * residue field will always be 0. |
1288 | */ |
1289 | if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) |
1290 | residue = xilinx_dma_get_residue(chan, desc); |
1291 | } |
1292 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
1293 | |
1294 | dma_set_residue(state: txstate, residue); |
1295 | |
1296 | return ret; |
1297 | } |
1298 | |
1299 | /** |
1300 | * xilinx_dma_stop_transfer - Halt DMA channel |
1301 | * @chan: Driver specific DMA channel |
1302 | * |
1303 | * Return: '0' on success and failure value on error |
1304 | */ |
1305 | static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) |
1306 | { |
1307 | u32 val; |
1308 | |
1309 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
1310 | |
1311 | /* Wait for the hardware to halt */ |
1312 | return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
1313 | val & XILINX_DMA_DMASR_HALTED, 0, |
1314 | XILINX_DMA_LOOP_COUNT); |
1315 | } |
1316 | |
1317 | /** |
1318 | * xilinx_cdma_stop_transfer - Wait for the current transfer to complete |
1319 | * @chan: Driver specific DMA channel |
1320 | * |
1321 | * Return: '0' on success and failure value on error |
1322 | */ |
1323 | static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) |
1324 | { |
1325 | u32 val; |
1326 | |
1327 | return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
1328 | val & XILINX_DMA_DMASR_IDLE, 0, |
1329 | XILINX_DMA_LOOP_COUNT); |
1330 | } |
1331 | |
1332 | /** |
1333 | * xilinx_dma_start - Start DMA channel |
1334 | * @chan: Driver specific DMA channel |
1335 | */ |
1336 | static void xilinx_dma_start(struct xilinx_dma_chan *chan) |
1337 | { |
1338 | int err; |
1339 | u32 val; |
1340 | |
1341 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
1342 | |
1343 | /* Wait for the hardware to start */ |
1344 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
1345 | !(val & XILINX_DMA_DMASR_HALTED), 0, |
1346 | XILINX_DMA_LOOP_COUNT); |
1347 | |
1348 | if (err) { |
1349 | dev_err(chan->dev, "Cannot start channel %p: %x\n" , |
1350 | chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
1351 | |
1352 | chan->err = true; |
1353 | } |
1354 | } |
1355 | |
1356 | /** |
1357 | * xilinx_vdma_start_transfer - Starts VDMA transfer |
1358 | * @chan: Driver specific channel struct pointer |
1359 | */ |
1360 | static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) |
1361 | { |
1362 | struct xilinx_vdma_config *config = &chan->config; |
1363 | struct xilinx_dma_tx_descriptor *desc; |
1364 | u32 reg, j; |
1365 | struct xilinx_vdma_tx_segment *segment, *last = NULL; |
1366 | int i = 0; |
1367 | |
1368 | /* This function was invoked with lock held */ |
1369 | if (chan->err) |
1370 | return; |
1371 | |
1372 | if (!chan->idle) |
1373 | return; |
1374 | |
1375 | if (list_empty(head: &chan->pending_list)) |
1376 | return; |
1377 | |
1378 | desc = list_first_entry(&chan->pending_list, |
1379 | struct xilinx_dma_tx_descriptor, node); |
1380 | |
1381 | /* Configure the hardware using info in the config structure */ |
1382 | if (chan->has_vflip) { |
1383 | reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); |
1384 | reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; |
1385 | reg |= config->vflip_en; |
1386 | dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, |
1387 | value: reg); |
1388 | } |
1389 | |
1390 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
1391 | |
1392 | if (config->frm_cnt_en) |
1393 | reg |= XILINX_DMA_DMACR_FRAMECNT_EN; |
1394 | else |
1395 | reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; |
1396 | |
1397 | /* If not parking, enable circular mode */ |
1398 | if (config->park) |
1399 | reg &= ~XILINX_DMA_DMACR_CIRC_EN; |
1400 | else |
1401 | reg |= XILINX_DMA_DMACR_CIRC_EN; |
1402 | |
1403 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: reg); |
1404 | |
1405 | j = chan->desc_submitcount; |
1406 | reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); |
1407 | if (chan->direction == DMA_MEM_TO_DEV) { |
1408 | reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; |
1409 | reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; |
1410 | } else { |
1411 | reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; |
1412 | reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; |
1413 | } |
1414 | dma_write(chan, XILINX_DMA_REG_PARK_PTR, value: reg); |
1415 | |
1416 | /* Start the hardware */ |
1417 | xilinx_dma_start(chan); |
1418 | |
1419 | if (chan->err) |
1420 | return; |
1421 | |
1422 | /* Start the transfer */ |
1423 | if (chan->desc_submitcount < chan->num_frms) |
1424 | i = chan->desc_submitcount; |
1425 | |
1426 | list_for_each_entry(segment, &desc->segments, node) { |
1427 | if (chan->ext_addr) |
1428 | vdma_desc_write_64(chan, |
1429 | XILINX_VDMA_REG_START_ADDRESS_64(i++), |
1430 | value_lsb: segment->hw.buf_addr, |
1431 | value_msb: segment->hw.buf_addr_msb); |
1432 | else |
1433 | vdma_desc_write(chan, |
1434 | XILINX_VDMA_REG_START_ADDRESS(i++), |
1435 | value: segment->hw.buf_addr); |
1436 | |
1437 | last = segment; |
1438 | } |
1439 | |
1440 | if (!last) |
1441 | return; |
1442 | |
1443 | /* HW expects these parameters to be same for one transaction */ |
1444 | vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, value: last->hw.hsize); |
1445 | vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, |
1446 | value: last->hw.stride); |
1447 | vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, value: last->hw.vsize); |
1448 | |
1449 | chan->desc_submitcount++; |
1450 | chan->desc_pendingcount--; |
1451 | list_move_tail(list: &desc->node, head: &chan->active_list); |
1452 | if (chan->desc_submitcount == chan->num_frms) |
1453 | chan->desc_submitcount = 0; |
1454 | |
1455 | chan->idle = false; |
1456 | } |
1457 | |
1458 | /** |
1459 | * xilinx_cdma_start_transfer - Starts cdma transfer |
1460 | * @chan: Driver specific channel struct pointer |
1461 | */ |
1462 | static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) |
1463 | { |
1464 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
1465 | struct xilinx_cdma_tx_segment *tail_segment; |
1466 | u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); |
1467 | |
1468 | if (chan->err) |
1469 | return; |
1470 | |
1471 | if (!chan->idle) |
1472 | return; |
1473 | |
1474 | if (list_empty(head: &chan->pending_list)) |
1475 | return; |
1476 | |
1477 | head_desc = list_first_entry(&chan->pending_list, |
1478 | struct xilinx_dma_tx_descriptor, node); |
1479 | tail_desc = list_last_entry(&chan->pending_list, |
1480 | struct xilinx_dma_tx_descriptor, node); |
1481 | tail_segment = list_last_entry(&tail_desc->segments, |
1482 | struct xilinx_cdma_tx_segment, node); |
1483 | |
1484 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
1485 | ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
1486 | ctrl_reg |= chan->desc_pendingcount << |
1487 | XILINX_DMA_CR_COALESCE_SHIFT; |
1488 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: ctrl_reg); |
1489 | } |
1490 | |
1491 | if (chan->has_sg) { |
1492 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, |
1493 | XILINX_CDMA_CR_SGMODE); |
1494 | |
1495 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
1496 | XILINX_CDMA_CR_SGMODE); |
1497 | |
1498 | xilinx_write(chan, XILINX_DMA_REG_CURDESC, |
1499 | addr: head_desc->async_tx.phys); |
1500 | |
1501 | /* Update tail ptr register which will start the transfer */ |
1502 | xilinx_write(chan, XILINX_DMA_REG_TAILDESC, |
1503 | addr: tail_segment->phys); |
1504 | } else { |
1505 | /* In simple mode */ |
1506 | struct xilinx_cdma_tx_segment *segment; |
1507 | struct xilinx_cdma_desc_hw *hw; |
1508 | |
1509 | segment = list_first_entry(&head_desc->segments, |
1510 | struct xilinx_cdma_tx_segment, |
1511 | node); |
1512 | |
1513 | hw = &segment->hw; |
1514 | |
1515 | xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, |
1516 | xilinx_prep_dma_addr_t(hw->src_addr)); |
1517 | xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, |
1518 | xilinx_prep_dma_addr_t(hw->dest_addr)); |
1519 | |
1520 | /* Start the transfer */ |
1521 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
1522 | value: hw->control & chan->xdev->max_buffer_len); |
1523 | } |
1524 | |
1525 | list_splice_tail_init(list: &chan->pending_list, head: &chan->active_list); |
1526 | chan->desc_pendingcount = 0; |
1527 | chan->idle = false; |
1528 | } |
1529 | |
1530 | /** |
1531 | * xilinx_dma_start_transfer - Starts DMA transfer |
1532 | * @chan: Driver specific channel struct pointer |
1533 | */ |
1534 | static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) |
1535 | { |
1536 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
1537 | struct xilinx_axidma_tx_segment *tail_segment; |
1538 | u32 reg; |
1539 | |
1540 | if (chan->err) |
1541 | return; |
1542 | |
1543 | if (list_empty(head: &chan->pending_list)) |
1544 | return; |
1545 | |
1546 | if (!chan->idle) |
1547 | return; |
1548 | |
1549 | head_desc = list_first_entry(&chan->pending_list, |
1550 | struct xilinx_dma_tx_descriptor, node); |
1551 | tail_desc = list_last_entry(&chan->pending_list, |
1552 | struct xilinx_dma_tx_descriptor, node); |
1553 | tail_segment = list_last_entry(&tail_desc->segments, |
1554 | struct xilinx_axidma_tx_segment, node); |
1555 | |
1556 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
1557 | |
1558 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
1559 | reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
1560 | reg |= chan->desc_pendingcount << |
1561 | XILINX_DMA_CR_COALESCE_SHIFT; |
1562 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: reg); |
1563 | } |
1564 | |
1565 | if (chan->has_sg) |
1566 | xilinx_write(chan, XILINX_DMA_REG_CURDESC, |
1567 | addr: head_desc->async_tx.phys); |
1568 | reg &= ~XILINX_DMA_CR_DELAY_MAX; |
1569 | reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; |
1570 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: reg); |
1571 | |
1572 | xilinx_dma_start(chan); |
1573 | |
1574 | if (chan->err) |
1575 | return; |
1576 | |
1577 | /* Start the transfer */ |
1578 | if (chan->has_sg) { |
1579 | if (chan->cyclic) |
1580 | xilinx_write(chan, XILINX_DMA_REG_TAILDESC, |
1581 | addr: chan->cyclic_seg_v->phys); |
1582 | else |
1583 | xilinx_write(chan, XILINX_DMA_REG_TAILDESC, |
1584 | addr: tail_segment->phys); |
1585 | } else { |
1586 | struct xilinx_axidma_tx_segment *segment; |
1587 | struct xilinx_axidma_desc_hw *hw; |
1588 | |
1589 | segment = list_first_entry(&head_desc->segments, |
1590 | struct xilinx_axidma_tx_segment, |
1591 | node); |
1592 | hw = &segment->hw; |
1593 | |
1594 | xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, |
1595 | xilinx_prep_dma_addr_t(hw->buf_addr)); |
1596 | |
1597 | /* Start the transfer */ |
1598 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
1599 | value: hw->control & chan->xdev->max_buffer_len); |
1600 | } |
1601 | |
1602 | list_splice_tail_init(list: &chan->pending_list, head: &chan->active_list); |
1603 | chan->desc_pendingcount = 0; |
1604 | chan->idle = false; |
1605 | } |
1606 | |
1607 | /** |
1608 | * xilinx_mcdma_start_transfer - Starts MCDMA transfer |
1609 | * @chan: Driver specific channel struct pointer |
1610 | */ |
1611 | static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) |
1612 | { |
1613 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
1614 | struct xilinx_aximcdma_tx_segment *tail_segment; |
1615 | u32 reg; |
1616 | |
1617 | /* |
1618 | * lock has been held by calling functions, so we don't need it |
1619 | * to take it here again. |
1620 | */ |
1621 | |
1622 | if (chan->err) |
1623 | return; |
1624 | |
1625 | if (!chan->idle) |
1626 | return; |
1627 | |
1628 | if (list_empty(head: &chan->pending_list)) |
1629 | return; |
1630 | |
1631 | head_desc = list_first_entry(&chan->pending_list, |
1632 | struct xilinx_dma_tx_descriptor, node); |
1633 | tail_desc = list_last_entry(&chan->pending_list, |
1634 | struct xilinx_dma_tx_descriptor, node); |
1635 | tail_segment = list_last_entry(&tail_desc->segments, |
1636 | struct xilinx_aximcdma_tx_segment, node); |
1637 | |
1638 | reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); |
1639 | |
1640 | if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { |
1641 | reg &= ~XILINX_MCDMA_COALESCE_MASK; |
1642 | reg |= chan->desc_pendingcount << |
1643 | XILINX_MCDMA_COALESCE_SHIFT; |
1644 | } |
1645 | |
1646 | reg |= XILINX_MCDMA_IRQ_ALL_MASK; |
1647 | dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), value: reg); |
1648 | |
1649 | /* Program current descriptor */ |
1650 | xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), |
1651 | addr: head_desc->async_tx.phys); |
1652 | |
1653 | /* Program channel enable register */ |
1654 | reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); |
1655 | reg |= BIT(chan->tdest); |
1656 | dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, value: reg); |
1657 | |
1658 | /* Start the fetch of BDs for the channel */ |
1659 | reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); |
1660 | reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; |
1661 | dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), value: reg); |
1662 | |
1663 | xilinx_dma_start(chan); |
1664 | |
1665 | if (chan->err) |
1666 | return; |
1667 | |
1668 | /* Start the transfer */ |
1669 | xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), |
1670 | addr: tail_segment->phys); |
1671 | |
1672 | list_splice_tail_init(list: &chan->pending_list, head: &chan->active_list); |
1673 | chan->desc_pendingcount = 0; |
1674 | chan->idle = false; |
1675 | } |
1676 | |
1677 | /** |
1678 | * xilinx_dma_issue_pending - Issue pending transactions |
1679 | * @dchan: DMA channel |
1680 | */ |
1681 | static void xilinx_dma_issue_pending(struct dma_chan *dchan) |
1682 | { |
1683 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
1684 | unsigned long flags; |
1685 | |
1686 | spin_lock_irqsave(&chan->lock, flags); |
1687 | chan->start_transfer(chan); |
1688 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
1689 | } |
1690 | |
1691 | /** |
1692 | * xilinx_dma_device_config - Configure the DMA channel |
1693 | * @dchan: DMA channel |
1694 | * @config: channel configuration |
1695 | * |
1696 | * Return: 0 always. |
1697 | */ |
1698 | static int xilinx_dma_device_config(struct dma_chan *dchan, |
1699 | struct dma_slave_config *config) |
1700 | { |
1701 | return 0; |
1702 | } |
1703 | |
1704 | /** |
1705 | * xilinx_dma_complete_descriptor - Mark the active descriptor as complete |
1706 | * @chan : xilinx DMA channel |
1707 | * |
1708 | * CONTEXT: hardirq |
1709 | */ |
1710 | static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) |
1711 | { |
1712 | struct xilinx_dma_tx_descriptor *desc, *next; |
1713 | |
1714 | /* This function was invoked with lock held */ |
1715 | if (list_empty(head: &chan->active_list)) |
1716 | return; |
1717 | |
1718 | list_for_each_entry_safe(desc, next, &chan->active_list, node) { |
1719 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
1720 | struct xilinx_axidma_tx_segment *seg; |
1721 | |
1722 | seg = list_last_entry(&desc->segments, |
1723 | struct xilinx_axidma_tx_segment, node); |
1724 | if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) |
1725 | break; |
1726 | } |
1727 | if (chan->has_sg && chan->xdev->dma_config->dmatype != |
1728 | XDMA_TYPE_VDMA) |
1729 | desc->residue = xilinx_dma_get_residue(chan, desc); |
1730 | else |
1731 | desc->residue = 0; |
1732 | desc->err = chan->err; |
1733 | |
1734 | list_del(entry: &desc->node); |
1735 | if (!desc->cyclic) |
1736 | dma_cookie_complete(tx: &desc->async_tx); |
1737 | list_add_tail(new: &desc->node, head: &chan->done_list); |
1738 | } |
1739 | } |
1740 | |
1741 | /** |
1742 | * xilinx_dma_reset - Reset DMA channel |
1743 | * @chan: Driver specific DMA channel |
1744 | * |
1745 | * Return: '0' on success and failure value on error |
1746 | */ |
1747 | static int xilinx_dma_reset(struct xilinx_dma_chan *chan) |
1748 | { |
1749 | int err; |
1750 | u32 tmp; |
1751 | |
1752 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); |
1753 | |
1754 | /* Wait for the hardware to finish reset */ |
1755 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, |
1756 | !(tmp & XILINX_DMA_DMACR_RESET), 0, |
1757 | XILINX_DMA_LOOP_COUNT); |
1758 | |
1759 | if (err) { |
1760 | dev_err(chan->dev, "reset timeout, cr %x, sr %x\n" , |
1761 | dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), |
1762 | dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
1763 | return -ETIMEDOUT; |
1764 | } |
1765 | |
1766 | chan->err = false; |
1767 | chan->idle = true; |
1768 | chan->desc_pendingcount = 0; |
1769 | chan->desc_submitcount = 0; |
1770 | |
1771 | return err; |
1772 | } |
1773 | |
1774 | /** |
1775 | * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts |
1776 | * @chan: Driver specific DMA channel |
1777 | * |
1778 | * Return: '0' on success and failure value on error |
1779 | */ |
1780 | static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) |
1781 | { |
1782 | int err; |
1783 | |
1784 | /* Reset VDMA */ |
1785 | err = xilinx_dma_reset(chan); |
1786 | if (err) |
1787 | return err; |
1788 | |
1789 | /* Enable interrupts */ |
1790 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
1791 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
1792 | |
1793 | return 0; |
1794 | } |
1795 | |
1796 | /** |
1797 | * xilinx_mcdma_irq_handler - MCDMA Interrupt handler |
1798 | * @irq: IRQ number |
1799 | * @data: Pointer to the Xilinx MCDMA channel structure |
1800 | * |
1801 | * Return: IRQ_HANDLED/IRQ_NONE |
1802 | */ |
1803 | static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) |
1804 | { |
1805 | struct xilinx_dma_chan *chan = data; |
1806 | u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; |
1807 | |
1808 | if (chan->direction == DMA_DEV_TO_MEM) |
1809 | ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; |
1810 | else |
1811 | ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; |
1812 | |
1813 | /* Read the channel id raising the interrupt*/ |
1814 | chan_sermask = dma_ctrl_read(chan, reg: ser_offset); |
1815 | chan_id = ffs(chan_sermask); |
1816 | |
1817 | if (!chan_id) |
1818 | return IRQ_NONE; |
1819 | |
1820 | if (chan->direction == DMA_DEV_TO_MEM) |
1821 | chan_offset = chan->xdev->dma_config->max_channels / 2; |
1822 | |
1823 | chan_offset = chan_offset + (chan_id - 1); |
1824 | chan = chan->xdev->chan[chan_offset]; |
1825 | /* Read the status and ack the interrupts. */ |
1826 | status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); |
1827 | if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) |
1828 | return IRQ_NONE; |
1829 | |
1830 | dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), |
1831 | value: status & XILINX_MCDMA_IRQ_ALL_MASK); |
1832 | |
1833 | if (status & XILINX_MCDMA_IRQ_ERR_MASK) { |
1834 | dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n" , |
1835 | chan, |
1836 | dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), |
1837 | dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET |
1838 | (chan->tdest)), |
1839 | dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET |
1840 | (chan->tdest))); |
1841 | chan->err = true; |
1842 | } |
1843 | |
1844 | if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { |
1845 | /* |
1846 | * Device takes too long to do the transfer when user requires |
1847 | * responsiveness. |
1848 | */ |
1849 | dev_dbg(chan->dev, "Inter-packet latency too long\n" ); |
1850 | } |
1851 | |
1852 | if (status & XILINX_MCDMA_IRQ_IOC_MASK) { |
1853 | spin_lock(lock: &chan->lock); |
1854 | xilinx_dma_complete_descriptor(chan); |
1855 | chan->idle = true; |
1856 | chan->start_transfer(chan); |
1857 | spin_unlock(lock: &chan->lock); |
1858 | } |
1859 | |
1860 | tasklet_hi_schedule(t: &chan->tasklet); |
1861 | return IRQ_HANDLED; |
1862 | } |
1863 | |
1864 | /** |
1865 | * xilinx_dma_irq_handler - DMA Interrupt handler |
1866 | * @irq: IRQ number |
1867 | * @data: Pointer to the Xilinx DMA channel structure |
1868 | * |
1869 | * Return: IRQ_HANDLED/IRQ_NONE |
1870 | */ |
1871 | static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) |
1872 | { |
1873 | struct xilinx_dma_chan *chan = data; |
1874 | u32 status; |
1875 | |
1876 | /* Read the status and ack the interrupts. */ |
1877 | status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); |
1878 | if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) |
1879 | return IRQ_NONE; |
1880 | |
1881 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
1882 | value: status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
1883 | |
1884 | if (status & XILINX_DMA_DMASR_ERR_IRQ) { |
1885 | /* |
1886 | * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the |
1887 | * error is recoverable, ignore it. Otherwise flag the error. |
1888 | * |
1889 | * Only recoverable errors can be cleared in the DMASR register, |
1890 | * make sure not to write to other error bits to 1. |
1891 | */ |
1892 | u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; |
1893 | |
1894 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
1895 | value: errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); |
1896 | |
1897 | if (!chan->flush_on_fsync || |
1898 | (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { |
1899 | dev_err(chan->dev, |
1900 | "Channel %p has errors %x, cdr %x tdr %x\n" , |
1901 | chan, errors, |
1902 | dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), |
1903 | dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); |
1904 | chan->err = true; |
1905 | } |
1906 | } |
1907 | |
1908 | if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | |
1909 | XILINX_DMA_DMASR_DLY_CNT_IRQ)) { |
1910 | spin_lock(lock: &chan->lock); |
1911 | xilinx_dma_complete_descriptor(chan); |
1912 | chan->idle = true; |
1913 | chan->start_transfer(chan); |
1914 | spin_unlock(lock: &chan->lock); |
1915 | } |
1916 | |
1917 | tasklet_schedule(t: &chan->tasklet); |
1918 | return IRQ_HANDLED; |
1919 | } |
1920 | |
1921 | /** |
1922 | * append_desc_queue - Queuing descriptor |
1923 | * @chan: Driver specific dma channel |
1924 | * @desc: dma transaction descriptor |
1925 | */ |
1926 | static void append_desc_queue(struct xilinx_dma_chan *chan, |
1927 | struct xilinx_dma_tx_descriptor *desc) |
1928 | { |
1929 | struct xilinx_vdma_tx_segment *tail_segment; |
1930 | struct xilinx_dma_tx_descriptor *tail_desc; |
1931 | struct xilinx_axidma_tx_segment *axidma_tail_segment; |
1932 | struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; |
1933 | struct xilinx_cdma_tx_segment *cdma_tail_segment; |
1934 | |
1935 | if (list_empty(head: &chan->pending_list)) |
1936 | goto append; |
1937 | |
1938 | /* |
1939 | * Add the hardware descriptor to the chain of hardware descriptors |
1940 | * that already exists in memory. |
1941 | */ |
1942 | tail_desc = list_last_entry(&chan->pending_list, |
1943 | struct xilinx_dma_tx_descriptor, node); |
1944 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
1945 | tail_segment = list_last_entry(&tail_desc->segments, |
1946 | struct xilinx_vdma_tx_segment, |
1947 | node); |
1948 | tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
1949 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
1950 | cdma_tail_segment = list_last_entry(&tail_desc->segments, |
1951 | struct xilinx_cdma_tx_segment, |
1952 | node); |
1953 | cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
1954 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
1955 | axidma_tail_segment = list_last_entry(&tail_desc->segments, |
1956 | struct xilinx_axidma_tx_segment, |
1957 | node); |
1958 | axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
1959 | } else { |
1960 | aximcdma_tail_segment = |
1961 | list_last_entry(&tail_desc->segments, |
1962 | struct xilinx_aximcdma_tx_segment, |
1963 | node); |
1964 | aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
1965 | } |
1966 | |
1967 | /* |
1968 | * Add the software descriptor and all children to the list |
1969 | * of pending transactions |
1970 | */ |
1971 | append: |
1972 | list_add_tail(new: &desc->node, head: &chan->pending_list); |
1973 | chan->desc_pendingcount++; |
1974 | |
1975 | if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) |
1976 | && unlikely(chan->desc_pendingcount > chan->num_frms)) { |
1977 | dev_dbg(chan->dev, "desc pendingcount is too high\n" ); |
1978 | chan->desc_pendingcount = chan->num_frms; |
1979 | } |
1980 | } |
1981 | |
1982 | /** |
1983 | * xilinx_dma_tx_submit - Submit DMA transaction |
1984 | * @tx: Async transaction descriptor |
1985 | * |
1986 | * Return: cookie value on success and failure value on error |
1987 | */ |
1988 | static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
1989 | { |
1990 | struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); |
1991 | struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); |
1992 | dma_cookie_t cookie; |
1993 | unsigned long flags; |
1994 | int err; |
1995 | |
1996 | if (chan->cyclic) { |
1997 | xilinx_dma_free_tx_descriptor(chan, desc); |
1998 | return -EBUSY; |
1999 | } |
2000 | |
2001 | if (chan->err) { |
2002 | /* |
2003 | * If reset fails, need to hard reset the system. |
2004 | * Channel is no longer functional |
2005 | */ |
2006 | err = xilinx_dma_chan_reset(chan); |
2007 | if (err < 0) |
2008 | return err; |
2009 | } |
2010 | |
2011 | spin_lock_irqsave(&chan->lock, flags); |
2012 | |
2013 | cookie = dma_cookie_assign(tx); |
2014 | |
2015 | /* Put this transaction onto the tail of the pending queue */ |
2016 | append_desc_queue(chan, desc); |
2017 | |
2018 | if (desc->cyclic) |
2019 | chan->cyclic = true; |
2020 | |
2021 | chan->terminating = false; |
2022 | |
2023 | spin_unlock_irqrestore(lock: &chan->lock, flags); |
2024 | |
2025 | return cookie; |
2026 | } |
2027 | |
2028 | /** |
2029 | * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a |
2030 | * DMA_SLAVE transaction |
2031 | * @dchan: DMA channel |
2032 | * @xt: Interleaved template pointer |
2033 | * @flags: transfer ack flags |
2034 | * |
2035 | * Return: Async transaction descriptor on success and NULL on failure |
2036 | */ |
2037 | static struct dma_async_tx_descriptor * |
2038 | xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, |
2039 | struct dma_interleaved_template *xt, |
2040 | unsigned long flags) |
2041 | { |
2042 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2043 | struct xilinx_dma_tx_descriptor *desc; |
2044 | struct xilinx_vdma_tx_segment *segment; |
2045 | struct xilinx_vdma_desc_hw *hw; |
2046 | |
2047 | if (!is_slave_direction(direction: xt->dir)) |
2048 | return NULL; |
2049 | |
2050 | if (!xt->numf || !xt->sgl[0].size) |
2051 | return NULL; |
2052 | |
2053 | if (xt->frame_size != 1) |
2054 | return NULL; |
2055 | |
2056 | /* Allocate a transaction descriptor. */ |
2057 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
2058 | if (!desc) |
2059 | return NULL; |
2060 | |
2061 | dma_async_tx_descriptor_init(tx: &desc->async_tx, chan: &chan->common); |
2062 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
2063 | async_tx_ack(tx: &desc->async_tx); |
2064 | |
2065 | /* Allocate the link descriptor from DMA pool */ |
2066 | segment = xilinx_vdma_alloc_tx_segment(chan); |
2067 | if (!segment) |
2068 | goto error; |
2069 | |
2070 | /* Fill in the hardware descriptor */ |
2071 | hw = &segment->hw; |
2072 | hw->vsize = xt->numf; |
2073 | hw->hsize = xt->sgl[0].size; |
2074 | hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << |
2075 | XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; |
2076 | hw->stride |= chan->config.frm_dly << |
2077 | XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; |
2078 | |
2079 | if (xt->dir != DMA_MEM_TO_DEV) { |
2080 | if (chan->ext_addr) { |
2081 | hw->buf_addr = lower_32_bits(xt->dst_start); |
2082 | hw->buf_addr_msb = upper_32_bits(xt->dst_start); |
2083 | } else { |
2084 | hw->buf_addr = xt->dst_start; |
2085 | } |
2086 | } else { |
2087 | if (chan->ext_addr) { |
2088 | hw->buf_addr = lower_32_bits(xt->src_start); |
2089 | hw->buf_addr_msb = upper_32_bits(xt->src_start); |
2090 | } else { |
2091 | hw->buf_addr = xt->src_start; |
2092 | } |
2093 | } |
2094 | |
2095 | /* Insert the segment into the descriptor segments list. */ |
2096 | list_add_tail(new: &segment->node, head: &desc->segments); |
2097 | |
2098 | /* Link the last hardware descriptor with the first. */ |
2099 | segment = list_first_entry(&desc->segments, |
2100 | struct xilinx_vdma_tx_segment, node); |
2101 | desc->async_tx.phys = segment->phys; |
2102 | |
2103 | return &desc->async_tx; |
2104 | |
2105 | error: |
2106 | xilinx_dma_free_tx_descriptor(chan, desc); |
2107 | return NULL; |
2108 | } |
2109 | |
2110 | /** |
2111 | * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction |
2112 | * @dchan: DMA channel |
2113 | * @dma_dst: destination address |
2114 | * @dma_src: source address |
2115 | * @len: transfer length |
2116 | * @flags: transfer ack flags |
2117 | * |
2118 | * Return: Async transaction descriptor on success and NULL on failure |
2119 | */ |
2120 | static struct dma_async_tx_descriptor * |
2121 | xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, |
2122 | dma_addr_t dma_src, size_t len, unsigned long flags) |
2123 | { |
2124 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2125 | struct xilinx_dma_tx_descriptor *desc; |
2126 | struct xilinx_cdma_tx_segment *segment; |
2127 | struct xilinx_cdma_desc_hw *hw; |
2128 | |
2129 | if (!len || len > chan->xdev->max_buffer_len) |
2130 | return NULL; |
2131 | |
2132 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
2133 | if (!desc) |
2134 | return NULL; |
2135 | |
2136 | dma_async_tx_descriptor_init(tx: &desc->async_tx, chan: &chan->common); |
2137 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
2138 | |
2139 | /* Allocate the link descriptor from DMA pool */ |
2140 | segment = xilinx_cdma_alloc_tx_segment(chan); |
2141 | if (!segment) |
2142 | goto error; |
2143 | |
2144 | hw = &segment->hw; |
2145 | hw->control = len; |
2146 | hw->src_addr = dma_src; |
2147 | hw->dest_addr = dma_dst; |
2148 | if (chan->ext_addr) { |
2149 | hw->src_addr_msb = upper_32_bits(dma_src); |
2150 | hw->dest_addr_msb = upper_32_bits(dma_dst); |
2151 | } |
2152 | |
2153 | /* Insert the segment into the descriptor segments list. */ |
2154 | list_add_tail(new: &segment->node, head: &desc->segments); |
2155 | |
2156 | desc->async_tx.phys = segment->phys; |
2157 | hw->next_desc = segment->phys; |
2158 | |
2159 | return &desc->async_tx; |
2160 | |
2161 | error: |
2162 | xilinx_dma_free_tx_descriptor(chan, desc); |
2163 | return NULL; |
2164 | } |
2165 | |
2166 | /** |
2167 | * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction |
2168 | * @dchan: DMA channel |
2169 | * @sgl: scatterlist to transfer to/from |
2170 | * @sg_len: number of entries in @scatterlist |
2171 | * @direction: DMA direction |
2172 | * @flags: transfer ack flags |
2173 | * @context: APP words of the descriptor |
2174 | * |
2175 | * Return: Async transaction descriptor on success and NULL on failure |
2176 | */ |
2177 | static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( |
2178 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
2179 | enum dma_transfer_direction direction, unsigned long flags, |
2180 | void *context) |
2181 | { |
2182 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2183 | struct xilinx_dma_tx_descriptor *desc; |
2184 | struct xilinx_axidma_tx_segment *segment = NULL; |
2185 | u32 *app_w = (u32 *)context; |
2186 | struct scatterlist *sg; |
2187 | size_t copy; |
2188 | size_t sg_used; |
2189 | unsigned int i; |
2190 | |
2191 | if (!is_slave_direction(direction)) |
2192 | return NULL; |
2193 | |
2194 | /* Allocate a transaction descriptor. */ |
2195 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
2196 | if (!desc) |
2197 | return NULL; |
2198 | |
2199 | dma_async_tx_descriptor_init(tx: &desc->async_tx, chan: &chan->common); |
2200 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
2201 | |
2202 | /* Build transactions using information in the scatter gather list */ |
2203 | for_each_sg(sgl, sg, sg_len, i) { |
2204 | sg_used = 0; |
2205 | |
2206 | /* Loop until the entire scatterlist entry is used */ |
2207 | while (sg_used < sg_dma_len(sg)) { |
2208 | struct xilinx_axidma_desc_hw *hw; |
2209 | |
2210 | /* Get a free segment */ |
2211 | segment = xilinx_axidma_alloc_tx_segment(chan); |
2212 | if (!segment) |
2213 | goto error; |
2214 | |
2215 | /* |
2216 | * Calculate the maximum number of bytes to transfer, |
2217 | * making sure it is less than the hw limit |
2218 | */ |
2219 | copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), |
2220 | done: sg_used); |
2221 | hw = &segment->hw; |
2222 | |
2223 | /* Fill in the descriptor */ |
2224 | xilinx_axidma_buf(chan, hw, sg_dma_address(sg), |
2225 | sg_used, period_len: 0); |
2226 | |
2227 | hw->control = copy; |
2228 | |
2229 | if (chan->direction == DMA_MEM_TO_DEV) { |
2230 | if (app_w) |
2231 | memcpy(hw->app, app_w, sizeof(u32) * |
2232 | XILINX_DMA_NUM_APP_WORDS); |
2233 | } |
2234 | |
2235 | sg_used += copy; |
2236 | |
2237 | /* |
2238 | * Insert the segment into the descriptor segments |
2239 | * list. |
2240 | */ |
2241 | list_add_tail(new: &segment->node, head: &desc->segments); |
2242 | } |
2243 | } |
2244 | |
2245 | segment = list_first_entry(&desc->segments, |
2246 | struct xilinx_axidma_tx_segment, node); |
2247 | desc->async_tx.phys = segment->phys; |
2248 | |
2249 | /* For the last DMA_MEM_TO_DEV transfer, set EOP */ |
2250 | if (chan->direction == DMA_MEM_TO_DEV) { |
2251 | segment->hw.control |= XILINX_DMA_BD_SOP; |
2252 | segment = list_last_entry(&desc->segments, |
2253 | struct xilinx_axidma_tx_segment, |
2254 | node); |
2255 | segment->hw.control |= XILINX_DMA_BD_EOP; |
2256 | } |
2257 | |
2258 | if (chan->xdev->has_axistream_connected) |
2259 | desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; |
2260 | |
2261 | return &desc->async_tx; |
2262 | |
2263 | error: |
2264 | xilinx_dma_free_tx_descriptor(chan, desc); |
2265 | return NULL; |
2266 | } |
2267 | |
2268 | /** |
2269 | * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction |
2270 | * @dchan: DMA channel |
2271 | * @buf_addr: Physical address of the buffer |
2272 | * @buf_len: Total length of the cyclic buffers |
2273 | * @period_len: length of individual cyclic buffer |
2274 | * @direction: DMA direction |
2275 | * @flags: transfer ack flags |
2276 | * |
2277 | * Return: Async transaction descriptor on success and NULL on failure |
2278 | */ |
2279 | static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( |
2280 | struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, |
2281 | size_t period_len, enum dma_transfer_direction direction, |
2282 | unsigned long flags) |
2283 | { |
2284 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2285 | struct xilinx_dma_tx_descriptor *desc; |
2286 | struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; |
2287 | size_t copy, sg_used; |
2288 | unsigned int num_periods; |
2289 | int i; |
2290 | u32 reg; |
2291 | |
2292 | if (!period_len) |
2293 | return NULL; |
2294 | |
2295 | num_periods = buf_len / period_len; |
2296 | |
2297 | if (!num_periods) |
2298 | return NULL; |
2299 | |
2300 | if (!is_slave_direction(direction)) |
2301 | return NULL; |
2302 | |
2303 | /* Allocate a transaction descriptor. */ |
2304 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
2305 | if (!desc) |
2306 | return NULL; |
2307 | |
2308 | chan->direction = direction; |
2309 | dma_async_tx_descriptor_init(tx: &desc->async_tx, chan: &chan->common); |
2310 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
2311 | |
2312 | for (i = 0; i < num_periods; ++i) { |
2313 | sg_used = 0; |
2314 | |
2315 | while (sg_used < period_len) { |
2316 | struct xilinx_axidma_desc_hw *hw; |
2317 | |
2318 | /* Get a free segment */ |
2319 | segment = xilinx_axidma_alloc_tx_segment(chan); |
2320 | if (!segment) |
2321 | goto error; |
2322 | |
2323 | /* |
2324 | * Calculate the maximum number of bytes to transfer, |
2325 | * making sure it is less than the hw limit |
2326 | */ |
2327 | copy = xilinx_dma_calc_copysize(chan, size: period_len, |
2328 | done: sg_used); |
2329 | hw = &segment->hw; |
2330 | xilinx_axidma_buf(chan, hw, buf_addr, sg_used, |
2331 | period_len: period_len * i); |
2332 | hw->control = copy; |
2333 | |
2334 | if (prev) |
2335 | prev->hw.next_desc = segment->phys; |
2336 | |
2337 | prev = segment; |
2338 | sg_used += copy; |
2339 | |
2340 | /* |
2341 | * Insert the segment into the descriptor segments |
2342 | * list. |
2343 | */ |
2344 | list_add_tail(new: &segment->node, head: &desc->segments); |
2345 | } |
2346 | } |
2347 | |
2348 | head_segment = list_first_entry(&desc->segments, |
2349 | struct xilinx_axidma_tx_segment, node); |
2350 | desc->async_tx.phys = head_segment->phys; |
2351 | |
2352 | desc->cyclic = true; |
2353 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
2354 | reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; |
2355 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: reg); |
2356 | |
2357 | segment = list_last_entry(&desc->segments, |
2358 | struct xilinx_axidma_tx_segment, |
2359 | node); |
2360 | segment->hw.next_desc = (u32) head_segment->phys; |
2361 | |
2362 | /* For the last DMA_MEM_TO_DEV transfer, set EOP */ |
2363 | if (direction == DMA_MEM_TO_DEV) { |
2364 | head_segment->hw.control |= XILINX_DMA_BD_SOP; |
2365 | segment->hw.control |= XILINX_DMA_BD_EOP; |
2366 | } |
2367 | |
2368 | return &desc->async_tx; |
2369 | |
2370 | error: |
2371 | xilinx_dma_free_tx_descriptor(chan, desc); |
2372 | return NULL; |
2373 | } |
2374 | |
2375 | /** |
2376 | * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction |
2377 | * @dchan: DMA channel |
2378 | * @sgl: scatterlist to transfer to/from |
2379 | * @sg_len: number of entries in @scatterlist |
2380 | * @direction: DMA direction |
2381 | * @flags: transfer ack flags |
2382 | * @context: APP words of the descriptor |
2383 | * |
2384 | * Return: Async transaction descriptor on success and NULL on failure |
2385 | */ |
2386 | static struct dma_async_tx_descriptor * |
2387 | xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, |
2388 | unsigned int sg_len, |
2389 | enum dma_transfer_direction direction, |
2390 | unsigned long flags, void *context) |
2391 | { |
2392 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2393 | struct xilinx_dma_tx_descriptor *desc; |
2394 | struct xilinx_aximcdma_tx_segment *segment = NULL; |
2395 | u32 *app_w = (u32 *)context; |
2396 | struct scatterlist *sg; |
2397 | size_t copy; |
2398 | size_t sg_used; |
2399 | unsigned int i; |
2400 | |
2401 | if (!is_slave_direction(direction)) |
2402 | return NULL; |
2403 | |
2404 | /* Allocate a transaction descriptor. */ |
2405 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
2406 | if (!desc) |
2407 | return NULL; |
2408 | |
2409 | dma_async_tx_descriptor_init(tx: &desc->async_tx, chan: &chan->common); |
2410 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
2411 | |
2412 | /* Build transactions using information in the scatter gather list */ |
2413 | for_each_sg(sgl, sg, sg_len, i) { |
2414 | sg_used = 0; |
2415 | |
2416 | /* Loop until the entire scatterlist entry is used */ |
2417 | while (sg_used < sg_dma_len(sg)) { |
2418 | struct xilinx_aximcdma_desc_hw *hw; |
2419 | |
2420 | /* Get a free segment */ |
2421 | segment = xilinx_aximcdma_alloc_tx_segment(chan); |
2422 | if (!segment) |
2423 | goto error; |
2424 | |
2425 | /* |
2426 | * Calculate the maximum number of bytes to transfer, |
2427 | * making sure it is less than the hw limit |
2428 | */ |
2429 | copy = min_t(size_t, sg_dma_len(sg) - sg_used, |
2430 | chan->xdev->max_buffer_len); |
2431 | hw = &segment->hw; |
2432 | |
2433 | /* Fill in the descriptor */ |
2434 | xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), |
2435 | sg_used); |
2436 | hw->control = copy; |
2437 | |
2438 | if (chan->direction == DMA_MEM_TO_DEV && app_w) { |
2439 | memcpy(hw->app, app_w, sizeof(u32) * |
2440 | XILINX_DMA_NUM_APP_WORDS); |
2441 | } |
2442 | |
2443 | sg_used += copy; |
2444 | /* |
2445 | * Insert the segment into the descriptor segments |
2446 | * list. |
2447 | */ |
2448 | list_add_tail(new: &segment->node, head: &desc->segments); |
2449 | } |
2450 | } |
2451 | |
2452 | segment = list_first_entry(&desc->segments, |
2453 | struct xilinx_aximcdma_tx_segment, node); |
2454 | desc->async_tx.phys = segment->phys; |
2455 | |
2456 | /* For the last DMA_MEM_TO_DEV transfer, set EOP */ |
2457 | if (chan->direction == DMA_MEM_TO_DEV) { |
2458 | segment->hw.control |= XILINX_MCDMA_BD_SOP; |
2459 | segment = list_last_entry(&desc->segments, |
2460 | struct xilinx_aximcdma_tx_segment, |
2461 | node); |
2462 | segment->hw.control |= XILINX_MCDMA_BD_EOP; |
2463 | } |
2464 | |
2465 | return &desc->async_tx; |
2466 | |
2467 | error: |
2468 | xilinx_dma_free_tx_descriptor(chan, desc); |
2469 | |
2470 | return NULL; |
2471 | } |
2472 | |
2473 | /** |
2474 | * xilinx_dma_terminate_all - Halt the channel and free descriptors |
2475 | * @dchan: Driver specific DMA Channel pointer |
2476 | * |
2477 | * Return: '0' always. |
2478 | */ |
2479 | static int xilinx_dma_terminate_all(struct dma_chan *dchan) |
2480 | { |
2481 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2482 | u32 reg; |
2483 | int err; |
2484 | |
2485 | if (!chan->cyclic) { |
2486 | err = chan->stop_transfer(chan); |
2487 | if (err) { |
2488 | dev_err(chan->dev, "Cannot stop channel %p: %x\n" , |
2489 | chan, dma_ctrl_read(chan, |
2490 | XILINX_DMA_REG_DMASR)); |
2491 | chan->err = true; |
2492 | } |
2493 | } |
2494 | |
2495 | xilinx_dma_chan_reset(chan); |
2496 | /* Remove and free all of the descriptors in the lists */ |
2497 | chan->terminating = true; |
2498 | xilinx_dma_free_descriptors(chan); |
2499 | chan->idle = true; |
2500 | |
2501 | if (chan->cyclic) { |
2502 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
2503 | reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; |
2504 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: reg); |
2505 | chan->cyclic = false; |
2506 | } |
2507 | |
2508 | if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) |
2509 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, |
2510 | XILINX_CDMA_CR_SGMODE); |
2511 | |
2512 | return 0; |
2513 | } |
2514 | |
2515 | static void xilinx_dma_synchronize(struct dma_chan *dchan) |
2516 | { |
2517 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2518 | |
2519 | tasklet_kill(t: &chan->tasklet); |
2520 | } |
2521 | |
2522 | /** |
2523 | * xilinx_vdma_channel_set_config - Configure VDMA channel |
2524 | * Run-time configuration for Axi VDMA, supports: |
2525 | * . halt the channel |
2526 | * . configure interrupt coalescing and inter-packet delay threshold |
2527 | * . start/stop parking |
2528 | * . enable genlock |
2529 | * |
2530 | * @dchan: DMA channel |
2531 | * @cfg: VDMA device configuration pointer |
2532 | * |
2533 | * Return: '0' on success and failure value on error |
2534 | */ |
2535 | int xilinx_vdma_channel_set_config(struct dma_chan *dchan, |
2536 | struct xilinx_vdma_config *cfg) |
2537 | { |
2538 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
2539 | u32 dmacr; |
2540 | |
2541 | if (cfg->reset) |
2542 | return xilinx_dma_chan_reset(chan); |
2543 | |
2544 | dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
2545 | |
2546 | chan->config.frm_dly = cfg->frm_dly; |
2547 | chan->config.park = cfg->park; |
2548 | |
2549 | /* genlock settings */ |
2550 | chan->config.gen_lock = cfg->gen_lock; |
2551 | chan->config.master = cfg->master; |
2552 | |
2553 | dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; |
2554 | if (cfg->gen_lock && chan->genlock) { |
2555 | dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; |
2556 | dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; |
2557 | dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; |
2558 | } |
2559 | |
2560 | chan->config.frm_cnt_en = cfg->frm_cnt_en; |
2561 | chan->config.vflip_en = cfg->vflip_en; |
2562 | |
2563 | if (cfg->park) |
2564 | chan->config.park_frm = cfg->park_frm; |
2565 | else |
2566 | chan->config.park_frm = -1; |
2567 | |
2568 | chan->config.coalesc = cfg->coalesc; |
2569 | chan->config.delay = cfg->delay; |
2570 | |
2571 | if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { |
2572 | dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; |
2573 | dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; |
2574 | chan->config.coalesc = cfg->coalesc; |
2575 | } |
2576 | |
2577 | if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { |
2578 | dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; |
2579 | dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; |
2580 | chan->config.delay = cfg->delay; |
2581 | } |
2582 | |
2583 | /* FSync Source selection */ |
2584 | dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; |
2585 | dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; |
2586 | |
2587 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, value: dmacr); |
2588 | |
2589 | return 0; |
2590 | } |
2591 | EXPORT_SYMBOL(xilinx_vdma_channel_set_config); |
2592 | |
2593 | /* ----------------------------------------------------------------------------- |
2594 | * Probe and remove |
2595 | */ |
2596 | |
2597 | /** |
2598 | * xilinx_dma_chan_remove - Per Channel remove function |
2599 | * @chan: Driver specific DMA channel |
2600 | */ |
2601 | static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) |
2602 | { |
2603 | /* Disable all interrupts */ |
2604 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, |
2605 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
2606 | |
2607 | if (chan->irq > 0) |
2608 | free_irq(chan->irq, chan); |
2609 | |
2610 | tasklet_kill(t: &chan->tasklet); |
2611 | |
2612 | list_del(entry: &chan->common.device_node); |
2613 | } |
2614 | |
2615 | static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
2616 | struct clk **tx_clk, struct clk **rx_clk, |
2617 | struct clk **sg_clk, struct clk **tmp_clk) |
2618 | { |
2619 | int err; |
2620 | |
2621 | *tmp_clk = NULL; |
2622 | |
2623 | *axi_clk = devm_clk_get(dev: &pdev->dev, id: "s_axi_lite_aclk" ); |
2624 | if (IS_ERR(ptr: *axi_clk)) |
2625 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: *axi_clk), fmt: "failed to get axi_aclk\n" ); |
2626 | |
2627 | *tx_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_mm2s_aclk" ); |
2628 | if (IS_ERR(ptr: *tx_clk)) |
2629 | *tx_clk = NULL; |
2630 | |
2631 | *rx_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_s2mm_aclk" ); |
2632 | if (IS_ERR(ptr: *rx_clk)) |
2633 | *rx_clk = NULL; |
2634 | |
2635 | *sg_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_sg_aclk" ); |
2636 | if (IS_ERR(ptr: *sg_clk)) |
2637 | *sg_clk = NULL; |
2638 | |
2639 | err = clk_prepare_enable(clk: *axi_clk); |
2640 | if (err) { |
2641 | dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n" , err); |
2642 | return err; |
2643 | } |
2644 | |
2645 | err = clk_prepare_enable(clk: *tx_clk); |
2646 | if (err) { |
2647 | dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n" , err); |
2648 | goto err_disable_axiclk; |
2649 | } |
2650 | |
2651 | err = clk_prepare_enable(clk: *rx_clk); |
2652 | if (err) { |
2653 | dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n" , err); |
2654 | goto err_disable_txclk; |
2655 | } |
2656 | |
2657 | err = clk_prepare_enable(clk: *sg_clk); |
2658 | if (err) { |
2659 | dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n" , err); |
2660 | goto err_disable_rxclk; |
2661 | } |
2662 | |
2663 | return 0; |
2664 | |
2665 | err_disable_rxclk: |
2666 | clk_disable_unprepare(clk: *rx_clk); |
2667 | err_disable_txclk: |
2668 | clk_disable_unprepare(clk: *tx_clk); |
2669 | err_disable_axiclk: |
2670 | clk_disable_unprepare(clk: *axi_clk); |
2671 | |
2672 | return err; |
2673 | } |
2674 | |
2675 | static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
2676 | struct clk **dev_clk, struct clk **tmp_clk, |
2677 | struct clk **tmp1_clk, struct clk **tmp2_clk) |
2678 | { |
2679 | int err; |
2680 | |
2681 | *tmp_clk = NULL; |
2682 | *tmp1_clk = NULL; |
2683 | *tmp2_clk = NULL; |
2684 | |
2685 | *axi_clk = devm_clk_get(dev: &pdev->dev, id: "s_axi_lite_aclk" ); |
2686 | if (IS_ERR(ptr: *axi_clk)) |
2687 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: *axi_clk), fmt: "failed to get axi_aclk\n" ); |
2688 | |
2689 | *dev_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_aclk" ); |
2690 | if (IS_ERR(ptr: *dev_clk)) |
2691 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: *dev_clk), fmt: "failed to get dev_clk\n" ); |
2692 | |
2693 | err = clk_prepare_enable(clk: *axi_clk); |
2694 | if (err) { |
2695 | dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n" , err); |
2696 | return err; |
2697 | } |
2698 | |
2699 | err = clk_prepare_enable(clk: *dev_clk); |
2700 | if (err) { |
2701 | dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n" , err); |
2702 | goto err_disable_axiclk; |
2703 | } |
2704 | |
2705 | return 0; |
2706 | |
2707 | err_disable_axiclk: |
2708 | clk_disable_unprepare(clk: *axi_clk); |
2709 | |
2710 | return err; |
2711 | } |
2712 | |
2713 | static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
2714 | struct clk **tx_clk, struct clk **txs_clk, |
2715 | struct clk **rx_clk, struct clk **rxs_clk) |
2716 | { |
2717 | int err; |
2718 | |
2719 | *axi_clk = devm_clk_get(dev: &pdev->dev, id: "s_axi_lite_aclk" ); |
2720 | if (IS_ERR(ptr: *axi_clk)) |
2721 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: *axi_clk), fmt: "failed to get axi_aclk\n" ); |
2722 | |
2723 | *tx_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_mm2s_aclk" ); |
2724 | if (IS_ERR(ptr: *tx_clk)) |
2725 | *tx_clk = NULL; |
2726 | |
2727 | *txs_clk = devm_clk_get(dev: &pdev->dev, id: "m_axis_mm2s_aclk" ); |
2728 | if (IS_ERR(ptr: *txs_clk)) |
2729 | *txs_clk = NULL; |
2730 | |
2731 | *rx_clk = devm_clk_get(dev: &pdev->dev, id: "m_axi_s2mm_aclk" ); |
2732 | if (IS_ERR(ptr: *rx_clk)) |
2733 | *rx_clk = NULL; |
2734 | |
2735 | *rxs_clk = devm_clk_get(dev: &pdev->dev, id: "s_axis_s2mm_aclk" ); |
2736 | if (IS_ERR(ptr: *rxs_clk)) |
2737 | *rxs_clk = NULL; |
2738 | |
2739 | err = clk_prepare_enable(clk: *axi_clk); |
2740 | if (err) { |
2741 | dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n" , |
2742 | err); |
2743 | return err; |
2744 | } |
2745 | |
2746 | err = clk_prepare_enable(clk: *tx_clk); |
2747 | if (err) { |
2748 | dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n" , err); |
2749 | goto err_disable_axiclk; |
2750 | } |
2751 | |
2752 | err = clk_prepare_enable(clk: *txs_clk); |
2753 | if (err) { |
2754 | dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n" , err); |
2755 | goto err_disable_txclk; |
2756 | } |
2757 | |
2758 | err = clk_prepare_enable(clk: *rx_clk); |
2759 | if (err) { |
2760 | dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n" , err); |
2761 | goto err_disable_txsclk; |
2762 | } |
2763 | |
2764 | err = clk_prepare_enable(clk: *rxs_clk); |
2765 | if (err) { |
2766 | dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n" , err); |
2767 | goto err_disable_rxclk; |
2768 | } |
2769 | |
2770 | return 0; |
2771 | |
2772 | err_disable_rxclk: |
2773 | clk_disable_unprepare(clk: *rx_clk); |
2774 | err_disable_txsclk: |
2775 | clk_disable_unprepare(clk: *txs_clk); |
2776 | err_disable_txclk: |
2777 | clk_disable_unprepare(clk: *tx_clk); |
2778 | err_disable_axiclk: |
2779 | clk_disable_unprepare(clk: *axi_clk); |
2780 | |
2781 | return err; |
2782 | } |
2783 | |
2784 | static void xdma_disable_allclks(struct xilinx_dma_device *xdev) |
2785 | { |
2786 | clk_disable_unprepare(clk: xdev->rxs_clk); |
2787 | clk_disable_unprepare(clk: xdev->rx_clk); |
2788 | clk_disable_unprepare(clk: xdev->txs_clk); |
2789 | clk_disable_unprepare(clk: xdev->tx_clk); |
2790 | clk_disable_unprepare(clk: xdev->axi_clk); |
2791 | } |
2792 | |
2793 | /** |
2794 | * xilinx_dma_chan_probe - Per Channel Probing |
2795 | * It get channel features from the device tree entry and |
2796 | * initialize special channel handling routines |
2797 | * |
2798 | * @xdev: Driver specific device structure |
2799 | * @node: Device node |
2800 | * |
2801 | * Return: '0' on success and failure value on error |
2802 | */ |
2803 | static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, |
2804 | struct device_node *node) |
2805 | { |
2806 | struct xilinx_dma_chan *chan; |
2807 | bool has_dre = false; |
2808 | u32 value, width; |
2809 | int err; |
2810 | |
2811 | /* Allocate and initialize the channel structure */ |
2812 | chan = devm_kzalloc(dev: xdev->dev, size: sizeof(*chan), GFP_KERNEL); |
2813 | if (!chan) |
2814 | return -ENOMEM; |
2815 | |
2816 | chan->dev = xdev->dev; |
2817 | chan->xdev = xdev; |
2818 | chan->desc_pendingcount = 0x0; |
2819 | chan->ext_addr = xdev->ext_addr; |
2820 | /* This variable ensures that descriptors are not |
2821 | * Submitted when dma engine is in progress. This variable is |
2822 | * Added to avoid polling for a bit in the status register to |
2823 | * Know dma state in the driver hot path. |
2824 | */ |
2825 | chan->idle = true; |
2826 | |
2827 | spin_lock_init(&chan->lock); |
2828 | INIT_LIST_HEAD(list: &chan->pending_list); |
2829 | INIT_LIST_HEAD(list: &chan->done_list); |
2830 | INIT_LIST_HEAD(list: &chan->active_list); |
2831 | INIT_LIST_HEAD(list: &chan->free_seg_list); |
2832 | |
2833 | /* Retrieve the channel properties from the device tree */ |
2834 | has_dre = of_property_read_bool(np: node, propname: "xlnx,include-dre" ); |
2835 | |
2836 | of_property_read_u8(np: node, propname: "xlnx,irq-delay" , out_value: &chan->irq_delay); |
2837 | |
2838 | chan->genlock = of_property_read_bool(np: node, propname: "xlnx,genlock-mode" ); |
2839 | |
2840 | err = of_property_read_u32(np: node, propname: "xlnx,datawidth" , out_value: &value); |
2841 | if (err) { |
2842 | dev_err(xdev->dev, "missing xlnx,datawidth property\n" ); |
2843 | return err; |
2844 | } |
2845 | width = value >> 3; /* Convert bits to bytes */ |
2846 | |
2847 | /* If data width is greater than 8 bytes, DRE is not in hw */ |
2848 | if (width > 8) |
2849 | has_dre = false; |
2850 | |
2851 | if (!has_dre) |
2852 | xdev->common.copy_align = (enum dmaengine_alignment)fls(x: width - 1); |
2853 | |
2854 | if (of_device_is_compatible(device: node, "xlnx,axi-vdma-mm2s-channel" ) || |
2855 | of_device_is_compatible(device: node, "xlnx,axi-dma-mm2s-channel" ) || |
2856 | of_device_is_compatible(device: node, "xlnx,axi-cdma-channel" )) { |
2857 | chan->direction = DMA_MEM_TO_DEV; |
2858 | chan->id = xdev->mm2s_chan_id++; |
2859 | chan->tdest = chan->id; |
2860 | |
2861 | chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; |
2862 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
2863 | chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; |
2864 | chan->config.park = 1; |
2865 | |
2866 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
2867 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) |
2868 | chan->flush_on_fsync = true; |
2869 | } |
2870 | } else if (of_device_is_compatible(device: node, |
2871 | "xlnx,axi-vdma-s2mm-channel" ) || |
2872 | of_device_is_compatible(device: node, |
2873 | "xlnx,axi-dma-s2mm-channel" )) { |
2874 | chan->direction = DMA_DEV_TO_MEM; |
2875 | chan->id = xdev->s2mm_chan_id++; |
2876 | chan->tdest = chan->id - xdev->dma_config->max_channels / 2; |
2877 | chan->has_vflip = of_property_read_bool(np: node, |
2878 | propname: "xlnx,enable-vert-flip" ); |
2879 | if (chan->has_vflip) { |
2880 | chan->config.vflip_en = dma_read(chan, |
2881 | XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & |
2882 | XILINX_VDMA_ENABLE_VERTICAL_FLIP; |
2883 | } |
2884 | |
2885 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) |
2886 | chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; |
2887 | else |
2888 | chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; |
2889 | |
2890 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
2891 | chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; |
2892 | chan->config.park = 1; |
2893 | |
2894 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
2895 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) |
2896 | chan->flush_on_fsync = true; |
2897 | } |
2898 | } else { |
2899 | dev_err(xdev->dev, "Invalid channel compatible node\n" ); |
2900 | return -EINVAL; |
2901 | } |
2902 | |
2903 | /* Request the interrupt */ |
2904 | chan->irq = of_irq_get(dev: node, index: chan->tdest); |
2905 | if (chan->irq < 0) |
2906 | return dev_err_probe(dev: xdev->dev, err: chan->irq, fmt: "failed to get irq\n" ); |
2907 | err = request_irq(irq: chan->irq, handler: xdev->dma_config->irq_handler, |
2908 | IRQF_SHARED, name: "xilinx-dma-controller" , dev: chan); |
2909 | if (err) { |
2910 | dev_err(xdev->dev, "unable to request IRQ %d\n" , chan->irq); |
2911 | return err; |
2912 | } |
2913 | |
2914 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
2915 | chan->start_transfer = xilinx_dma_start_transfer; |
2916 | chan->stop_transfer = xilinx_dma_stop_transfer; |
2917 | } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { |
2918 | chan->start_transfer = xilinx_mcdma_start_transfer; |
2919 | chan->stop_transfer = xilinx_dma_stop_transfer; |
2920 | } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
2921 | chan->start_transfer = xilinx_cdma_start_transfer; |
2922 | chan->stop_transfer = xilinx_cdma_stop_transfer; |
2923 | } else { |
2924 | chan->start_transfer = xilinx_vdma_start_transfer; |
2925 | chan->stop_transfer = xilinx_dma_stop_transfer; |
2926 | } |
2927 | |
2928 | /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ |
2929 | if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { |
2930 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || |
2931 | dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & |
2932 | XILINX_DMA_DMASR_SG_MASK) |
2933 | chan->has_sg = true; |
2934 | dev_dbg(chan->dev, "ch %d: SG %s\n" , chan->id, |
2935 | chan->has_sg ? "enabled" : "disabled" ); |
2936 | } |
2937 | |
2938 | /* Initialize the tasklet */ |
2939 | tasklet_setup(t: &chan->tasklet, callback: xilinx_dma_do_tasklet); |
2940 | |
2941 | /* |
2942 | * Initialize the DMA channel and add it to the DMA engine channels |
2943 | * list. |
2944 | */ |
2945 | chan->common.device = &xdev->common; |
2946 | |
2947 | list_add_tail(new: &chan->common.device_node, head: &xdev->common.channels); |
2948 | xdev->chan[chan->id] = chan; |
2949 | |
2950 | /* Reset the channel */ |
2951 | err = xilinx_dma_chan_reset(chan); |
2952 | if (err < 0) { |
2953 | dev_err(xdev->dev, "Reset channel failed\n" ); |
2954 | return err; |
2955 | } |
2956 | |
2957 | return 0; |
2958 | } |
2959 | |
2960 | /** |
2961 | * xilinx_dma_child_probe - Per child node probe |
2962 | * It get number of dma-channels per child node from |
2963 | * device-tree and initializes all the channels. |
2964 | * |
2965 | * @xdev: Driver specific device structure |
2966 | * @node: Device node |
2967 | * |
2968 | * Return: '0' on success and failure value on error. |
2969 | */ |
2970 | static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, |
2971 | struct device_node *node) |
2972 | { |
2973 | int ret, i; |
2974 | u32 nr_channels = 1; |
2975 | |
2976 | ret = of_property_read_u32(np: node, propname: "dma-channels" , out_value: &nr_channels); |
2977 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) |
2978 | dev_warn(xdev->dev, "missing dma-channels property\n" ); |
2979 | |
2980 | for (i = 0; i < nr_channels; i++) { |
2981 | ret = xilinx_dma_chan_probe(xdev, node); |
2982 | if (ret) |
2983 | return ret; |
2984 | } |
2985 | |
2986 | return 0; |
2987 | } |
2988 | |
2989 | /** |
2990 | * of_dma_xilinx_xlate - Translation function |
2991 | * @dma_spec: Pointer to DMA specifier as found in the device tree |
2992 | * @ofdma: Pointer to DMA controller data |
2993 | * |
2994 | * Return: DMA channel pointer on success and NULL on error |
2995 | */ |
2996 | static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, |
2997 | struct of_dma *ofdma) |
2998 | { |
2999 | struct xilinx_dma_device *xdev = ofdma->of_dma_data; |
3000 | int chan_id = dma_spec->args[0]; |
3001 | |
3002 | if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) |
3003 | return NULL; |
3004 | |
3005 | return dma_get_slave_channel(chan: &xdev->chan[chan_id]->common); |
3006 | } |
3007 | |
3008 | static const struct xilinx_dma_config axidma_config = { |
3009 | .dmatype = XDMA_TYPE_AXIDMA, |
3010 | .clk_init = axidma_clk_init, |
3011 | .irq_handler = xilinx_dma_irq_handler, |
3012 | .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, |
3013 | }; |
3014 | |
3015 | static const struct xilinx_dma_config aximcdma_config = { |
3016 | .dmatype = XDMA_TYPE_AXIMCDMA, |
3017 | .clk_init = axidma_clk_init, |
3018 | .irq_handler = xilinx_mcdma_irq_handler, |
3019 | .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, |
3020 | }; |
3021 | static const struct xilinx_dma_config axicdma_config = { |
3022 | .dmatype = XDMA_TYPE_CDMA, |
3023 | .clk_init = axicdma_clk_init, |
3024 | .irq_handler = xilinx_dma_irq_handler, |
3025 | .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, |
3026 | }; |
3027 | |
3028 | static const struct xilinx_dma_config axivdma_config = { |
3029 | .dmatype = XDMA_TYPE_VDMA, |
3030 | .clk_init = axivdma_clk_init, |
3031 | .irq_handler = xilinx_dma_irq_handler, |
3032 | .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, |
3033 | }; |
3034 | |
3035 | static const struct of_device_id xilinx_dma_of_ids[] = { |
3036 | { .compatible = "xlnx,axi-dma-1.00.a" , .data = &axidma_config }, |
3037 | { .compatible = "xlnx,axi-cdma-1.00.a" , .data = &axicdma_config }, |
3038 | { .compatible = "xlnx,axi-vdma-1.00.a" , .data = &axivdma_config }, |
3039 | { .compatible = "xlnx,axi-mcdma-1.00.a" , .data = &aximcdma_config }, |
3040 | {} |
3041 | }; |
3042 | MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); |
3043 | |
3044 | /** |
3045 | * xilinx_dma_probe - Driver probe function |
3046 | * @pdev: Pointer to the platform_device structure |
3047 | * |
3048 | * Return: '0' on success and failure value on error |
3049 | */ |
3050 | static int xilinx_dma_probe(struct platform_device *pdev) |
3051 | { |
3052 | int (*clk_init)(struct platform_device *, struct clk **, struct clk **, |
3053 | struct clk **, struct clk **, struct clk **) |
3054 | = axivdma_clk_init; |
3055 | struct device_node *node = pdev->dev.of_node; |
3056 | struct xilinx_dma_device *xdev; |
3057 | struct device_node *child, *np = pdev->dev.of_node; |
3058 | u32 num_frames, addr_width, len_width; |
3059 | int i, err; |
3060 | |
3061 | /* Allocate and initialize the DMA engine structure */ |
3062 | xdev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*xdev), GFP_KERNEL); |
3063 | if (!xdev) |
3064 | return -ENOMEM; |
3065 | |
3066 | xdev->dev = &pdev->dev; |
3067 | if (np) { |
3068 | const struct of_device_id *match; |
3069 | |
3070 | match = of_match_node(matches: xilinx_dma_of_ids, node: np); |
3071 | if (match && match->data) { |
3072 | xdev->dma_config = match->data; |
3073 | clk_init = xdev->dma_config->clk_init; |
3074 | } |
3075 | } |
3076 | |
3077 | err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, |
3078 | &xdev->rx_clk, &xdev->rxs_clk); |
3079 | if (err) |
3080 | return err; |
3081 | |
3082 | /* Request and map I/O memory */ |
3083 | xdev->regs = devm_platform_ioremap_resource(pdev, index: 0); |
3084 | if (IS_ERR(ptr: xdev->regs)) { |
3085 | err = PTR_ERR(ptr: xdev->regs); |
3086 | goto disable_clks; |
3087 | } |
3088 | /* Retrieve the DMA engine properties from the device tree */ |
3089 | xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); |
3090 | xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; |
3091 | |
3092 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || |
3093 | xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { |
3094 | if (!of_property_read_u32(np: node, propname: "xlnx,sg-length-width" , |
3095 | out_value: &len_width)) { |
3096 | if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || |
3097 | len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { |
3098 | dev_warn(xdev->dev, |
3099 | "invalid xlnx,sg-length-width property value. Using default width\n" ); |
3100 | } else { |
3101 | if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) |
3102 | dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n" ); |
3103 | xdev->max_buffer_len = |
3104 | GENMASK(len_width - 1, 0); |
3105 | } |
3106 | } |
3107 | } |
3108 | |
3109 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
3110 | xdev->has_axistream_connected = |
3111 | of_property_read_bool(np: node, propname: "xlnx,axistream-connected" ); |
3112 | } |
3113 | |
3114 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
3115 | err = of_property_read_u32(np: node, propname: "xlnx,num-fstores" , |
3116 | out_value: &num_frames); |
3117 | if (err < 0) { |
3118 | dev_err(xdev->dev, |
3119 | "missing xlnx,num-fstores property\n" ); |
3120 | goto disable_clks; |
3121 | } |
3122 | |
3123 | err = of_property_read_u32(np: node, propname: "xlnx,flush-fsync" , |
3124 | out_value: &xdev->flush_on_fsync); |
3125 | if (err < 0) |
3126 | dev_warn(xdev->dev, |
3127 | "missing xlnx,flush-fsync property\n" ); |
3128 | } |
3129 | |
3130 | err = of_property_read_u32(np: node, propname: "xlnx,addrwidth" , out_value: &addr_width); |
3131 | if (err < 0) |
3132 | dev_warn(xdev->dev, "missing xlnx,addrwidth property\n" ); |
3133 | |
3134 | if (addr_width > 32) |
3135 | xdev->ext_addr = true; |
3136 | else |
3137 | xdev->ext_addr = false; |
3138 | |
3139 | /* Set metadata mode */ |
3140 | if (xdev->has_axistream_connected) |
3141 | xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; |
3142 | |
3143 | /* Set the dma mask bits */ |
3144 | err = dma_set_mask_and_coherent(dev: xdev->dev, DMA_BIT_MASK(addr_width)); |
3145 | if (err < 0) { |
3146 | dev_err(xdev->dev, "DMA mask error %d\n" , err); |
3147 | goto disable_clks; |
3148 | } |
3149 | |
3150 | /* Initialize the DMA engine */ |
3151 | xdev->common.dev = &pdev->dev; |
3152 | |
3153 | INIT_LIST_HEAD(list: &xdev->common.channels); |
3154 | if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { |
3155 | dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); |
3156 | dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); |
3157 | } |
3158 | |
3159 | xdev->common.device_alloc_chan_resources = |
3160 | xilinx_dma_alloc_chan_resources; |
3161 | xdev->common.device_free_chan_resources = |
3162 | xilinx_dma_free_chan_resources; |
3163 | xdev->common.device_terminate_all = xilinx_dma_terminate_all; |
3164 | xdev->common.device_synchronize = xilinx_dma_synchronize; |
3165 | xdev->common.device_tx_status = xilinx_dma_tx_status; |
3166 | xdev->common.device_issue_pending = xilinx_dma_issue_pending; |
3167 | xdev->common.device_config = xilinx_dma_device_config; |
3168 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
3169 | dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); |
3170 | xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; |
3171 | xdev->common.device_prep_dma_cyclic = |
3172 | xilinx_dma_prep_dma_cyclic; |
3173 | /* Residue calculation is supported by only AXI DMA and CDMA */ |
3174 | xdev->common.residue_granularity = |
3175 | DMA_RESIDUE_GRANULARITY_SEGMENT; |
3176 | } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
3177 | dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); |
3178 | xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; |
3179 | /* Residue calculation is supported by only AXI DMA and CDMA */ |
3180 | xdev->common.residue_granularity = |
3181 | DMA_RESIDUE_GRANULARITY_SEGMENT; |
3182 | } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { |
3183 | xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; |
3184 | } else { |
3185 | xdev->common.device_prep_interleaved_dma = |
3186 | xilinx_vdma_dma_prep_interleaved; |
3187 | } |
3188 | |
3189 | platform_set_drvdata(pdev, data: xdev); |
3190 | |
3191 | /* Initialize the channels */ |
3192 | for_each_child_of_node(node, child) { |
3193 | err = xilinx_dma_child_probe(xdev, node: child); |
3194 | if (err < 0) { |
3195 | of_node_put(node: child); |
3196 | goto error; |
3197 | } |
3198 | } |
3199 | |
3200 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
3201 | for (i = 0; i < xdev->dma_config->max_channels; i++) |
3202 | if (xdev->chan[i]) |
3203 | xdev->chan[i]->num_frms = num_frames; |
3204 | } |
3205 | |
3206 | /* Register the DMA engine with the core */ |
3207 | err = dma_async_device_register(device: &xdev->common); |
3208 | if (err) { |
3209 | dev_err(xdev->dev, "failed to register the dma device\n" ); |
3210 | goto error; |
3211 | } |
3212 | |
3213 | err = of_dma_controller_register(np: node, of_dma_xlate: of_dma_xilinx_xlate, |
3214 | data: xdev); |
3215 | if (err < 0) { |
3216 | dev_err(&pdev->dev, "Unable to register DMA to DT\n" ); |
3217 | dma_async_device_unregister(device: &xdev->common); |
3218 | goto error; |
3219 | } |
3220 | |
3221 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) |
3222 | dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n" ); |
3223 | else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) |
3224 | dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n" ); |
3225 | else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) |
3226 | dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n" ); |
3227 | else |
3228 | dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n" ); |
3229 | |
3230 | return 0; |
3231 | |
3232 | error: |
3233 | for (i = 0; i < xdev->dma_config->max_channels; i++) |
3234 | if (xdev->chan[i]) |
3235 | xilinx_dma_chan_remove(chan: xdev->chan[i]); |
3236 | disable_clks: |
3237 | xdma_disable_allclks(xdev); |
3238 | |
3239 | return err; |
3240 | } |
3241 | |
3242 | /** |
3243 | * xilinx_dma_remove - Driver remove function |
3244 | * @pdev: Pointer to the platform_device structure |
3245 | */ |
3246 | static void xilinx_dma_remove(struct platform_device *pdev) |
3247 | { |
3248 | struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); |
3249 | int i; |
3250 | |
3251 | of_dma_controller_free(np: pdev->dev.of_node); |
3252 | |
3253 | dma_async_device_unregister(device: &xdev->common); |
3254 | |
3255 | for (i = 0; i < xdev->dma_config->max_channels; i++) |
3256 | if (xdev->chan[i]) |
3257 | xilinx_dma_chan_remove(chan: xdev->chan[i]); |
3258 | |
3259 | xdma_disable_allclks(xdev); |
3260 | } |
3261 | |
3262 | static struct platform_driver xilinx_vdma_driver = { |
3263 | .driver = { |
3264 | .name = "xilinx-vdma" , |
3265 | .of_match_table = xilinx_dma_of_ids, |
3266 | }, |
3267 | .probe = xilinx_dma_probe, |
3268 | .remove_new = xilinx_dma_remove, |
3269 | }; |
3270 | |
3271 | module_platform_driver(xilinx_vdma_driver); |
3272 | |
3273 | MODULE_AUTHOR("Xilinx, Inc." ); |
3274 | MODULE_DESCRIPTION("Xilinx VDMA driver" ); |
3275 | MODULE_LICENSE("GPL v2" ); |
3276 | |