1/*
2 * edac_mc kernel module
3 * (C) 2005, 2006 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * Modified by Dave Peterson and Doug Thompson
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/proc_fs.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/smp.h>
20#include <linux/init.h>
21#include <linux/sysctl.h>
22#include <linux/highmem.h>
23#include <linux/timer.h>
24#include <linux/slab.h>
25#include <linux/jiffies.h>
26#include <linux/spinlock.h>
27#include <linux/list.h>
28#include <linux/ctype.h>
29#include <linux/edac.h>
30#include <linux/bitops.h>
31#include <linux/uaccess.h>
32#include <asm/page.h>
33#include "edac_mc.h"
34#include "edac_module.h"
35#include <ras/ras_event.h>
36
37#ifdef CONFIG_EDAC_ATOMIC_SCRUB
38#include <asm/edac.h>
39#else
40#define edac_atomic_scrub(va, size) do { } while (0)
41#endif
42
43int edac_op_state = EDAC_OPSTATE_INVAL;
44EXPORT_SYMBOL_GPL(edac_op_state);
45
46static int edac_report = EDAC_REPORTING_ENABLED;
47
48/* lock to memory controller's control array */
49static DEFINE_MUTEX(mem_ctls_mutex);
50static LIST_HEAD(mc_devices);
51
52/*
53 * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
54 * apei/ghes and i7core_edac to be used at the same time.
55 */
56static const char *edac_mc_owner;
57
58int edac_get_report_status(void)
59{
60 return edac_report;
61}
62EXPORT_SYMBOL_GPL(edac_get_report_status);
63
64void edac_set_report_status(int new)
65{
66 if (new == EDAC_REPORTING_ENABLED ||
67 new == EDAC_REPORTING_DISABLED ||
68 new == EDAC_REPORTING_FORCE)
69 edac_report = new;
70}
71EXPORT_SYMBOL_GPL(edac_set_report_status);
72
73static int edac_report_set(const char *str, const struct kernel_param *kp)
74{
75 if (!str)
76 return -EINVAL;
77
78 if (!strncmp(str, "on", 2))
79 edac_report = EDAC_REPORTING_ENABLED;
80 else if (!strncmp(str, "off", 3))
81 edac_report = EDAC_REPORTING_DISABLED;
82 else if (!strncmp(str, "force", 5))
83 edac_report = EDAC_REPORTING_FORCE;
84
85 return 0;
86}
87
88static int edac_report_get(char *buffer, const struct kernel_param *kp)
89{
90 int ret = 0;
91
92 switch (edac_report) {
93 case EDAC_REPORTING_ENABLED:
94 ret = sprintf(buffer, "on");
95 break;
96 case EDAC_REPORTING_DISABLED:
97 ret = sprintf(buffer, "off");
98 break;
99 case EDAC_REPORTING_FORCE:
100 ret = sprintf(buffer, "force");
101 break;
102 default:
103 ret = -EINVAL;
104 break;
105 }
106
107 return ret;
108}
109
110static const struct kernel_param_ops edac_report_ops = {
111 .set = edac_report_set,
112 .get = edac_report_get,
113};
114
115module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644);
116
117unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
118 unsigned len)
119{
120 struct mem_ctl_info *mci = dimm->mci;
121 int i, n, count = 0;
122 char *p = buf;
123
124 for (i = 0; i < mci->n_layers; i++) {
125 n = snprintf(p, len, "%s %d ",
126 edac_layer_name[mci->layers[i].type],
127 dimm->location[i]);
128 p += n;
129 len -= n;
130 count += n;
131 if (!len)
132 break;
133 }
134
135 return count;
136}
137
138#ifdef CONFIG_EDAC_DEBUG
139
140static void edac_mc_dump_channel(struct rank_info *chan)
141{
142 edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx);
143 edac_dbg(4, " channel = %p\n", chan);
144 edac_dbg(4, " channel->csrow = %p\n", chan->csrow);
145 edac_dbg(4, " channel->dimm = %p\n", chan->dimm);
146}
147
148static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
149{
150 char location[80];
151
152 edac_dimm_info_location(dimm, location, sizeof(location));
153
154 edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
155 dimm->mci->csbased ? "rank" : "dimm",
156 number, location, dimm->csrow, dimm->cschannel);
157 edac_dbg(4, " dimm = %p\n", dimm);
158 edac_dbg(4, " dimm->label = '%s'\n", dimm->label);
159 edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
160 edac_dbg(4, " dimm->grain = %d\n", dimm->grain);
161 edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
162}
163
164static void edac_mc_dump_csrow(struct csrow_info *csrow)
165{
166 edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
167 edac_dbg(4, " csrow = %p\n", csrow);
168 edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page);
169 edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page);
170 edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask);
171 edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels);
172 edac_dbg(4, " csrow->channels = %p\n", csrow->channels);
173 edac_dbg(4, " csrow->mci = %p\n", csrow->mci);
174}
175
176static void edac_mc_dump_mci(struct mem_ctl_info *mci)
177{
178 edac_dbg(3, "\tmci = %p\n", mci);
179 edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
180 edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
181 edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
182 edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
183 edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
184 mci->nr_csrows, mci->csrows);
185 edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
186 mci->tot_dimms, mci->dimms);
187 edac_dbg(3, "\tdev = %p\n", mci->pdev);
188 edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
189 mci->mod_name, mci->ctl_name);
190 edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
191}
192
193#endif /* CONFIG_EDAC_DEBUG */
194
195const char * const edac_mem_types[] = {
196 [MEM_EMPTY] = "Empty",
197 [MEM_RESERVED] = "Reserved",
198 [MEM_UNKNOWN] = "Unknown",
199 [MEM_FPM] = "FPM",
200 [MEM_EDO] = "EDO",
201 [MEM_BEDO] = "BEDO",
202 [MEM_SDR] = "Unbuffered-SDR",
203 [MEM_RDR] = "Registered-SDR",
204 [MEM_DDR] = "Unbuffered-DDR",
205 [MEM_RDDR] = "Registered-DDR",
206 [MEM_RMBS] = "RMBS",
207 [MEM_DDR2] = "Unbuffered-DDR2",
208 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
209 [MEM_RDDR2] = "Registered-DDR2",
210 [MEM_XDR] = "XDR",
211 [MEM_DDR3] = "Unbuffered-DDR3",
212 [MEM_RDDR3] = "Registered-DDR3",
213 [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM",
214 [MEM_DDR4] = "Unbuffered-DDR4",
215 [MEM_RDDR4] = "Registered-DDR4",
216 [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM",
217 [MEM_NVDIMM] = "Non-volatile-RAM",
218};
219EXPORT_SYMBOL_GPL(edac_mem_types);
220
221/**
222 * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
223 * @p: pointer to a pointer with the memory offset to be used. At
224 * return, this will be incremented to point to the next offset
225 * @size: Size of the data structure to be reserved
226 * @n_elems: Number of elements that should be reserved
227 *
228 * If 'size' is a constant, the compiler will optimize this whole function
229 * down to either a no-op or the addition of a constant to the value of '*p'.
230 *
231 * The 'p' pointer is absolutely needed to keep the proper advancing
232 * further in memory to the proper offsets when allocating the struct along
233 * with its embedded structs, as edac_device_alloc_ctl_info() does it
234 * above, for example.
235 *
236 * At return, the pointer 'p' will be incremented to be used on a next call
237 * to this function.
238 */
239void *edac_align_ptr(void **p, unsigned size, int n_elems)
240{
241 unsigned align, r;
242 void *ptr = *p;
243
244 *p += size * n_elems;
245
246 /*
247 * 'p' can possibly be an unaligned item X such that sizeof(X) is
248 * 'size'. Adjust 'p' so that its alignment is at least as
249 * stringent as what the compiler would provide for X and return
250 * the aligned result.
251 * Here we assume that the alignment of a "long long" is the most
252 * stringent alignment that the compiler will ever provide by default.
253 * As far as I know, this is a reasonable assumption.
254 */
255 if (size > sizeof(long))
256 align = sizeof(long long);
257 else if (size > sizeof(int))
258 align = sizeof(long);
259 else if (size > sizeof(short))
260 align = sizeof(int);
261 else if (size > sizeof(char))
262 align = sizeof(short);
263 else
264 return (char *)ptr;
265
266 r = (unsigned long)p % align;
267
268 if (r == 0)
269 return (char *)ptr;
270
271 *p += align - r;
272
273 return (void *)(((unsigned long)ptr) + align - r);
274}
275
276static void _edac_mc_free(struct mem_ctl_info *mci)
277{
278 int i, chn, row;
279 struct csrow_info *csr;
280 const unsigned int tot_dimms = mci->tot_dimms;
281 const unsigned int tot_channels = mci->num_cschannel;
282 const unsigned int tot_csrows = mci->nr_csrows;
283
284 if (mci->dimms) {
285 for (i = 0; i < tot_dimms; i++)
286 kfree(mci->dimms[i]);
287 kfree(mci->dimms);
288 }
289 if (mci->csrows) {
290 for (row = 0; row < tot_csrows; row++) {
291 csr = mci->csrows[row];
292 if (csr) {
293 if (csr->channels) {
294 for (chn = 0; chn < tot_channels; chn++)
295 kfree(csr->channels[chn]);
296 kfree(csr->channels);
297 }
298 kfree(csr);
299 }
300 }
301 kfree(mci->csrows);
302 }
303 kfree(mci);
304}
305
306struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
307 unsigned n_layers,
308 struct edac_mc_layer *layers,
309 unsigned sz_pvt)
310{
311 struct mem_ctl_info *mci;
312 struct edac_mc_layer *layer;
313 struct csrow_info *csr;
314 struct rank_info *chan;
315 struct dimm_info *dimm;
316 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
317 unsigned pos[EDAC_MAX_LAYERS];
318 unsigned size, tot_dimms = 1, count = 1;
319 unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0;
320 void *pvt, *p, *ptr = NULL;
321 int i, j, row, chn, n, len, off;
322 bool per_rank = false;
323
324 BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0);
325 /*
326 * Calculate the total amount of dimms and csrows/cschannels while
327 * in the old API emulation mode
328 */
329 for (i = 0; i < n_layers; i++) {
330 tot_dimms *= layers[i].size;
331 if (layers[i].is_virt_csrow)
332 tot_csrows *= layers[i].size;
333 else
334 tot_channels *= layers[i].size;
335
336 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT)
337 per_rank = true;
338 }
339
340 /* Figure out the offsets of the various items from the start of an mc
341 * structure. We want the alignment of each item to be at least as
342 * stringent as what the compiler would provide if we could simply
343 * hardcode everything into a single struct.
344 */
345 mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
346 layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
347 for (i = 0; i < n_layers; i++) {
348 count *= layers[i].size;
349 edac_dbg(4, "errcount layer %d size %d\n", i, count);
350 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
351 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
352 tot_errcount += 2 * count;
353 }
354
355 edac_dbg(4, "allocating %d error counters\n", tot_errcount);
356 pvt = edac_align_ptr(&ptr, sz_pvt, 1);
357 size = ((unsigned long)pvt) + sz_pvt;
358
359 edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
360 size,
361 tot_dimms,
362 per_rank ? "ranks" : "dimms",
363 tot_csrows * tot_channels);
364
365 mci = kzalloc(size, GFP_KERNEL);
366 if (mci == NULL)
367 return NULL;
368
369 /* Adjust pointers so they point within the memory we just allocated
370 * rather than an imaginary chunk of memory located at address 0.
371 */
372 layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
373 for (i = 0; i < n_layers; i++) {
374 mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i]));
375 mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i]));
376 }
377 pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
378
379 /* setup index and various internal pointers */
380 mci->mc_idx = mc_num;
381 mci->tot_dimms = tot_dimms;
382 mci->pvt_info = pvt;
383 mci->n_layers = n_layers;
384 mci->layers = layer;
385 memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
386 mci->nr_csrows = tot_csrows;
387 mci->num_cschannel = tot_channels;
388 mci->csbased = per_rank;
389
390 /*
391 * Alocate and fill the csrow/channels structs
392 */
393 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
394 if (!mci->csrows)
395 goto error;
396 for (row = 0; row < tot_csrows; row++) {
397 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
398 if (!csr)
399 goto error;
400 mci->csrows[row] = csr;
401 csr->csrow_idx = row;
402 csr->mci = mci;
403 csr->nr_channels = tot_channels;
404 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
405 GFP_KERNEL);
406 if (!csr->channels)
407 goto error;
408
409 for (chn = 0; chn < tot_channels; chn++) {
410 chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
411 if (!chan)
412 goto error;
413 csr->channels[chn] = chan;
414 chan->chan_idx = chn;
415 chan->csrow = csr;
416 }
417 }
418
419 /*
420 * Allocate and fill the dimm structs
421 */
422 mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
423 if (!mci->dimms)
424 goto error;
425
426 memset(&pos, 0, sizeof(pos));
427 row = 0;
428 chn = 0;
429 for (i = 0; i < tot_dimms; i++) {
430 chan = mci->csrows[row]->channels[chn];
431 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
432 if (off < 0 || off >= tot_dimms) {
433 edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n");
434 goto error;
435 }
436
437 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
438 if (!dimm)
439 goto error;
440 mci->dimms[off] = dimm;
441 dimm->mci = mci;
442
443 /*
444 * Copy DIMM location and initialize it.
445 */
446 len = sizeof(dimm->label);
447 p = dimm->label;
448 n = snprintf(p, len, "mc#%u", mc_num);
449 p += n;
450 len -= n;
451 for (j = 0; j < n_layers; j++) {
452 n = snprintf(p, len, "%s#%u",
453 edac_layer_name[layers[j].type],
454 pos[j]);
455 p += n;
456 len -= n;
457 dimm->location[j] = pos[j];
458
459 if (len <= 0)
460 break;
461 }
462
463 /* Link it to the csrows old API data */
464 chan->dimm = dimm;
465 dimm->csrow = row;
466 dimm->cschannel = chn;
467
468 /* Increment csrow location */
469 if (layers[0].is_virt_csrow) {
470 chn++;
471 if (chn == tot_channels) {
472 chn = 0;
473 row++;
474 }
475 } else {
476 row++;
477 if (row == tot_csrows) {
478 row = 0;
479 chn++;
480 }
481 }
482
483 /* Increment dimm location */
484 for (j = n_layers - 1; j >= 0; j--) {
485 pos[j]++;
486 if (pos[j] < layers[j].size)
487 break;
488 pos[j] = 0;
489 }
490 }
491
492 mci->op_state = OP_ALLOC;
493
494 return mci;
495
496error:
497 _edac_mc_free(mci);
498
499 return NULL;
500}
501EXPORT_SYMBOL_GPL(edac_mc_alloc);
502
503void edac_mc_free(struct mem_ctl_info *mci)
504{
505 edac_dbg(1, "\n");
506
507 /* If we're not yet registered with sysfs free only what was allocated
508 * in edac_mc_alloc().
509 */
510 if (!device_is_registered(&mci->dev)) {
511 _edac_mc_free(mci);
512 return;
513 }
514
515 /* the mci instance is freed here, when the sysfs object is dropped */
516 edac_unregister_sysfs(mci);
517}
518EXPORT_SYMBOL_GPL(edac_mc_free);
519
520bool edac_has_mcs(void)
521{
522 bool ret;
523
524 mutex_lock(&mem_ctls_mutex);
525
526 ret = list_empty(&mc_devices);
527
528 mutex_unlock(&mem_ctls_mutex);
529
530 return !ret;
531}
532EXPORT_SYMBOL_GPL(edac_has_mcs);
533
534/* Caller must hold mem_ctls_mutex */
535static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
536{
537 struct mem_ctl_info *mci;
538 struct list_head *item;
539
540 edac_dbg(3, "\n");
541
542 list_for_each(item, &mc_devices) {
543 mci = list_entry(item, struct mem_ctl_info, link);
544
545 if (mci->pdev == dev)
546 return mci;
547 }
548
549 return NULL;
550}
551
552/**
553 * find_mci_by_dev
554 *
555 * scan list of controllers looking for the one that manages
556 * the 'dev' device
557 * @dev: pointer to a struct device related with the MCI
558 */
559struct mem_ctl_info *find_mci_by_dev(struct device *dev)
560{
561 struct mem_ctl_info *ret;
562
563 mutex_lock(&mem_ctls_mutex);
564 ret = __find_mci_by_dev(dev);
565 mutex_unlock(&mem_ctls_mutex);
566
567 return ret;
568}
569EXPORT_SYMBOL_GPL(find_mci_by_dev);
570
571/*
572 * edac_mc_workq_function
573 * performs the operation scheduled by a workq request
574 */
575static void edac_mc_workq_function(struct work_struct *work_req)
576{
577 struct delayed_work *d_work = to_delayed_work(work_req);
578 struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
579
580 mutex_lock(&mem_ctls_mutex);
581
582 if (mci->op_state != OP_RUNNING_POLL) {
583 mutex_unlock(&mem_ctls_mutex);
584 return;
585 }
586
587 if (edac_op_state == EDAC_OPSTATE_POLL)
588 mci->edac_check(mci);
589
590 mutex_unlock(&mem_ctls_mutex);
591
592 /* Queue ourselves again. */
593 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
594}
595
596/*
597 * edac_mc_reset_delay_period(unsigned long value)
598 *
599 * user space has updated our poll period value, need to
600 * reset our workq delays
601 */
602void edac_mc_reset_delay_period(unsigned long value)
603{
604 struct mem_ctl_info *mci;
605 struct list_head *item;
606
607 mutex_lock(&mem_ctls_mutex);
608
609 list_for_each(item, &mc_devices) {
610 mci = list_entry(item, struct mem_ctl_info, link);
611
612 if (mci->op_state == OP_RUNNING_POLL)
613 edac_mod_work(&mci->work, value);
614 }
615 mutex_unlock(&mem_ctls_mutex);
616}
617
618
619
620/* Return 0 on success, 1 on failure.
621 * Before calling this function, caller must
622 * assign a unique value to mci->mc_idx.
623 *
624 * locking model:
625 *
626 * called with the mem_ctls_mutex lock held
627 */
628static int add_mc_to_global_list(struct mem_ctl_info *mci)
629{
630 struct list_head *item, *insert_before;
631 struct mem_ctl_info *p;
632
633 insert_before = &mc_devices;
634
635 p = __find_mci_by_dev(mci->pdev);
636 if (unlikely(p != NULL))
637 goto fail0;
638
639 list_for_each(item, &mc_devices) {
640 p = list_entry(item, struct mem_ctl_info, link);
641
642 if (p->mc_idx >= mci->mc_idx) {
643 if (unlikely(p->mc_idx == mci->mc_idx))
644 goto fail1;
645
646 insert_before = item;
647 break;
648 }
649 }
650
651 list_add_tail_rcu(&mci->link, insert_before);
652 return 0;
653
654fail0:
655 edac_printk(KERN_WARNING, EDAC_MC,
656 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
657 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
658 return 1;
659
660fail1:
661 edac_printk(KERN_WARNING, EDAC_MC,
662 "bug in low-level driver: attempt to assign\n"
663 " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
664 return 1;
665}
666
667static int del_mc_from_global_list(struct mem_ctl_info *mci)
668{
669 list_del_rcu(&mci->link);
670
671 /* these are for safe removal of devices from global list while
672 * NMI handlers may be traversing list
673 */
674 synchronize_rcu();
675 INIT_LIST_HEAD(&mci->link);
676
677 return list_empty(&mc_devices);
678}
679
680struct mem_ctl_info *edac_mc_find(int idx)
681{
682 struct mem_ctl_info *mci = NULL;
683 struct list_head *item;
684
685 mutex_lock(&mem_ctls_mutex);
686
687 list_for_each(item, &mc_devices) {
688 mci = list_entry(item, struct mem_ctl_info, link);
689
690 if (mci->mc_idx >= idx) {
691 if (mci->mc_idx == idx) {
692 goto unlock;
693 }
694 break;
695 }
696 }
697
698unlock:
699 mutex_unlock(&mem_ctls_mutex);
700 return mci;
701}
702EXPORT_SYMBOL(edac_mc_find);
703
704const char *edac_get_owner(void)
705{
706 return edac_mc_owner;
707}
708EXPORT_SYMBOL_GPL(edac_get_owner);
709
710/* FIXME - should a warning be printed if no error detection? correction? */
711int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
712 const struct attribute_group **groups)
713{
714 int ret = -EINVAL;
715 edac_dbg(0, "\n");
716
717#ifdef CONFIG_EDAC_DEBUG
718 if (edac_debug_level >= 3)
719 edac_mc_dump_mci(mci);
720
721 if (edac_debug_level >= 4) {
722 int i;
723
724 for (i = 0; i < mci->nr_csrows; i++) {
725 struct csrow_info *csrow = mci->csrows[i];
726 u32 nr_pages = 0;
727 int j;
728
729 for (j = 0; j < csrow->nr_channels; j++)
730 nr_pages += csrow->channels[j]->dimm->nr_pages;
731 if (!nr_pages)
732 continue;
733 edac_mc_dump_csrow(csrow);
734 for (j = 0; j < csrow->nr_channels; j++)
735 if (csrow->channels[j]->dimm->nr_pages)
736 edac_mc_dump_channel(csrow->channels[j]);
737 }
738 for (i = 0; i < mci->tot_dimms; i++)
739 if (mci->dimms[i]->nr_pages)
740 edac_mc_dump_dimm(mci->dimms[i], i);
741 }
742#endif
743 mutex_lock(&mem_ctls_mutex);
744
745 if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
746 ret = -EPERM;
747 goto fail0;
748 }
749
750 if (add_mc_to_global_list(mci))
751 goto fail0;
752
753 /* set load time so that error rate can be tracked */
754 mci->start_time = jiffies;
755
756 mci->bus = edac_get_sysfs_subsys();
757
758 if (edac_create_sysfs_mci_device(mci, groups)) {
759 edac_mc_printk(mci, KERN_WARNING,
760 "failed to create sysfs device\n");
761 goto fail1;
762 }
763
764 if (mci->edac_check) {
765 mci->op_state = OP_RUNNING_POLL;
766
767 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
768 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
769
770 } else {
771 mci->op_state = OP_RUNNING_INTERRUPT;
772 }
773
774 /* Report action taken */
775 edac_mc_printk(mci, KERN_INFO,
776 "Giving out device to module %s controller %s: DEV %s (%s)\n",
777 mci->mod_name, mci->ctl_name, mci->dev_name,
778 edac_op_state_to_string(mci->op_state));
779
780 edac_mc_owner = mci->mod_name;
781
782 mutex_unlock(&mem_ctls_mutex);
783 return 0;
784
785fail1:
786 del_mc_from_global_list(mci);
787
788fail0:
789 mutex_unlock(&mem_ctls_mutex);
790 return ret;
791}
792EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
793
794struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
795{
796 struct mem_ctl_info *mci;
797
798 edac_dbg(0, "\n");
799
800 mutex_lock(&mem_ctls_mutex);
801
802 /* find the requested mci struct in the global list */
803 mci = __find_mci_by_dev(dev);
804 if (mci == NULL) {
805 mutex_unlock(&mem_ctls_mutex);
806 return NULL;
807 }
808
809 /* mark MCI offline: */
810 mci->op_state = OP_OFFLINE;
811
812 if (del_mc_from_global_list(mci))
813 edac_mc_owner = NULL;
814
815 mutex_unlock(&mem_ctls_mutex);
816
817 if (mci->edac_check)
818 edac_stop_work(&mci->work);
819
820 /* remove from sysfs */
821 edac_remove_sysfs_mci_device(mci);
822
823 edac_printk(KERN_INFO, EDAC_MC,
824 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
825 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
826
827 return mci;
828}
829EXPORT_SYMBOL_GPL(edac_mc_del_mc);
830
831static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
832 u32 size)
833{
834 struct page *pg;
835 void *virt_addr;
836 unsigned long flags = 0;
837
838 edac_dbg(3, "\n");
839
840 /* ECC error page was not in our memory. Ignore it. */
841 if (!pfn_valid(page))
842 return;
843
844 /* Find the actual page structure then map it and fix */
845 pg = pfn_to_page(page);
846
847 if (PageHighMem(pg))
848 local_irq_save(flags);
849
850 virt_addr = kmap_atomic(pg);
851
852 /* Perform architecture specific atomic scrub operation */
853 edac_atomic_scrub(virt_addr + offset, size);
854
855 /* Unmap and complete */
856 kunmap_atomic(virt_addr);
857
858 if (PageHighMem(pg))
859 local_irq_restore(flags);
860}
861
862/* FIXME - should return -1 */
863int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
864{
865 struct csrow_info **csrows = mci->csrows;
866 int row, i, j, n;
867
868 edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
869 row = -1;
870
871 for (i = 0; i < mci->nr_csrows; i++) {
872 struct csrow_info *csrow = csrows[i];
873 n = 0;
874 for (j = 0; j < csrow->nr_channels; j++) {
875 struct dimm_info *dimm = csrow->channels[j]->dimm;
876 n += dimm->nr_pages;
877 }
878 if (n == 0)
879 continue;
880
881 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
882 mci->mc_idx,
883 csrow->first_page, page, csrow->last_page,
884 csrow->page_mask);
885
886 if ((page >= csrow->first_page) &&
887 (page <= csrow->last_page) &&
888 ((page & csrow->page_mask) ==
889 (csrow->first_page & csrow->page_mask))) {
890 row = i;
891 break;
892 }
893 }
894
895 if (row == -1)
896 edac_mc_printk(mci, KERN_ERR,
897 "could not look up page error address %lx\n",
898 (unsigned long)page);
899
900 return row;
901}
902EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
903
904const char *edac_layer_name[] = {
905 [EDAC_MC_LAYER_BRANCH] = "branch",
906 [EDAC_MC_LAYER_CHANNEL] = "channel",
907 [EDAC_MC_LAYER_SLOT] = "slot",
908 [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
909 [EDAC_MC_LAYER_ALL_MEM] = "memory",
910};
911EXPORT_SYMBOL_GPL(edac_layer_name);
912
913static void edac_inc_ce_error(struct mem_ctl_info *mci,
914 bool enable_per_layer_report,
915 const int pos[EDAC_MAX_LAYERS],
916 const u16 count)
917{
918 int i, index = 0;
919
920 mci->ce_mc += count;
921
922 if (!enable_per_layer_report) {
923 mci->ce_noinfo_count += count;
924 return;
925 }
926
927 for (i = 0; i < mci->n_layers; i++) {
928 if (pos[i] < 0)
929 break;
930 index += pos[i];
931 mci->ce_per_layer[i][index] += count;
932
933 if (i < mci->n_layers - 1)
934 index *= mci->layers[i + 1].size;
935 }
936}
937
938static void edac_inc_ue_error(struct mem_ctl_info *mci,
939 bool enable_per_layer_report,
940 const int pos[EDAC_MAX_LAYERS],
941 const u16 count)
942{
943 int i, index = 0;
944
945 mci->ue_mc += count;
946
947 if (!enable_per_layer_report) {
948 mci->ue_noinfo_count += count;
949 return;
950 }
951
952 for (i = 0; i < mci->n_layers; i++) {
953 if (pos[i] < 0)
954 break;
955 index += pos[i];
956 mci->ue_per_layer[i][index] += count;
957
958 if (i < mci->n_layers - 1)
959 index *= mci->layers[i + 1].size;
960 }
961}
962
963static void edac_ce_error(struct mem_ctl_info *mci,
964 const u16 error_count,
965 const int pos[EDAC_MAX_LAYERS],
966 const char *msg,
967 const char *location,
968 const char *label,
969 const char *detail,
970 const char *other_detail,
971 const bool enable_per_layer_report,
972 const unsigned long page_frame_number,
973 const unsigned long offset_in_page,
974 long grain)
975{
976 unsigned long remapped_page;
977 char *msg_aux = "";
978
979 if (*msg)
980 msg_aux = " ";
981
982 if (edac_mc_get_log_ce()) {
983 if (other_detail && *other_detail)
984 edac_mc_printk(mci, KERN_WARNING,
985 "%d CE %s%son %s (%s %s - %s)\n",
986 error_count, msg, msg_aux, label,
987 location, detail, other_detail);
988 else
989 edac_mc_printk(mci, KERN_WARNING,
990 "%d CE %s%son %s (%s %s)\n",
991 error_count, msg, msg_aux, label,
992 location, detail);
993 }
994 edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
995
996 if (mci->scrub_mode == SCRUB_SW_SRC) {
997 /*
998 * Some memory controllers (called MCs below) can remap
999 * memory so that it is still available at a different
1000 * address when PCI devices map into memory.
1001 * MC's that can't do this, lose the memory where PCI
1002 * devices are mapped. This mapping is MC-dependent
1003 * and so we call back into the MC driver for it to
1004 * map the MC page to a physical (CPU) page which can
1005 * then be mapped to a virtual page - which can then
1006 * be scrubbed.
1007 */
1008 remapped_page = mci->ctl_page_to_phys ?
1009 mci->ctl_page_to_phys(mci, page_frame_number) :
1010 page_frame_number;
1011
1012 edac_mc_scrub_block(remapped_page,
1013 offset_in_page, grain);
1014 }
1015}
1016
1017static void edac_ue_error(struct mem_ctl_info *mci,
1018 const u16 error_count,
1019 const int pos[EDAC_MAX_LAYERS],
1020 const char *msg,
1021 const char *location,
1022 const char *label,
1023 const char *detail,
1024 const char *other_detail,
1025 const bool enable_per_layer_report)
1026{
1027 char *msg_aux = "";
1028
1029 if (*msg)
1030 msg_aux = " ";
1031
1032 if (edac_mc_get_log_ue()) {
1033 if (other_detail && *other_detail)
1034 edac_mc_printk(mci, KERN_WARNING,
1035 "%d UE %s%son %s (%s %s - %s)\n",
1036 error_count, msg, msg_aux, label,
1037 location, detail, other_detail);
1038 else
1039 edac_mc_printk(mci, KERN_WARNING,
1040 "%d UE %s%son %s (%s %s)\n",
1041 error_count, msg, msg_aux, label,
1042 location, detail);
1043 }
1044
1045 if (edac_mc_get_panic_on_ue()) {
1046 if (other_detail && *other_detail)
1047 panic("UE %s%son %s (%s%s - %s)\n",
1048 msg, msg_aux, label, location, detail, other_detail);
1049 else
1050 panic("UE %s%son %s (%s%s)\n",
1051 msg, msg_aux, label, location, detail);
1052 }
1053
1054 edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
1055}
1056
1057void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
1058 struct mem_ctl_info *mci,
1059 struct edac_raw_error_desc *e)
1060{
1061 char detail[80];
1062 int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
1063
1064 /* Memory type dependent details about the error */
1065 if (type == HW_EVENT_ERR_CORRECTED) {
1066 snprintf(detail, sizeof(detail),
1067 "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx",
1068 e->page_frame_number, e->offset_in_page,
1069 e->grain, e->syndrome);
1070 edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1071 detail, e->other_detail, e->enable_per_layer_report,
1072 e->page_frame_number, e->offset_in_page, e->grain);
1073 } else {
1074 snprintf(detail, sizeof(detail),
1075 "page:0x%lx offset:0x%lx grain:%ld",
1076 e->page_frame_number, e->offset_in_page, e->grain);
1077
1078 edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1079 detail, e->other_detail, e->enable_per_layer_report);
1080 }
1081
1082
1083}
1084EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
1085
1086void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1087 struct mem_ctl_info *mci,
1088 const u16 error_count,
1089 const unsigned long page_frame_number,
1090 const unsigned long offset_in_page,
1091 const unsigned long syndrome,
1092 const int top_layer,
1093 const int mid_layer,
1094 const int low_layer,
1095 const char *msg,
1096 const char *other_detail)
1097{
1098 char *p;
1099 int row = -1, chan = -1;
1100 int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
1101 int i, n_labels = 0;
1102 u8 grain_bits;
1103 struct edac_raw_error_desc *e = &mci->error_desc;
1104
1105 edac_dbg(3, "MC%d\n", mci->mc_idx);
1106
1107 /* Fills the error report buffer */
1108 memset(e, 0, sizeof (*e));
1109 e->error_count = error_count;
1110 e->top_layer = top_layer;
1111 e->mid_layer = mid_layer;
1112 e->low_layer = low_layer;
1113 e->page_frame_number = page_frame_number;
1114 e->offset_in_page = offset_in_page;
1115 e->syndrome = syndrome;
1116 e->msg = msg;
1117 e->other_detail = other_detail;
1118
1119 /*
1120 * Check if the event report is consistent and if the memory
1121 * location is known. If it is known, enable_per_layer_report will be
1122 * true, the DIMM(s) label info will be filled and the per-layer
1123 * error counters will be incremented.
1124 */
1125 for (i = 0; i < mci->n_layers; i++) {
1126 if (pos[i] >= (int)mci->layers[i].size) {
1127
1128 edac_mc_printk(mci, KERN_ERR,
1129 "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
1130 edac_layer_name[mci->layers[i].type],
1131 pos[i], mci->layers[i].size);
1132 /*
1133 * Instead of just returning it, let's use what's
1134 * known about the error. The increment routines and
1135 * the DIMM filter logic will do the right thing by
1136 * pointing the likely damaged DIMMs.
1137 */
1138 pos[i] = -1;
1139 }
1140 if (pos[i] >= 0)
1141 e->enable_per_layer_report = true;
1142 }
1143
1144 /*
1145 * Get the dimm label/grain that applies to the match criteria.
1146 * As the error algorithm may not be able to point to just one memory
1147 * stick, the logic here will get all possible labels that could
1148 * pottentially be affected by the error.
1149 * On FB-DIMM memory controllers, for uncorrected errors, it is common
1150 * to have only the MC channel and the MC dimm (also called "branch")
1151 * but the channel is not known, as the memory is arranged in pairs,
1152 * where each memory belongs to a separate channel within the same
1153 * branch.
1154 */
1155 p = e->label;
1156 *p = '\0';
1157
1158 for (i = 0; i < mci->tot_dimms; i++) {
1159 struct dimm_info *dimm = mci->dimms[i];
1160
1161 if (top_layer >= 0 && top_layer != dimm->location[0])
1162 continue;
1163 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1164 continue;
1165 if (low_layer >= 0 && low_layer != dimm->location[2])
1166 continue;
1167
1168 /* get the max grain, over the error match range */
1169 if (dimm->grain > e->grain)
1170 e->grain = dimm->grain;
1171
1172 /*
1173 * If the error is memory-controller wide, there's no need to
1174 * seek for the affected DIMMs because the whole
1175 * channel/memory controller/... may be affected.
1176 * Also, don't show errors for empty DIMM slots.
1177 */
1178 if (e->enable_per_layer_report && dimm->nr_pages) {
1179 if (n_labels >= EDAC_MAX_LABELS) {
1180 e->enable_per_layer_report = false;
1181 break;
1182 }
1183 n_labels++;
1184 if (p != e->label) {
1185 strcpy(p, OTHER_LABEL);
1186 p += strlen(OTHER_LABEL);
1187 }
1188 strcpy(p, dimm->label);
1189 p += strlen(p);
1190 *p = '\0';
1191
1192 /*
1193 * get csrow/channel of the DIMM, in order to allow
1194 * incrementing the compat API counters
1195 */
1196 edac_dbg(4, "%s csrows map: (%d,%d)\n",
1197 mci->csbased ? "rank" : "dimm",
1198 dimm->csrow, dimm->cschannel);
1199 if (row == -1)
1200 row = dimm->csrow;
1201 else if (row >= 0 && row != dimm->csrow)
1202 row = -2;
1203
1204 if (chan == -1)
1205 chan = dimm->cschannel;
1206 else if (chan >= 0 && chan != dimm->cschannel)
1207 chan = -2;
1208 }
1209 }
1210
1211 if (!e->enable_per_layer_report) {
1212 strcpy(e->label, "any memory");
1213 } else {
1214 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1215 if (p == e->label)
1216 strcpy(e->label, "unknown memory");
1217 if (type == HW_EVENT_ERR_CORRECTED) {
1218 if (row >= 0) {
1219 mci->csrows[row]->ce_count += error_count;
1220 if (chan >= 0)
1221 mci->csrows[row]->channels[chan]->ce_count += error_count;
1222 }
1223 } else
1224 if (row >= 0)
1225 mci->csrows[row]->ue_count += error_count;
1226 }
1227
1228 /* Fill the RAM location data */
1229 p = e->location;
1230
1231 for (i = 0; i < mci->n_layers; i++) {
1232 if (pos[i] < 0)
1233 continue;
1234
1235 p += sprintf(p, "%s:%d ",
1236 edac_layer_name[mci->layers[i].type],
1237 pos[i]);
1238 }
1239 if (p > e->location)
1240 *(p - 1) = '\0';
1241
1242 /* Report the error via the trace interface */
1243 grain_bits = fls_long(e->grain) + 1;
1244
1245 if (IS_ENABLED(CONFIG_RAS))
1246 trace_mc_event(type, e->msg, e->label, e->error_count,
1247 mci->mc_idx, e->top_layer, e->mid_layer,
1248 e->low_layer,
1249 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
1250 grain_bits, e->syndrome, e->other_detail);
1251
1252 edac_raw_mc_handle_error(type, mci, e);
1253}
1254EXPORT_SYMBOL_GPL(edac_mc_handle_error);
1255