1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * rt8973a.h |
4 | * |
5 | * Copyright (c) 2014 Samsung Electronics Co., Ltd |
6 | */ |
7 | |
8 | #ifndef __LINUX_EXTCON_RT8973A_H |
9 | #define __LINUX_EXTCON_RT8973A_H |
10 | |
11 | enum rt8973a_types { |
12 | TYPE_RT8973A, |
13 | }; |
14 | |
15 | /* RT8973A registers */ |
16 | enum rt8973A_reg { |
17 | RT8973A_REG_DEVICE_ID = 0x1, |
18 | RT8973A_REG_CONTROL1, |
19 | RT8973A_REG_INT1, |
20 | RT8973A_REG_INT2, |
21 | RT8973A_REG_INTM1, |
22 | RT8973A_REG_INTM2, |
23 | RT8973A_REG_ADC, |
24 | RT8973A_REG_RSVD_1, |
25 | RT8973A_REG_RSVD_2, |
26 | RT8973A_REG_DEV1, |
27 | RT8973A_REG_DEV2, |
28 | RT8973A_REG_RSVD_3, |
29 | RT8973A_REG_RSVD_4, |
30 | RT8973A_REG_RSVD_5, |
31 | RT8973A_REG_RSVD_6, |
32 | RT8973A_REG_RSVD_7, |
33 | RT8973A_REG_RSVD_8, |
34 | RT8973A_REG_RSVD_9, |
35 | RT8973A_REG_MANUAL_SW1, |
36 | RT8973A_REG_MANUAL_SW2, |
37 | RT8973A_REG_RSVD_10, |
38 | RT8973A_REG_RSVD_11, |
39 | RT8973A_REG_RSVD_12, |
40 | RT8973A_REG_RSVD_13, |
41 | RT8973A_REG_RSVD_14, |
42 | RT8973A_REG_RSVD_15, |
43 | RT8973A_REG_RESET, |
44 | |
45 | RT8973A_REG_END, |
46 | }; |
47 | |
48 | /* Define RT8973A MASK/SHIFT constant */ |
49 | #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0 |
50 | #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3 |
51 | #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT) |
52 | #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT) |
53 | |
54 | #define RT8973A_REG_CONTROL1_INTM_SHIFT 0 |
55 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2 |
56 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3 |
57 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4 |
58 | #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5 |
59 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6 |
60 | #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7 |
61 | #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT) |
62 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT) |
63 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT) |
64 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT) |
65 | #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT) |
66 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT) |
67 | #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT) |
68 | |
69 | #define RT9873A_REG_INTM1_ATTACH_SHIFT 0 |
70 | #define RT9873A_REG_INTM1_DETACH_SHIFT 1 |
71 | #define RT9873A_REG_INTM1_CHGDET_SHIFT 2 |
72 | #define RT9873A_REG_INTM1_DCD_T_SHIFT 3 |
73 | #define RT9873A_REG_INTM1_OVP_SHIFT 4 |
74 | #define RT9873A_REG_INTM1_CONNECT_SHIFT 5 |
75 | #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6 |
76 | #define RT9873A_REG_INTM1_OTP_SHIFT 7 |
77 | #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT) |
78 | #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT) |
79 | #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT) |
80 | #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT) |
81 | #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT) |
82 | #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT) |
83 | #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT) |
84 | #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT) |
85 | |
86 | #define RT9873A_REG_INTM2_UVLO_SHIFT 1 |
87 | #define RT9873A_REG_INTM2_POR_SHIFT 2 |
88 | #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3 |
89 | #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4 |
90 | #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5 |
91 | #define RT9873A_REG_INTM2_OCP_SHIFT 6 |
92 | #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7 |
93 | #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT) |
94 | #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT) |
95 | #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT) |
96 | #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT) |
97 | #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT) |
98 | #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT) |
99 | #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT) |
100 | |
101 | #define RT8973A_REG_ADC_SHIFT 0 |
102 | #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT) |
103 | |
104 | #define RT8973A_REG_DEV1_OTG_SHIFT 0 |
105 | #define RT8973A_REG_DEV1_SDP_SHIFT 2 |
106 | #define RT8973A_REG_DEV1_UART_SHIFT 3 |
107 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4 |
108 | #define RT8973A_REG_DEV1_CDPORT_SHIFT 5 |
109 | #define RT8973A_REG_DEV1_DCPORT_SHIFT 6 |
110 | #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT) |
111 | #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT) |
112 | #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT) |
113 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT) |
114 | #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT) |
115 | #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT) |
116 | #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \ |
117 | | RT8973A_REG_DEV1_CDPORT_MASK) |
118 | |
119 | #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0 |
120 | #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1 |
121 | #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2 |
122 | #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3 |
123 | #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT) |
124 | #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT) |
125 | #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT) |
126 | #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT) |
127 | |
128 | #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2 |
129 | #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5 |
130 | #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT) |
131 | #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT) |
132 | #define DM_DP_CON_SWITCH_OPEN 0x0 |
133 | #define DM_DP_CON_SWITCH_USB 0x1 |
134 | #define DM_DP_CON_SWITCH_UART 0x3 |
135 | #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ |
136 | | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) |
137 | #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ |
138 | | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) |
139 | #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ |
140 | | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) |
141 | |
142 | #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0 |
143 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2 |
144 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3 |
145 | #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT) |
146 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT) |
147 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT) |
148 | #define RT8973A_REG_MANUAL_SW2_FET_ON 0 |
149 | #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1 |
150 | #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0 |
151 | #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1 |
152 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0 |
153 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1 |
154 | |
155 | #define RT8973A_REG_RESET_SHIFT 0 |
156 | #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT) |
157 | #define RT8973A_REG_RESET 0x1 |
158 | |
159 | /* RT8973A Interrupts */ |
160 | enum rt8973a_irq { |
161 | /* Interrupt1*/ |
162 | RT8973A_INT1_ATTACH, |
163 | RT8973A_INT1_DETACH, |
164 | RT8973A_INT1_CHGDET, |
165 | RT8973A_INT1_DCD_T, |
166 | RT8973A_INT1_OVP, |
167 | RT8973A_INT1_CONNECT, |
168 | RT8973A_INT1_ADC_CHG, |
169 | RT8973A_INT1_OTP, |
170 | |
171 | /* Interrupt2*/ |
172 | RT8973A_INT2_UVLO, |
173 | RT8973A_INT2_POR, |
174 | RT8973A_INT2_OTP_FET, |
175 | RT8973A_INT2_OVP_FET, |
176 | RT8973A_INT2_OCP_LATCH, |
177 | RT8973A_INT2_OCP, |
178 | RT8973A_INT2_OVP_OCP, |
179 | |
180 | RT8973A_NUM, |
181 | }; |
182 | |
183 | #define RT8973A_INT1_ATTACH_MASK BIT(0) |
184 | #define RT8973A_INT1_DETACH_MASK BIT(1) |
185 | #define RT8973A_INT1_CHGDET_MASK BIT(2) |
186 | #define RT8973A_INT1_DCD_T_MASK BIT(3) |
187 | #define RT8973A_INT1_OVP_MASK BIT(4) |
188 | #define RT8973A_INT1_CONNECT_MASK BIT(5) |
189 | #define RT8973A_INT1_ADC_CHG_MASK BIT(6) |
190 | #define RT8973A_INT1_OTP_MASK BIT(7) |
191 | #define RT8973A_INT2_UVLOT_MASK BIT(0) |
192 | #define RT8973A_INT2_POR_MASK BIT(1) |
193 | #define RT8973A_INT2_OTP_FET_MASK BIT(2) |
194 | #define RT8973A_INT2_OVP_FET_MASK BIT(3) |
195 | #define RT8973A_INT2_OCP_LATCH_MASK BIT(4) |
196 | #define RT8973A_INT2_OCP_MASK BIT(5) |
197 | #define RT8973A_INT2_OVP_OCP_MASK BIT(6) |
198 | |
199 | #endif /* __LINUX_EXTCON_RT8973A_H */ |
200 | |