| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver |
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| 4 | * |
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| 5 | * Copyright (C) 2017-2018 Intel Corporation, Inc. |
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| 6 | * |
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| 7 | * Authors: |
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| 8 | * Kang Luwei <luwei.kang@intel.com> |
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| 9 | * Xiao Guangrong <guangrong.xiao@linux.intel.com> |
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| 10 | * Wu Hao <hao.wu@intel.com> |
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| 11 | * Joseph Grecco <joe.grecco@intel.com> |
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| 12 | * Enno Luebbers <enno.luebbers@intel.com> |
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| 13 | * Tim Whisonant <tim.whisonant@intel.com> |
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| 14 | * Ananda Ravuri <ananda.ravuri@intel.com> |
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| 15 | * Henry Mitchel <henry.mitchel@intel.com> |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef __DFL_FME_PR_H |
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| 19 | #define __DFL_FME_PR_H |
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| 20 | |
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| 21 | #include <linux/platform_device.h> |
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| 22 | |
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| 23 | /** |
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| 24 | * struct dfl_fme_region - FME fpga region data structure |
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| 25 | * |
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| 26 | * @region: platform device of the FPGA region. |
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| 27 | * @node: used to link fme_region to a list. |
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| 28 | * @port_id: indicate which port this region connected to. |
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| 29 | */ |
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| 30 | struct dfl_fme_region { |
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| 31 | struct platform_device *region; |
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| 32 | struct list_head node; |
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| 33 | int port_id; |
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| 34 | }; |
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| 35 | |
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| 36 | /** |
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| 37 | * struct dfl_fme_region_pdata - platform data for FME region platform device. |
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| 38 | * |
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| 39 | * @mgr: platform device of the FPGA manager. |
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| 40 | * @br: platform device of the FPGA bridge. |
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| 41 | * @region_id: region id (same as port_id). |
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| 42 | */ |
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| 43 | struct dfl_fme_region_pdata { |
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| 44 | struct platform_device *mgr; |
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| 45 | struct platform_device *br; |
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| 46 | int region_id; |
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| 47 | }; |
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| 48 | |
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| 49 | /** |
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| 50 | * struct dfl_fme_bridge - FME fpga bridge data structure |
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| 51 | * |
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| 52 | * @br: platform device of the FPGA bridge. |
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| 53 | * @node: used to link fme_bridge to a list. |
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| 54 | */ |
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| 55 | struct dfl_fme_bridge { |
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| 56 | struct platform_device *br; |
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| 57 | struct list_head node; |
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| 58 | }; |
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| 59 | |
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| 60 | /** |
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| 61 | * struct dfl_fme_br_pdata - platform data for FME bridge platform device. |
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| 62 | * |
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| 63 | * @cdev: container device. |
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| 64 | * @port_id: port id. |
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| 65 | */ |
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| 66 | struct dfl_fme_br_pdata { |
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| 67 | struct dfl_fpga_cdev *cdev; |
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| 68 | int port_id; |
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| 69 | }; |
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| 70 | |
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| 71 | /** |
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| 72 | * struct dfl_fme_mgr_pdata - platform data for FME manager platform device. |
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| 73 | * |
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| 74 | * @ioaddr: mapped io address for FME manager platform device. |
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| 75 | */ |
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| 76 | struct dfl_fme_mgr_pdata { |
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| 77 | void __iomem *ioaddr; |
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| 78 | }; |
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| 79 | |
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| 80 | #define DFL_FPGA_FME_MGR "dfl-fme-mgr" |
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| 81 | #define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge" |
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| 82 | #define DFL_FPGA_FME_REGION "dfl-fme-region" |
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| 83 | |
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| 84 | #endif /* __DFL_FME_PR_H */ |
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| 85 | |
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