1// SPDX-License-Identifier: GPL-2.0+
2
3/*
4 * GPIO driver for the AMD G series FCH (eg. GX-412TC)
5 *
6 * Copyright (C) 2018 metux IT consult
7 * Author: Enrico Weigelt, metux IT consult <info@metux.net>
8 *
9 */
10
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/gpio/driver.h>
17#include <linux/platform_data/gpio/gpio-amd-fch.h>
18#include <linux/spinlock.h>
19
20#define AMD_FCH_MMIO_BASE 0xFED80000
21#define AMD_FCH_GPIO_BANK0_BASE 0x1500
22#define AMD_FCH_GPIO_SIZE 0x0300
23
24#define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)
25#define AMD_FCH_GPIO_FLAG_WRITE BIT(22)
26#define AMD_FCH_GPIO_FLAG_READ BIT(16)
27
28static struct resource amd_fch_gpio_iores =
29 DEFINE_RES_MEM_NAMED(
30 AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,
31 AMD_FCH_GPIO_SIZE,
32 "amd-fch-gpio-iomem");
33
34struct amd_fch_gpio_priv {
35 struct platform_device *pdev;
36 struct gpio_chip gc;
37 void __iomem *base;
38 struct amd_fch_gpio_pdata *pdata;
39 spinlock_t lock;
40};
41
42static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
43 unsigned int gpio)
44{
45 return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
46}
47
48static int amd_fch_gpio_direction_input(struct gpio_chip *gc,
49 unsigned int offset)
50{
51 unsigned long flags;
52 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
53 void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
54
55 spin_lock_irqsave(&priv->lock, flags);
56 writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
57 spin_unlock_irqrestore(&priv->lock, flags);
58
59 return 0;
60}
61
62static int amd_fch_gpio_direction_output(struct gpio_chip *gc,
63 unsigned int gpio, int value)
64{
65 unsigned long flags;
66 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
67 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
68 u32 val;
69
70 spin_lock_irqsave(&priv->lock, flags);
71
72 val = readl_relaxed(ptr);
73 if (value)
74 val |= AMD_FCH_GPIO_FLAG_WRITE;
75 else
76 val &= ~AMD_FCH_GPIO_FLAG_WRITE;
77
78 writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
79
80 spin_unlock_irqrestore(&priv->lock, flags);
81
82 return 0;
83}
84
85static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
86{
87 int ret;
88 unsigned long flags;
89 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
90 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
91
92 spin_lock_irqsave(&priv->lock, flags);
93 ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
94 spin_unlock_irqrestore(&priv->lock, flags);
95
96 return ret;
97}
98
99static void amd_fch_gpio_set(struct gpio_chip *gc,
100 unsigned int gpio, int value)
101{
102 unsigned long flags;
103 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
104 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
105 u32 mask;
106
107 spin_lock_irqsave(&priv->lock, flags);
108
109 mask = readl_relaxed(ptr);
110 if (value)
111 mask |= AMD_FCH_GPIO_FLAG_WRITE;
112 else
113 mask &= ~AMD_FCH_GPIO_FLAG_WRITE;
114 writel_relaxed(mask, ptr);
115
116 spin_unlock_irqrestore(&priv->lock, flags);
117}
118
119static int amd_fch_gpio_get(struct gpio_chip *gc,
120 unsigned int offset)
121{
122 unsigned long flags;
123 int ret;
124 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
125 void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
126
127 spin_lock_irqsave(&priv->lock, flags);
128 ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);
129 spin_unlock_irqrestore(&priv->lock, flags);
130
131 return ret;
132}
133
134static int amd_fch_gpio_request(struct gpio_chip *chip,
135 unsigned int gpio_pin)
136{
137 return 0;
138}
139
140static int amd_fch_gpio_probe(struct platform_device *pdev)
141{
142 struct amd_fch_gpio_priv *priv;
143 struct amd_fch_gpio_pdata *pdata;
144
145 pdata = dev_get_platdata(&pdev->dev);
146 if (!pdata) {
147 dev_err(&pdev->dev, "no platform_data\n");
148 return -ENOENT;
149 }
150
151 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
152 if (!priv)
153 return -ENOMEM;
154
155 priv->pdata = pdata;
156 priv->pdev = pdev;
157
158 priv->gc.owner = THIS_MODULE;
159 priv->gc.parent = &pdev->dev;
160 priv->gc.label = dev_name(&pdev->dev);
161 priv->gc.ngpio = priv->pdata->gpio_num;
162 priv->gc.names = priv->pdata->gpio_names;
163 priv->gc.base = -1;
164 priv->gc.request = amd_fch_gpio_request;
165 priv->gc.direction_input = amd_fch_gpio_direction_input;
166 priv->gc.direction_output = amd_fch_gpio_direction_output;
167 priv->gc.get_direction = amd_fch_gpio_get_direction;
168 priv->gc.get = amd_fch_gpio_get;
169 priv->gc.set = amd_fch_gpio_set;
170
171 spin_lock_init(&priv->lock);
172
173 priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores);
174 if (IS_ERR(priv->base))
175 return PTR_ERR(priv->base);
176
177 platform_set_drvdata(pdev, priv);
178
179 return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
180}
181
182static struct platform_driver amd_fch_gpio_driver = {
183 .driver = {
184 .name = AMD_FCH_GPIO_DRIVER_NAME,
185 },
186 .probe = amd_fch_gpio_probe,
187};
188
189module_platform_driver(amd_fch_gpio_driver);
190
191MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
192MODULE_DESCRIPTION("AMD G-series FCH GPIO driver");
193MODULE_LICENSE("GPL");
194MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME);
195