1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Atheros AR71XX/AR724X/AR913X GPIO API support |
4 | * |
5 | * Copyright (C) 2015 Alban Bedel <albeu@free.fr> |
6 | * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> |
7 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
8 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
9 | */ |
10 | |
11 | #include <linux/gpio/driver.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/platform_data/gpio-ath79.h> |
14 | #include <linux/of.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/module.h> |
17 | #include <linux/irq.h> |
18 | |
19 | #define AR71XX_GPIO_REG_OE 0x00 |
20 | #define AR71XX_GPIO_REG_IN 0x04 |
21 | #define AR71XX_GPIO_REG_SET 0x0c |
22 | #define AR71XX_GPIO_REG_CLEAR 0x10 |
23 | |
24 | #define AR71XX_GPIO_REG_INT_ENABLE 0x14 |
25 | #define AR71XX_GPIO_REG_INT_TYPE 0x18 |
26 | #define AR71XX_GPIO_REG_INT_POLARITY 0x1c |
27 | #define AR71XX_GPIO_REG_INT_PENDING 0x20 |
28 | #define AR71XX_GPIO_REG_INT_MASK 0x24 |
29 | |
30 | struct ath79_gpio_ctrl { |
31 | struct gpio_chip gc; |
32 | void __iomem *base; |
33 | raw_spinlock_t lock; |
34 | unsigned long both_edges; |
35 | }; |
36 | |
37 | static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) |
38 | { |
39 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data); |
40 | |
41 | return container_of(gc, struct ath79_gpio_ctrl, gc); |
42 | } |
43 | |
44 | static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) |
45 | { |
46 | return readl(addr: ctrl->base + reg); |
47 | } |
48 | |
49 | static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, |
50 | unsigned reg, u32 val) |
51 | { |
52 | writel(val, addr: ctrl->base + reg); |
53 | } |
54 | |
55 | static bool ath79_gpio_update_bits( |
56 | struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) |
57 | { |
58 | u32 old_val, new_val; |
59 | |
60 | old_val = ath79_gpio_read(ctrl, reg); |
61 | new_val = (old_val & ~mask) | (bits & mask); |
62 | |
63 | if (new_val != old_val) |
64 | ath79_gpio_write(ctrl, reg, val: new_val); |
65 | |
66 | return new_val != old_val; |
67 | } |
68 | |
69 | static void ath79_gpio_irq_unmask(struct irq_data *data) |
70 | { |
71 | struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); |
72 | u32 mask = BIT(irqd_to_hwirq(data)); |
73 | unsigned long flags; |
74 | |
75 | gpiochip_enable_irq(gc: &ctrl->gc, offset: irqd_to_hwirq(d: data)); |
76 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
77 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, bits: mask); |
78 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
79 | } |
80 | |
81 | static void ath79_gpio_irq_mask(struct irq_data *data) |
82 | { |
83 | struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); |
84 | u32 mask = BIT(irqd_to_hwirq(data)); |
85 | unsigned long flags; |
86 | |
87 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
88 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, bits: 0); |
89 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
90 | gpiochip_disable_irq(gc: &ctrl->gc, offset: irqd_to_hwirq(d: data)); |
91 | } |
92 | |
93 | static void ath79_gpio_irq_enable(struct irq_data *data) |
94 | { |
95 | struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); |
96 | u32 mask = BIT(irqd_to_hwirq(data)); |
97 | unsigned long flags; |
98 | |
99 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
100 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, bits: mask); |
101 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, bits: mask); |
102 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
103 | } |
104 | |
105 | static void ath79_gpio_irq_disable(struct irq_data *data) |
106 | { |
107 | struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); |
108 | u32 mask = BIT(irqd_to_hwirq(data)); |
109 | unsigned long flags; |
110 | |
111 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
112 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, bits: 0); |
113 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, bits: 0); |
114 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
115 | } |
116 | |
117 | static int ath79_gpio_irq_set_type(struct irq_data *data, |
118 | unsigned int flow_type) |
119 | { |
120 | struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); |
121 | u32 mask = BIT(irqd_to_hwirq(data)); |
122 | u32 type = 0, polarity = 0; |
123 | unsigned long flags; |
124 | bool disabled; |
125 | |
126 | switch (flow_type) { |
127 | case IRQ_TYPE_EDGE_RISING: |
128 | polarity |= mask; |
129 | fallthrough; |
130 | case IRQ_TYPE_EDGE_FALLING: |
131 | case IRQ_TYPE_EDGE_BOTH: |
132 | break; |
133 | |
134 | case IRQ_TYPE_LEVEL_HIGH: |
135 | polarity |= mask; |
136 | fallthrough; |
137 | case IRQ_TYPE_LEVEL_LOW: |
138 | type |= mask; |
139 | break; |
140 | |
141 | default: |
142 | return -EINVAL; |
143 | } |
144 | |
145 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
146 | |
147 | if (flow_type == IRQ_TYPE_EDGE_BOTH) { |
148 | ctrl->both_edges |= mask; |
149 | polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); |
150 | } else { |
151 | ctrl->both_edges &= ~mask; |
152 | } |
153 | |
154 | /* As the IRQ configuration can't be loaded atomically we |
155 | * have to disable the interrupt while the configuration state |
156 | * is invalid. |
157 | */ |
158 | disabled = ath79_gpio_update_bits( |
159 | ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, bits: 0); |
160 | |
161 | ath79_gpio_update_bits( |
162 | ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, bits: type); |
163 | ath79_gpio_update_bits( |
164 | ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, bits: polarity); |
165 | |
166 | if (disabled) |
167 | ath79_gpio_update_bits( |
168 | ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, bits: mask); |
169 | |
170 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
171 | |
172 | return 0; |
173 | } |
174 | |
175 | static const struct irq_chip ath79_gpio_irqchip = { |
176 | .name = "gpio-ath79" , |
177 | .irq_enable = ath79_gpio_irq_enable, |
178 | .irq_disable = ath79_gpio_irq_disable, |
179 | .irq_mask = ath79_gpio_irq_mask, |
180 | .irq_unmask = ath79_gpio_irq_unmask, |
181 | .irq_set_type = ath79_gpio_irq_set_type, |
182 | .flags = IRQCHIP_IMMUTABLE, |
183 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
184 | }; |
185 | |
186 | static void ath79_gpio_irq_handler(struct irq_desc *desc) |
187 | { |
188 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
189 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
190 | struct ath79_gpio_ctrl *ctrl = |
191 | container_of(gc, struct ath79_gpio_ctrl, gc); |
192 | unsigned long flags, pending; |
193 | u32 both_edges, state; |
194 | int irq; |
195 | |
196 | chained_irq_enter(chip: irqchip, desc); |
197 | |
198 | raw_spin_lock_irqsave(&ctrl->lock, flags); |
199 | |
200 | pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); |
201 | |
202 | /* Update the polarity of the both edges irqs */ |
203 | both_edges = ctrl->both_edges & pending; |
204 | if (both_edges) { |
205 | state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); |
206 | ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, |
207 | mask: both_edges, bits: ~state); |
208 | } |
209 | |
210 | raw_spin_unlock_irqrestore(&ctrl->lock, flags); |
211 | |
212 | for_each_set_bit(irq, &pending, gc->ngpio) |
213 | generic_handle_domain_irq(domain: gc->irq.domain, hwirq: irq); |
214 | |
215 | chained_irq_exit(chip: irqchip, desc); |
216 | } |
217 | |
218 | static const struct of_device_id ath79_gpio_of_match[] = { |
219 | { .compatible = "qca,ar7100-gpio" }, |
220 | { .compatible = "qca,ar9340-gpio" }, |
221 | {}, |
222 | }; |
223 | MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); |
224 | |
225 | static int ath79_gpio_probe(struct platform_device *pdev) |
226 | { |
227 | struct ath79_gpio_platform_data *pdata = dev_get_platdata(dev: &pdev->dev); |
228 | struct device *dev = &pdev->dev; |
229 | struct device_node *np = dev->of_node; |
230 | struct ath79_gpio_ctrl *ctrl; |
231 | struct gpio_irq_chip *girq; |
232 | u32 ath79_gpio_count; |
233 | bool oe_inverted; |
234 | int err; |
235 | |
236 | ctrl = devm_kzalloc(dev, size: sizeof(*ctrl), GFP_KERNEL); |
237 | if (!ctrl) |
238 | return -ENOMEM; |
239 | |
240 | if (np) { |
241 | err = of_property_read_u32(np, propname: "ngpios" , out_value: &ath79_gpio_count); |
242 | if (err) { |
243 | dev_err(dev, "ngpios property is not valid\n" ); |
244 | return err; |
245 | } |
246 | oe_inverted = of_device_is_compatible(device: np, "qca,ar9340-gpio" ); |
247 | } else if (pdata) { |
248 | ath79_gpio_count = pdata->ngpios; |
249 | oe_inverted = pdata->oe_inverted; |
250 | } else { |
251 | dev_err(dev, "No DT node or platform data found\n" ); |
252 | return -EINVAL; |
253 | } |
254 | |
255 | if (ath79_gpio_count >= 32) { |
256 | dev_err(dev, "ngpios must be less than 32\n" ); |
257 | return -EINVAL; |
258 | } |
259 | |
260 | ctrl->base = devm_platform_ioremap_resource(pdev, index: 0); |
261 | if (IS_ERR(ptr: ctrl->base)) |
262 | return PTR_ERR(ptr: ctrl->base); |
263 | |
264 | raw_spin_lock_init(&ctrl->lock); |
265 | err = bgpio_init(gc: &ctrl->gc, dev, sz: 4, |
266 | dat: ctrl->base + AR71XX_GPIO_REG_IN, |
267 | set: ctrl->base + AR71XX_GPIO_REG_SET, |
268 | clr: ctrl->base + AR71XX_GPIO_REG_CLEAR, |
269 | dirout: oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, |
270 | dirin: oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, |
271 | flags: 0); |
272 | if (err) { |
273 | dev_err(dev, "bgpio_init failed\n" ); |
274 | return err; |
275 | } |
276 | /* Use base 0 to stay compatible with legacy platforms */ |
277 | ctrl->gc.base = 0; |
278 | |
279 | /* Optional interrupt setup */ |
280 | if (!np || of_property_read_bool(np, propname: "interrupt-controller" )) { |
281 | girq = &ctrl->gc.irq; |
282 | gpio_irq_chip_set_chip(girq, chip: &ath79_gpio_irqchip); |
283 | girq->parent_handler = ath79_gpio_irq_handler; |
284 | girq->num_parents = 1; |
285 | girq->parents = devm_kcalloc(dev, n: 1, size: sizeof(*girq->parents), |
286 | GFP_KERNEL); |
287 | if (!girq->parents) |
288 | return -ENOMEM; |
289 | girq->parents[0] = platform_get_irq(pdev, 0); |
290 | girq->default_type = IRQ_TYPE_NONE; |
291 | girq->handler = handle_simple_irq; |
292 | } |
293 | |
294 | return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); |
295 | } |
296 | |
297 | static struct platform_driver ath79_gpio_driver = { |
298 | .driver = { |
299 | .name = "ath79-gpio" , |
300 | .of_match_table = ath79_gpio_of_match, |
301 | }, |
302 | .probe = ath79_gpio_probe, |
303 | }; |
304 | |
305 | module_platform_driver(ath79_gpio_driver); |
306 | |
307 | MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support" ); |
308 | MODULE_LICENSE("GPL v2" ); |
309 | |