1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7#include <linux/bitops.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15
16/* EIC registers definition */
17#define SPRD_EIC_DBNC_DATA 0x0
18#define SPRD_EIC_DBNC_DMSK 0x4
19#define SPRD_EIC_DBNC_IEV 0x14
20#define SPRD_EIC_DBNC_IE 0x18
21#define SPRD_EIC_DBNC_RIS 0x1c
22#define SPRD_EIC_DBNC_MIS 0x20
23#define SPRD_EIC_DBNC_IC 0x24
24#define SPRD_EIC_DBNC_TRIG 0x28
25#define SPRD_EIC_DBNC_CTRL0 0x40
26
27#define SPRD_EIC_LATCH_INTEN 0x0
28#define SPRD_EIC_LATCH_INTRAW 0x4
29#define SPRD_EIC_LATCH_INTMSK 0x8
30#define SPRD_EIC_LATCH_INTCLR 0xc
31#define SPRD_EIC_LATCH_INTPOL 0x10
32#define SPRD_EIC_LATCH_INTMODE 0x14
33
34#define SPRD_EIC_ASYNC_INTIE 0x0
35#define SPRD_EIC_ASYNC_INTRAW 0x4
36#define SPRD_EIC_ASYNC_INTMSK 0x8
37#define SPRD_EIC_ASYNC_INTCLR 0xc
38#define SPRD_EIC_ASYNC_INTMODE 0x10
39#define SPRD_EIC_ASYNC_INTBOTH 0x14
40#define SPRD_EIC_ASYNC_INTPOL 0x18
41#define SPRD_EIC_ASYNC_DATA 0x1c
42
43#define SPRD_EIC_SYNC_INTIE 0x0
44#define SPRD_EIC_SYNC_INTRAW 0x4
45#define SPRD_EIC_SYNC_INTMSK 0x8
46#define SPRD_EIC_SYNC_INTCLR 0xc
47#define SPRD_EIC_SYNC_INTMODE 0x10
48#define SPRD_EIC_SYNC_INTBOTH 0x14
49#define SPRD_EIC_SYNC_INTPOL 0x18
50#define SPRD_EIC_SYNC_DATA 0x1c
51
52/*
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
54 * contains 8 EICs.
55 */
56#define SPRD_EIC_MAX_BANK 3
57#define SPRD_EIC_PER_BANK_NR 8
58#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
59#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
60#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
61
62/*
63 * The Spreadtrum EIC (external interrupt controller) can be used only in
64 * input mode to generate interrupts if detecting input signals.
65 *
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
68 *
69 * The debounce EIC is used to capture the input signals' stable status
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
72 * The debounce range is from 1ms to 4s with a step size of 1ms.
73 *
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
76 * to capture signals.
77 *
78 * The async EIC uses a 32k clock to capture the short signals (microsecond
79 * resolution) to generate interrupts by level or edge trigger.
80 *
81 * The EIC-sync is similar with GPIO's input function, which is a synchronized
82 * signal input register.
83 */
84enum sprd_eic_type {
85 SPRD_EIC_DEBOUNCE,
86 SPRD_EIC_LATCH,
87 SPRD_EIC_ASYNC,
88 SPRD_EIC_SYNC,
89 SPRD_EIC_MAX,
90};
91
92struct sprd_eic {
93 struct gpio_chip chip;
94 struct irq_chip intc;
95 void __iomem *base[SPRD_EIC_MAX_BANK];
96 enum sprd_eic_type type;
97 spinlock_t lock;
98 int irq;
99};
100
101struct sprd_eic_variant_data {
102 enum sprd_eic_type type;
103 u32 num_eics;
104};
105
106static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
107 "eic-debounce", "eic-latch", "eic-async",
108 "eic-sync",
109};
110
111static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
112 .type = SPRD_EIC_DEBOUNCE,
113 .num_eics = 8,
114};
115
116static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
117 .type = SPRD_EIC_LATCH,
118 .num_eics = 8,
119};
120
121static const struct sprd_eic_variant_data sc9860_eic_async_data = {
122 .type = SPRD_EIC_ASYNC,
123 .num_eics = 8,
124};
125
126static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
127 .type = SPRD_EIC_SYNC,
128 .num_eics = 8,
129};
130
131static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
132 unsigned int bank)
133{
134 if (bank >= SPRD_EIC_MAX_BANK)
135 return NULL;
136
137 return sprd_eic->base[bank];
138}
139
140static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
141 u16 reg, unsigned int val)
142{
143 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
144 void __iomem *base =
145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
146 unsigned long flags;
147 u32 tmp;
148
149 spin_lock_irqsave(&sprd_eic->lock, flags);
150 tmp = readl_relaxed(base + reg);
151
152 if (val)
153 tmp |= BIT(SPRD_EIC_BIT(offset));
154 else
155 tmp &= ~BIT(SPRD_EIC_BIT(offset));
156
157 writel_relaxed(tmp, base + reg);
158 spin_unlock_irqrestore(&sprd_eic->lock, flags);
159}
160
161static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
162{
163 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
164 void __iomem *base =
165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
166
167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
168}
169
170static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
171{
172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
173 return 0;
174}
175
176static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
177{
178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
179}
180
181static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
182{
183 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
184
185 switch (sprd_eic->type) {
186 case SPRD_EIC_DEBOUNCE:
187 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
188 case SPRD_EIC_ASYNC:
189 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
190 case SPRD_EIC_SYNC:
191 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
192 default:
193 return -ENOTSUPP;
194 }
195}
196
197static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
198{
199 /* EICs are always input, nothing need to do here. */
200 return 0;
201}
202
203static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
204{
205 /* EICs are always input, nothing need to do here. */
206}
207
208static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
209 unsigned int debounce)
210{
211 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
212 void __iomem *base =
213 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
214 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
215 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
216
217 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
218 writel_relaxed(value, base + reg);
219
220 return 0;
221}
222
223static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
224 unsigned long config)
225{
226 unsigned long param = pinconf_to_config_param(config);
227 u32 arg = pinconf_to_config_argument(config);
228
229 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
230 return sprd_eic_set_debounce(chip, offset, arg);
231
232 return -ENOTSUPP;
233}
234
235static void sprd_eic_irq_mask(struct irq_data *data)
236{
237 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
238 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
239 u32 offset = irqd_to_hwirq(data);
240
241 switch (sprd_eic->type) {
242 case SPRD_EIC_DEBOUNCE:
243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
244 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
245 break;
246 case SPRD_EIC_LATCH:
247 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
248 break;
249 case SPRD_EIC_ASYNC:
250 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
251 break;
252 case SPRD_EIC_SYNC:
253 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
254 break;
255 default:
256 dev_err(chip->parent, "Unsupported EIC type.\n");
257 }
258}
259
260static void sprd_eic_irq_unmask(struct irq_data *data)
261{
262 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
263 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
264 u32 offset = irqd_to_hwirq(data);
265
266 switch (sprd_eic->type) {
267 case SPRD_EIC_DEBOUNCE:
268 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
269 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
270 break;
271 case SPRD_EIC_LATCH:
272 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
273 break;
274 case SPRD_EIC_ASYNC:
275 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
276 break;
277 case SPRD_EIC_SYNC:
278 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
279 break;
280 default:
281 dev_err(chip->parent, "Unsupported EIC type.\n");
282 }
283}
284
285static void sprd_eic_irq_ack(struct irq_data *data)
286{
287 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
288 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
289 u32 offset = irqd_to_hwirq(data);
290
291 switch (sprd_eic->type) {
292 case SPRD_EIC_DEBOUNCE:
293 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
294 break;
295 case SPRD_EIC_LATCH:
296 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
297 break;
298 case SPRD_EIC_ASYNC:
299 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
300 break;
301 case SPRD_EIC_SYNC:
302 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
303 break;
304 default:
305 dev_err(chip->parent, "Unsupported EIC type.\n");
306 }
307}
308
309static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
310{
311 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
312 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
313 u32 offset = irqd_to_hwirq(data);
314 int state;
315
316 switch (sprd_eic->type) {
317 case SPRD_EIC_DEBOUNCE:
318 switch (flow_type) {
319 case IRQ_TYPE_LEVEL_HIGH:
320 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
321 break;
322 case IRQ_TYPE_LEVEL_LOW:
323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
324 break;
325 case IRQ_TYPE_EDGE_RISING:
326 case IRQ_TYPE_EDGE_FALLING:
327 case IRQ_TYPE_EDGE_BOTH:
328 state = sprd_eic_get(chip, offset);
329 if (state)
330 sprd_eic_update(chip, offset,
331 SPRD_EIC_DBNC_IEV, 0);
332 else
333 sprd_eic_update(chip, offset,
334 SPRD_EIC_DBNC_IEV, 1);
335 break;
336 default:
337 return -ENOTSUPP;
338 }
339
340 irq_set_handler_locked(data, handle_level_irq);
341 break;
342 case SPRD_EIC_LATCH:
343 switch (flow_type) {
344 case IRQ_TYPE_LEVEL_HIGH:
345 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
346 break;
347 case IRQ_TYPE_LEVEL_LOW:
348 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
349 break;
350 case IRQ_TYPE_EDGE_RISING:
351 case IRQ_TYPE_EDGE_FALLING:
352 case IRQ_TYPE_EDGE_BOTH:
353 state = sprd_eic_get(chip, offset);
354 if (state)
355 sprd_eic_update(chip, offset,
356 SPRD_EIC_LATCH_INTPOL, 0);
357 else
358 sprd_eic_update(chip, offset,
359 SPRD_EIC_LATCH_INTPOL, 1);
360 break;
361 default:
362 return -ENOTSUPP;
363 }
364
365 irq_set_handler_locked(data, handle_level_irq);
366 break;
367 case SPRD_EIC_ASYNC:
368 switch (flow_type) {
369 case IRQ_TYPE_EDGE_RISING:
370 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
371 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
372 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
373 irq_set_handler_locked(data, handle_edge_irq);
374 break;
375 case IRQ_TYPE_EDGE_FALLING:
376 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
377 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
378 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
379 irq_set_handler_locked(data, handle_edge_irq);
380 break;
381 case IRQ_TYPE_EDGE_BOTH:
382 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
383 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
384 irq_set_handler_locked(data, handle_edge_irq);
385 break;
386 case IRQ_TYPE_LEVEL_HIGH:
387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
390 irq_set_handler_locked(data, handle_level_irq);
391 break;
392 case IRQ_TYPE_LEVEL_LOW:
393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
396 irq_set_handler_locked(data, handle_level_irq);
397 break;
398 default:
399 return -ENOTSUPP;
400 }
401 break;
402 case SPRD_EIC_SYNC:
403 switch (flow_type) {
404 case IRQ_TYPE_EDGE_RISING:
405 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
406 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
407 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
408 irq_set_handler_locked(data, handle_edge_irq);
409 break;
410 case IRQ_TYPE_EDGE_FALLING:
411 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
412 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
413 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
414 irq_set_handler_locked(data, handle_edge_irq);
415 break;
416 case IRQ_TYPE_EDGE_BOTH:
417 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
418 irq_set_handler_locked(data, handle_edge_irq);
419 break;
420 case IRQ_TYPE_LEVEL_HIGH:
421 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
422 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
423 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
424 irq_set_handler_locked(data, handle_level_irq);
425 break;
426 case IRQ_TYPE_LEVEL_LOW:
427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
428 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
430 irq_set_handler_locked(data, handle_level_irq);
431 break;
432 default:
433 return -ENOTSUPP;
434 }
435 break;
436 default:
437 dev_err(chip->parent, "Unsupported EIC type.\n");
438 return -ENOTSUPP;
439 }
440
441 return 0;
442}
443
444static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
445 unsigned int offset)
446{
447 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
448 struct irq_data *data = irq_get_irq_data(irq);
449 u32 trigger = irqd_get_trigger_type(data);
450 int state, post_state;
451
452 /*
453 * The debounce EIC and latch EIC can only support level trigger, so we
454 * can toggle the level trigger to emulate the edge trigger.
455 */
456 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
457 sprd_eic->type != SPRD_EIC_LATCH) ||
458 !(trigger & IRQ_TYPE_EDGE_BOTH))
459 return;
460
461 sprd_eic_irq_mask(data);
462 state = sprd_eic_get(chip, offset);
463
464retry:
465 switch (sprd_eic->type) {
466 case SPRD_EIC_DEBOUNCE:
467 if (state)
468 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
469 else
470 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
471 break;
472 case SPRD_EIC_LATCH:
473 if (state)
474 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
475 else
476 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
477 break;
478 default:
479 sprd_eic_irq_unmask(data);
480 return;
481 }
482
483 post_state = sprd_eic_get(chip, offset);
484 if (state != post_state) {
485 dev_warn(chip->parent, "EIC level was changed.\n");
486 state = post_state;
487 goto retry;
488 }
489
490 sprd_eic_irq_unmask(data);
491}
492
493static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
494{
495 enum sprd_eic_type type = *(enum sprd_eic_type *)data;
496
497 return !strcmp(chip->label, sprd_eic_label_name[type]);
498}
499
500static void sprd_eic_handle_one_type(struct gpio_chip *chip)
501{
502 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
503 u32 bank, n, girq;
504
505 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
506 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
507 unsigned long reg;
508
509 switch (sprd_eic->type) {
510 case SPRD_EIC_DEBOUNCE:
511 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
512 SPRD_EIC_DATA_MASK;
513 break;
514 case SPRD_EIC_LATCH:
515 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
516 SPRD_EIC_DATA_MASK;
517 break;
518 case SPRD_EIC_ASYNC:
519 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
520 SPRD_EIC_DATA_MASK;
521 break;
522 case SPRD_EIC_SYNC:
523 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
524 SPRD_EIC_DATA_MASK;
525 break;
526 default:
527 dev_err(chip->parent, "Unsupported EIC type.\n");
528 return;
529 }
530
531 for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
532 girq = irq_find_mapping(chip->irq.domain,
533 bank * SPRD_EIC_PER_BANK_NR + n);
534
535 generic_handle_irq(girq);
536 sprd_eic_toggle_trigger(chip, girq, n);
537 }
538 }
539}
540
541static void sprd_eic_irq_handler(struct irq_desc *desc)
542{
543 struct irq_chip *ic = irq_desc_get_chip(desc);
544 struct gpio_chip *chip;
545 enum sprd_eic_type type;
546
547 chained_irq_enter(ic, desc);
548
549 /*
550 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
551 * and sync) share one same interrupt line, we should iterate each
552 * EIC module to check if there are EIC interrupts were triggered.
553 */
554 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
555 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
556 if (!chip)
557 continue;
558
559 sprd_eic_handle_one_type(chip);
560 }
561
562 chained_irq_exit(ic, desc);
563}
564
565static int sprd_eic_probe(struct platform_device *pdev)
566{
567 const struct sprd_eic_variant_data *pdata;
568 struct gpio_irq_chip *irq;
569 struct sprd_eic *sprd_eic;
570 struct resource *res;
571 int ret, i;
572
573 pdata = of_device_get_match_data(&pdev->dev);
574 if (!pdata) {
575 dev_err(&pdev->dev, "No matching driver data found.\n");
576 return -EINVAL;
577 }
578
579 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
580 if (!sprd_eic)
581 return -ENOMEM;
582
583 spin_lock_init(&sprd_eic->lock);
584 sprd_eic->type = pdata->type;
585
586 sprd_eic->irq = platform_get_irq(pdev, 0);
587 if (sprd_eic->irq < 0) {
588 dev_err(&pdev->dev, "Failed to get EIC interrupt.\n");
589 return sprd_eic->irq;
590 }
591
592 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
593 /*
594 * We can have maximum 3 banks EICs, and each EIC has
595 * its own base address. But some platform maybe only
596 * have one bank EIC, thus base[1] and base[2] can be
597 * optional.
598 */
599 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
600 if (!res)
601 continue;
602
603 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
604 if (IS_ERR(sprd_eic->base[i]))
605 return PTR_ERR(sprd_eic->base[i]);
606 }
607
608 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
609 sprd_eic->chip.ngpio = pdata->num_eics;
610 sprd_eic->chip.base = -1;
611 sprd_eic->chip.parent = &pdev->dev;
612 sprd_eic->chip.of_node = pdev->dev.of_node;
613 sprd_eic->chip.direction_input = sprd_eic_direction_input;
614 switch (sprd_eic->type) {
615 case SPRD_EIC_DEBOUNCE:
616 sprd_eic->chip.request = sprd_eic_request;
617 sprd_eic->chip.free = sprd_eic_free;
618 sprd_eic->chip.set_config = sprd_eic_set_config;
619 sprd_eic->chip.set = sprd_eic_set;
620 /* fall-through */
621 case SPRD_EIC_ASYNC:
622 /* fall-through */
623 case SPRD_EIC_SYNC:
624 sprd_eic->chip.get = sprd_eic_get;
625 break;
626 case SPRD_EIC_LATCH:
627 /* fall-through */
628 default:
629 break;
630 }
631
632 sprd_eic->intc.name = dev_name(&pdev->dev);
633 sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
634 sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
635 sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
636 sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
637 sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
638
639 irq = &sprd_eic->chip.irq;
640 irq->chip = &sprd_eic->intc;
641 irq->handler = handle_bad_irq;
642 irq->default_type = IRQ_TYPE_NONE;
643 irq->parent_handler = sprd_eic_irq_handler;
644 irq->parent_handler_data = sprd_eic;
645 irq->num_parents = 1;
646 irq->parents = &sprd_eic->irq;
647
648 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
649 if (ret < 0) {
650 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
651 return ret;
652 }
653
654 platform_set_drvdata(pdev, sprd_eic);
655 return 0;
656}
657
658static const struct of_device_id sprd_eic_of_match[] = {
659 {
660 .compatible = "sprd,sc9860-eic-debounce",
661 .data = &sc9860_eic_dbnc_data,
662 },
663 {
664 .compatible = "sprd,sc9860-eic-latch",
665 .data = &sc9860_eic_latch_data,
666 },
667 {
668 .compatible = "sprd,sc9860-eic-async",
669 .data = &sc9860_eic_async_data,
670 },
671 {
672 .compatible = "sprd,sc9860-eic-sync",
673 .data = &sc9860_eic_sync_data,
674 },
675 {
676 /* end of list */
677 }
678};
679MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
680
681static struct platform_driver sprd_eic_driver = {
682 .probe = sprd_eic_probe,
683 .driver = {
684 .name = "sprd-eic",
685 .of_match_table = sprd_eic_of_match,
686 },
687};
688
689module_platform_driver(sprd_eic_driver);
690
691MODULE_DESCRIPTION("Spreadtrum EIC driver");
692MODULE_LICENSE("GPL v2");
693