1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7#include <linux/bitops.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/notifier.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/spinlock.h>
16
17/* EIC registers definition */
18#define SPRD_EIC_DBNC_DATA 0x0
19#define SPRD_EIC_DBNC_DMSK 0x4
20#define SPRD_EIC_DBNC_IEV 0x14
21#define SPRD_EIC_DBNC_IE 0x18
22#define SPRD_EIC_DBNC_RIS 0x1c
23#define SPRD_EIC_DBNC_MIS 0x20
24#define SPRD_EIC_DBNC_IC 0x24
25#define SPRD_EIC_DBNC_TRIG 0x28
26#define SPRD_EIC_DBNC_CTRL0 0x40
27
28#define SPRD_EIC_LATCH_INTEN 0x0
29#define SPRD_EIC_LATCH_INTRAW 0x4
30#define SPRD_EIC_LATCH_INTMSK 0x8
31#define SPRD_EIC_LATCH_INTCLR 0xc
32#define SPRD_EIC_LATCH_INTPOL 0x10
33#define SPRD_EIC_LATCH_INTMODE 0x14
34
35#define SPRD_EIC_ASYNC_INTIE 0x0
36#define SPRD_EIC_ASYNC_INTRAW 0x4
37#define SPRD_EIC_ASYNC_INTMSK 0x8
38#define SPRD_EIC_ASYNC_INTCLR 0xc
39#define SPRD_EIC_ASYNC_INTMODE 0x10
40#define SPRD_EIC_ASYNC_INTBOTH 0x14
41#define SPRD_EIC_ASYNC_INTPOL 0x18
42#define SPRD_EIC_ASYNC_DATA 0x1c
43
44#define SPRD_EIC_SYNC_INTIE 0x0
45#define SPRD_EIC_SYNC_INTRAW 0x4
46#define SPRD_EIC_SYNC_INTMSK 0x8
47#define SPRD_EIC_SYNC_INTCLR 0xc
48#define SPRD_EIC_SYNC_INTMODE 0x10
49#define SPRD_EIC_SYNC_INTBOTH 0x14
50#define SPRD_EIC_SYNC_INTPOL 0x18
51#define SPRD_EIC_SYNC_DATA 0x1c
52
53/*
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
55 * contains 8 EICs.
56 */
57#define SPRD_EIC_MAX_BANK 3
58#define SPRD_EIC_PER_BANK_NR 8
59#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
60#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
61#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
62
63/*
64 * The Spreadtrum EIC (external interrupt controller) can be used only in
65 * input mode to generate interrupts if detecting input signals.
66 *
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
69 *
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
73 * The debounce range is from 1ms to 4s with a step size of 1ms.
74 *
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
77 * to capture signals.
78 *
79 * The async EIC uses a 32k clock to capture the short signals (microsecond
80 * resolution) to generate interrupts by level or edge trigger.
81 *
82 * The EIC-sync is similar with GPIO's input function, which is a synchronized
83 * signal input register.
84 */
85enum sprd_eic_type {
86 SPRD_EIC_DEBOUNCE,
87 SPRD_EIC_LATCH,
88 SPRD_EIC_ASYNC,
89 SPRD_EIC_SYNC,
90 SPRD_EIC_MAX,
91};
92
93struct sprd_eic {
94 struct gpio_chip chip;
95 struct notifier_block irq_nb;
96 void __iomem *base[SPRD_EIC_MAX_BANK];
97 enum sprd_eic_type type;
98 spinlock_t lock;
99 int irq;
100};
101
102static ATOMIC_NOTIFIER_HEAD(sprd_eic_irq_notifier);
103
104static struct sprd_eic *to_sprd_eic(struct notifier_block *nb)
105{
106 return container_of(nb, struct sprd_eic, irq_nb);
107}
108
109struct sprd_eic_variant_data {
110 enum sprd_eic_type type;
111 u32 num_eics;
112};
113
114static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
115 "eic-debounce", "eic-latch", "eic-async",
116 "eic-sync",
117};
118
119static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
120 .type = SPRD_EIC_DEBOUNCE,
121 .num_eics = 8,
122};
123
124static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
125 .type = SPRD_EIC_LATCH,
126 .num_eics = 8,
127};
128
129static const struct sprd_eic_variant_data sc9860_eic_async_data = {
130 .type = SPRD_EIC_ASYNC,
131 .num_eics = 8,
132};
133
134static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
135 .type = SPRD_EIC_SYNC,
136 .num_eics = 8,
137};
138
139static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
140 unsigned int bank)
141{
142 if (bank >= SPRD_EIC_MAX_BANK)
143 return NULL;
144
145 return sprd_eic->base[bank];
146}
147
148static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
149 u16 reg, unsigned int val)
150{
151 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
152 void __iomem *base =
153 sprd_eic_offset_base(sprd_eic, bank: offset / SPRD_EIC_PER_BANK_NR);
154 unsigned long flags;
155 u32 tmp;
156
157 spin_lock_irqsave(&sprd_eic->lock, flags);
158 tmp = readl_relaxed(base + reg);
159
160 if (val)
161 tmp |= BIT(SPRD_EIC_BIT(offset));
162 else
163 tmp &= ~BIT(SPRD_EIC_BIT(offset));
164
165 writel_relaxed(tmp, base + reg);
166 spin_unlock_irqrestore(lock: &sprd_eic->lock, flags);
167}
168
169static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
170{
171 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
172 void __iomem *base =
173 sprd_eic_offset_base(sprd_eic, bank: offset / SPRD_EIC_PER_BANK_NR);
174
175 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
176}
177
178static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
179{
180 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, val: 1);
181 return 0;
182}
183
184static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
185{
186 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, val: 0);
187}
188
189static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
190{
191 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
192
193 switch (sprd_eic->type) {
194 case SPRD_EIC_DEBOUNCE:
195 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
196 case SPRD_EIC_ASYNC:
197 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
198 case SPRD_EIC_SYNC:
199 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
200 default:
201 return -ENOTSUPP;
202 }
203}
204
205static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
206{
207 /* EICs are always input, nothing need to do here. */
208 return 0;
209}
210
211static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
212{
213 /* EICs are always input, nothing need to do here. */
214}
215
216static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
217 unsigned int debounce)
218{
219 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
220 void __iomem *base =
221 sprd_eic_offset_base(sprd_eic, bank: offset / SPRD_EIC_PER_BANK_NR);
222 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
223 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
224
225 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
226 writel_relaxed(value, base + reg);
227
228 return 0;
229}
230
231static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
232 unsigned long config)
233{
234 unsigned long param = pinconf_to_config_param(config);
235 u32 arg = pinconf_to_config_argument(config);
236
237 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
238 return sprd_eic_set_debounce(chip, offset, debounce: arg);
239
240 return -ENOTSUPP;
241}
242
243static void sprd_eic_irq_mask(struct irq_data *data)
244{
245 struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data);
246 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
247 u32 offset = irqd_to_hwirq(d: data);
248
249 switch (sprd_eic->type) {
250 case SPRD_EIC_DEBOUNCE:
251 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, val: 0);
252 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, val: 0);
253 break;
254 case SPRD_EIC_LATCH:
255 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, val: 0);
256 break;
257 case SPRD_EIC_ASYNC:
258 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, val: 0);
259 break;
260 case SPRD_EIC_SYNC:
261 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, val: 0);
262 break;
263 default:
264 dev_err(chip->parent, "Unsupported EIC type.\n");
265 }
266
267 gpiochip_disable_irq(gc: chip, offset);
268}
269
270static void sprd_eic_irq_unmask(struct irq_data *data)
271{
272 struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data);
273 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
274 u32 offset = irqd_to_hwirq(d: data);
275
276 gpiochip_enable_irq(gc: chip, offset);
277
278 switch (sprd_eic->type) {
279 case SPRD_EIC_DEBOUNCE:
280 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, val: 1);
281 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, val: 1);
282 break;
283 case SPRD_EIC_LATCH:
284 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, val: 1);
285 break;
286 case SPRD_EIC_ASYNC:
287 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, val: 1);
288 break;
289 case SPRD_EIC_SYNC:
290 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, val: 1);
291 break;
292 default:
293 dev_err(chip->parent, "Unsupported EIC type.\n");
294 }
295}
296
297static void sprd_eic_irq_ack(struct irq_data *data)
298{
299 struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data);
300 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
301 u32 offset = irqd_to_hwirq(d: data);
302
303 switch (sprd_eic->type) {
304 case SPRD_EIC_DEBOUNCE:
305 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, val: 1);
306 break;
307 case SPRD_EIC_LATCH:
308 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, val: 1);
309 break;
310 case SPRD_EIC_ASYNC:
311 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, val: 1);
312 break;
313 case SPRD_EIC_SYNC:
314 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, val: 1);
315 break;
316 default:
317 dev_err(chip->parent, "Unsupported EIC type.\n");
318 }
319}
320
321static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
322{
323 struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data);
324 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
325 u32 offset = irqd_to_hwirq(d: data);
326 int state;
327
328 switch (sprd_eic->type) {
329 case SPRD_EIC_DEBOUNCE:
330 switch (flow_type) {
331 case IRQ_TYPE_LEVEL_HIGH:
332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, val: 1);
333 break;
334 case IRQ_TYPE_LEVEL_LOW:
335 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, val: 0);
336 break;
337 case IRQ_TYPE_EDGE_RISING:
338 case IRQ_TYPE_EDGE_FALLING:
339 case IRQ_TYPE_EDGE_BOTH:
340 state = sprd_eic_get(chip, offset);
341 if (state)
342 sprd_eic_update(chip, offset,
343 SPRD_EIC_DBNC_IEV, val: 0);
344 else
345 sprd_eic_update(chip, offset,
346 SPRD_EIC_DBNC_IEV, val: 1);
347 break;
348 default:
349 return -ENOTSUPP;
350 }
351
352 irq_set_handler_locked(data, handler: handle_level_irq);
353 break;
354 case SPRD_EIC_LATCH:
355 switch (flow_type) {
356 case IRQ_TYPE_LEVEL_HIGH:
357 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, val: 0);
358 break;
359 case IRQ_TYPE_LEVEL_LOW:
360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, val: 1);
361 break;
362 case IRQ_TYPE_EDGE_RISING:
363 case IRQ_TYPE_EDGE_FALLING:
364 case IRQ_TYPE_EDGE_BOTH:
365 state = sprd_eic_get(chip, offset);
366 if (state)
367 sprd_eic_update(chip, offset,
368 SPRD_EIC_LATCH_INTPOL, val: 0);
369 else
370 sprd_eic_update(chip, offset,
371 SPRD_EIC_LATCH_INTPOL, val: 1);
372 break;
373 default:
374 return -ENOTSUPP;
375 }
376
377 irq_set_handler_locked(data, handler: handle_level_irq);
378 break;
379 case SPRD_EIC_ASYNC:
380 switch (flow_type) {
381 case IRQ_TYPE_EDGE_RISING:
382 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, val: 0);
383 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, val: 0);
384 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, val: 1);
385 irq_set_handler_locked(data, handler: handle_edge_irq);
386 break;
387 case IRQ_TYPE_EDGE_FALLING:
388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, val: 0);
389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, val: 0);
390 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, val: 0);
391 irq_set_handler_locked(data, handler: handle_edge_irq);
392 break;
393 case IRQ_TYPE_EDGE_BOTH:
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, val: 0);
395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, val: 1);
396 irq_set_handler_locked(data, handler: handle_edge_irq);
397 break;
398 case IRQ_TYPE_LEVEL_HIGH:
399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, val: 0);
400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, val: 1);
401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, val: 1);
402 irq_set_handler_locked(data, handler: handle_level_irq);
403 break;
404 case IRQ_TYPE_LEVEL_LOW:
405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, val: 0);
406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, val: 1);
407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, val: 0);
408 irq_set_handler_locked(data, handler: handle_level_irq);
409 break;
410 default:
411 return -ENOTSUPP;
412 }
413 break;
414 case SPRD_EIC_SYNC:
415 switch (flow_type) {
416 case IRQ_TYPE_EDGE_RISING:
417 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, val: 0);
418 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, val: 0);
419 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, val: 1);
420 irq_set_handler_locked(data, handler: handle_edge_irq);
421 break;
422 case IRQ_TYPE_EDGE_FALLING:
423 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, val: 0);
424 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, val: 0);
425 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, val: 0);
426 irq_set_handler_locked(data, handler: handle_edge_irq);
427 break;
428 case IRQ_TYPE_EDGE_BOTH:
429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, val: 0);
430 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, val: 1);
431 irq_set_handler_locked(data, handler: handle_edge_irq);
432 break;
433 case IRQ_TYPE_LEVEL_HIGH:
434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, val: 0);
435 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, val: 1);
436 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, val: 1);
437 irq_set_handler_locked(data, handler: handle_level_irq);
438 break;
439 case IRQ_TYPE_LEVEL_LOW:
440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, val: 0);
441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, val: 1);
442 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, val: 0);
443 irq_set_handler_locked(data, handler: handle_level_irq);
444 break;
445 default:
446 return -ENOTSUPP;
447 }
448 break;
449 default:
450 dev_err(chip->parent, "Unsupported EIC type.\n");
451 return -ENOTSUPP;
452 }
453
454 return 0;
455}
456
457static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
458 unsigned int offset)
459{
460 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
461 struct irq_data *data = irq_get_irq_data(irq);
462 u32 trigger = irqd_get_trigger_type(d: data);
463 int state, post_state;
464
465 /*
466 * The debounce EIC and latch EIC can only support level trigger, so we
467 * can toggle the level trigger to emulate the edge trigger.
468 */
469 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
470 sprd_eic->type != SPRD_EIC_LATCH) ||
471 !(trigger & IRQ_TYPE_EDGE_BOTH))
472 return;
473
474 sprd_eic_irq_mask(data);
475 state = sprd_eic_get(chip, offset);
476
477retry:
478 switch (sprd_eic->type) {
479 case SPRD_EIC_DEBOUNCE:
480 if (state)
481 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, val: 0);
482 else
483 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, val: 1);
484 break;
485 case SPRD_EIC_LATCH:
486 if (state)
487 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, val: 0);
488 else
489 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, val: 1);
490 break;
491 default:
492 sprd_eic_irq_unmask(data);
493 return;
494 }
495
496 post_state = sprd_eic_get(chip, offset);
497 if (state != post_state) {
498 dev_warn(chip->parent, "EIC level was changed.\n");
499 state = post_state;
500 goto retry;
501 }
502
503 sprd_eic_irq_unmask(data);
504}
505
506static void sprd_eic_handle_one_type(struct gpio_chip *chip)
507{
508 struct sprd_eic *sprd_eic = gpiochip_get_data(gc: chip);
509 u32 bank, n, girq;
510
511 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
512 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
513 unsigned long reg;
514
515 switch (sprd_eic->type) {
516 case SPRD_EIC_DEBOUNCE:
517 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
518 SPRD_EIC_DATA_MASK;
519 break;
520 case SPRD_EIC_LATCH:
521 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
522 SPRD_EIC_DATA_MASK;
523 break;
524 case SPRD_EIC_ASYNC:
525 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
526 SPRD_EIC_DATA_MASK;
527 break;
528 case SPRD_EIC_SYNC:
529 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
530 SPRD_EIC_DATA_MASK;
531 break;
532 default:
533 dev_err(chip->parent, "Unsupported EIC type.\n");
534 return;
535 }
536
537 for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
538 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
539
540 girq = irq_find_mapping(domain: chip->irq.domain, hwirq: offset);
541
542 generic_handle_irq(irq: girq);
543 sprd_eic_toggle_trigger(chip, irq: girq, offset);
544 }
545 }
546}
547
548static void sprd_eic_irq_handler(struct irq_desc *desc)
549{
550 struct irq_chip *ic = irq_desc_get_chip(desc);
551
552 chained_irq_enter(chip: ic, desc);
553
554 /*
555 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
556 * and sync) share one same interrupt line, we should notify all of
557 * them to let them check if there are EIC interrupts were triggered.
558 */
559 atomic_notifier_call_chain(nh: &sprd_eic_irq_notifier, val: 0, NULL);
560
561 chained_irq_exit(chip: ic, desc);
562}
563
564static int sprd_eic_irq_notify(struct notifier_block *nb, unsigned long action,
565 void *data)
566{
567 struct sprd_eic *sprd_eic = to_sprd_eic(nb);
568
569 sprd_eic_handle_one_type(chip: &sprd_eic->chip);
570
571 return NOTIFY_OK;
572}
573
574static const struct irq_chip sprd_eic_irq = {
575 .name = "sprd-eic",
576 .irq_ack = sprd_eic_irq_ack,
577 .irq_mask = sprd_eic_irq_mask,
578 .irq_unmask = sprd_eic_irq_unmask,
579 .irq_set_type = sprd_eic_irq_set_type,
580 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
581 GPIOCHIP_IRQ_RESOURCE_HELPERS,
582};
583
584static void sprd_eic_unregister_notifier(void *data)
585{
586 struct notifier_block *nb = data;
587
588 atomic_notifier_chain_unregister(nh: &sprd_eic_irq_notifier, nb);
589}
590
591static int sprd_eic_probe(struct platform_device *pdev)
592{
593 const struct sprd_eic_variant_data *pdata;
594 struct device *dev = &pdev->dev;
595 struct gpio_irq_chip *irq;
596 struct sprd_eic *sprd_eic;
597 struct resource *res;
598 int ret, i;
599
600 pdata = of_device_get_match_data(dev);
601 if (!pdata) {
602 dev_err(dev, "No matching driver data found.\n");
603 return -EINVAL;
604 }
605
606 sprd_eic = devm_kzalloc(dev, size: sizeof(*sprd_eic), GFP_KERNEL);
607 if (!sprd_eic)
608 return -ENOMEM;
609
610 spin_lock_init(&sprd_eic->lock);
611 sprd_eic->type = pdata->type;
612
613 sprd_eic->irq = platform_get_irq(pdev, 0);
614 if (sprd_eic->irq < 0)
615 return sprd_eic->irq;
616
617 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
618 /*
619 * We can have maximum 3 banks EICs, and each EIC has
620 * its own base address. But some platform maybe only
621 * have one bank EIC, thus base[1] and base[2] can be
622 * optional.
623 */
624 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
625 if (!res)
626 break;
627
628 sprd_eic->base[i] = devm_ioremap_resource(dev, res);
629 if (IS_ERR(ptr: sprd_eic->base[i]))
630 return PTR_ERR(ptr: sprd_eic->base[i]);
631 }
632
633 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
634 sprd_eic->chip.ngpio = pdata->num_eics;
635 sprd_eic->chip.base = -1;
636 sprd_eic->chip.parent = dev;
637 sprd_eic->chip.direction_input = sprd_eic_direction_input;
638 switch (sprd_eic->type) {
639 case SPRD_EIC_DEBOUNCE:
640 sprd_eic->chip.request = sprd_eic_request;
641 sprd_eic->chip.free = sprd_eic_free;
642 sprd_eic->chip.set_config = sprd_eic_set_config;
643 sprd_eic->chip.set = sprd_eic_set;
644 fallthrough;
645 case SPRD_EIC_ASYNC:
646 case SPRD_EIC_SYNC:
647 sprd_eic->chip.get = sprd_eic_get;
648 break;
649 case SPRD_EIC_LATCH:
650 default:
651 break;
652 }
653
654 irq = &sprd_eic->chip.irq;
655 gpio_irq_chip_set_chip(girq: irq, chip: &sprd_eic_irq);
656 irq->handler = handle_bad_irq;
657 irq->default_type = IRQ_TYPE_NONE;
658 irq->parent_handler = sprd_eic_irq_handler;
659 irq->parent_handler_data = sprd_eic;
660 irq->num_parents = 1;
661 irq->parents = &sprd_eic->irq;
662
663 ret = devm_gpiochip_add_data(dev, &sprd_eic->chip, sprd_eic);
664 if (ret < 0) {
665 dev_err(dev, "Could not register gpiochip %d.\n", ret);
666 return ret;
667 }
668
669 sprd_eic->irq_nb.notifier_call = sprd_eic_irq_notify;
670 ret = atomic_notifier_chain_register(nh: &sprd_eic_irq_notifier,
671 nb: &sprd_eic->irq_nb);
672 if (ret)
673 return dev_err_probe(dev, err: ret,
674 fmt: "Failed to register with the interrupt notifier");
675
676 return devm_add_action_or_reset(dev, sprd_eic_unregister_notifier,
677 &sprd_eic->irq_nb);
678}
679
680static const struct of_device_id sprd_eic_of_match[] = {
681 {
682 .compatible = "sprd,sc9860-eic-debounce",
683 .data = &sc9860_eic_dbnc_data,
684 },
685 {
686 .compatible = "sprd,sc9860-eic-latch",
687 .data = &sc9860_eic_latch_data,
688 },
689 {
690 .compatible = "sprd,sc9860-eic-async",
691 .data = &sc9860_eic_async_data,
692 },
693 {
694 .compatible = "sprd,sc9860-eic-sync",
695 .data = &sc9860_eic_sync_data,
696 },
697 {
698 /* end of list */
699 }
700};
701MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
702
703static struct platform_driver sprd_eic_driver = {
704 .probe = sprd_eic_probe,
705 .driver = {
706 .name = "sprd-eic",
707 .of_match_table = sprd_eic_of_match,
708 },
709};
710
711module_platform_driver(sprd_eic_driver);
712
713MODULE_DESCRIPTION("Spreadtrum EIC driver");
714MODULE_LICENSE("GPL v2");
715

source code of linux/drivers/gpio/gpio-eic-sprd.c