1/*
2 * GPIO interface for IT87xx Super I/O chips
3 *
4 * Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
5 * Copyright (c) 2017 Google, Inc.
6 *
7 * Based on it87_wdt.c by Oliver Schuster
8 * gpio-it8761e.c by Denis Turischev
9 * gpio-stmpe.c by Rabin Vincent
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License 2 as published
13 * by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/io.h>
31#include <linux/errno.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/gpio/driver.h>
35
36/* Chip Id numbers */
37#define NO_DEV_ID 0xffff
38#define IT8613_ID 0x8613
39#define IT8620_ID 0x8620
40#define IT8628_ID 0x8628
41#define IT8718_ID 0x8718
42#define IT8728_ID 0x8728
43#define IT8732_ID 0x8732
44#define IT8761_ID 0x8761
45#define IT8772_ID 0x8772
46#define IT8786_ID 0x8786
47
48/* IO Ports */
49#define REG 0x2e
50#define VAL 0x2f
51
52/* Logical device Numbers LDN */
53#define GPIO 0x07
54
55/* Configuration Registers and Functions */
56#define LDNREG 0x07
57#define CHIPID 0x20
58#define CHIPREV 0x22
59
60/**
61 * struct it87_gpio - it87-specific GPIO chip
62 * @chip the underlying gpio_chip structure
63 * @lock a lock to avoid races between operations
64 * @io_base base address for gpio ports
65 * @io_size size of the port rage starting from io_base.
66 * @output_base Super I/O register address for Output Enable register
67 * @simple_base Super I/O 'Simple I/O' Enable register
68 * @simple_size Super IO 'Simple I/O' Enable register size; this is
69 * required because IT87xx chips might only provide Simple I/O
70 * switches on a subset of lines, whereas the others keep the
71 * same status all time.
72 */
73struct it87_gpio {
74 struct gpio_chip chip;
75 spinlock_t lock;
76 u16 io_base;
77 u16 io_size;
78 u8 output_base;
79 u8 simple_base;
80 u8 simple_size;
81};
82
83static struct it87_gpio it87_gpio_chip = {
84 .lock = __SPIN_LOCK_UNLOCKED(it87_gpio_chip.lock),
85};
86
87/* Superio chip access functions; copied from wdt_it87 */
88
89static inline int superio_enter(void)
90{
91 /*
92 * Try to reserve REG and REG + 1 for exclusive access.
93 */
94 if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
95 return -EBUSY;
96
97 outb(0x87, REG);
98 outb(0x01, REG);
99 outb(0x55, REG);
100 outb(0x55, REG);
101 return 0;
102}
103
104static inline void superio_exit(void)
105{
106 outb(0x02, REG);
107 outb(0x02, VAL);
108 release_region(REG, 2);
109}
110
111static inline void superio_select(int ldn)
112{
113 outb(LDNREG, REG);
114 outb(ldn, VAL);
115}
116
117static inline int superio_inb(int reg)
118{
119 outb(reg, REG);
120 return inb(VAL);
121}
122
123static inline void superio_outb(int val, int reg)
124{
125 outb(reg, REG);
126 outb(val, VAL);
127}
128
129static inline int superio_inw(int reg)
130{
131 int val;
132
133 outb(reg++, REG);
134 val = inb(VAL) << 8;
135 outb(reg, REG);
136 val |= inb(VAL);
137 return val;
138}
139
140static inline void superio_outw(int val, int reg)
141{
142 outb(reg++, REG);
143 outb(val >> 8, VAL);
144 outb(reg, REG);
145 outb(val, VAL);
146}
147
148static inline void superio_set_mask(int mask, int reg)
149{
150 u8 curr_val = superio_inb(reg);
151 u8 new_val = curr_val | mask;
152
153 if (curr_val != new_val)
154 superio_outb(new_val, reg);
155}
156
157static inline void superio_clear_mask(int mask, int reg)
158{
159 u8 curr_val = superio_inb(reg);
160 u8 new_val = curr_val & ~mask;
161
162 if (curr_val != new_val)
163 superio_outb(new_val, reg);
164}
165
166static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num)
167{
168 u8 mask, group;
169 int rc = 0;
170 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
171
172 mask = 1 << (gpio_num % 8);
173 group = (gpio_num / 8);
174
175 spin_lock(&it87_gpio->lock);
176
177 rc = superio_enter();
178 if (rc)
179 goto exit;
180
181 /* not all the IT87xx chips support Simple I/O and not all of
182 * them allow all the lines to be set/unset to Simple I/O.
183 */
184 if (group < it87_gpio->simple_size)
185 superio_set_mask(mask, group + it87_gpio->simple_base);
186
187 /* clear output enable, setting the pin to input, as all the
188 * newly-exported GPIO interfaces are set to input.
189 */
190 superio_clear_mask(mask, group + it87_gpio->output_base);
191
192 superio_exit();
193
194exit:
195 spin_unlock(&it87_gpio->lock);
196 return rc;
197}
198
199static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num)
200{
201 u16 reg;
202 u8 mask;
203 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
204
205 mask = 1 << (gpio_num % 8);
206 reg = (gpio_num / 8) + it87_gpio->io_base;
207
208 return !!(inb(reg) & mask);
209}
210
211static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num)
212{
213 u8 mask, group;
214 int rc = 0;
215 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
216
217 mask = 1 << (gpio_num % 8);
218 group = (gpio_num / 8);
219
220 spin_lock(&it87_gpio->lock);
221
222 rc = superio_enter();
223 if (rc)
224 goto exit;
225
226 /* clear the output enable bit */
227 superio_clear_mask(mask, group + it87_gpio->output_base);
228
229 superio_exit();
230
231exit:
232 spin_unlock(&it87_gpio->lock);
233 return rc;
234}
235
236static void it87_gpio_set(struct gpio_chip *chip,
237 unsigned gpio_num, int val)
238{
239 u8 mask, curr_vals;
240 u16 reg;
241 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
242
243 mask = 1 << (gpio_num % 8);
244 reg = (gpio_num / 8) + it87_gpio->io_base;
245
246 curr_vals = inb(reg);
247 if (val)
248 outb(curr_vals | mask, reg);
249 else
250 outb(curr_vals & ~mask, reg);
251}
252
253static int it87_gpio_direction_out(struct gpio_chip *chip,
254 unsigned gpio_num, int val)
255{
256 u8 mask, group;
257 int rc = 0;
258 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
259
260 mask = 1 << (gpio_num % 8);
261 group = (gpio_num / 8);
262
263 spin_lock(&it87_gpio->lock);
264
265 rc = superio_enter();
266 if (rc)
267 goto exit;
268
269 /* set the output enable bit */
270 superio_set_mask(mask, group + it87_gpio->output_base);
271
272 it87_gpio_set(chip, gpio_num, val);
273
274 superio_exit();
275
276exit:
277 spin_unlock(&it87_gpio->lock);
278 return rc;
279}
280
281static const struct gpio_chip it87_template_chip = {
282 .label = KBUILD_MODNAME,
283 .owner = THIS_MODULE,
284 .request = it87_gpio_request,
285 .get = it87_gpio_get,
286 .direction_input = it87_gpio_direction_in,
287 .set = it87_gpio_set,
288 .direction_output = it87_gpio_direction_out,
289 .base = -1
290};
291
292static int __init it87_gpio_init(void)
293{
294 int rc = 0, i;
295 u16 chip_type;
296 u8 chip_rev, gpio_ba_reg;
297 char *labels, **labels_table;
298
299 struct it87_gpio *it87_gpio = &it87_gpio_chip;
300
301 rc = superio_enter();
302 if (rc)
303 return rc;
304
305 chip_type = superio_inw(CHIPID);
306 chip_rev = superio_inb(CHIPREV) & 0x0f;
307 superio_exit();
308
309 it87_gpio->chip = it87_template_chip;
310
311 switch (chip_type) {
312 case IT8613_ID:
313 gpio_ba_reg = 0x62;
314 it87_gpio->io_size = 8; /* it8613 only needs 6, use 8 for alignment */
315 it87_gpio->output_base = 0xc8;
316 it87_gpio->simple_base = 0xc0;
317 it87_gpio->simple_size = 6;
318 it87_gpio->chip.ngpio = 64; /* has 48, use 64 for convenient calc */
319 break;
320 case IT8620_ID:
321 case IT8628_ID:
322 gpio_ba_reg = 0x62;
323 it87_gpio->io_size = 11;
324 it87_gpio->output_base = 0xc8;
325 it87_gpio->simple_size = 0;
326 it87_gpio->chip.ngpio = 64;
327 break;
328 case IT8718_ID:
329 case IT8728_ID:
330 case IT8732_ID:
331 case IT8772_ID:
332 case IT8786_ID:
333 gpio_ba_reg = 0x62;
334 it87_gpio->io_size = 8;
335 it87_gpio->output_base = 0xc8;
336 it87_gpio->simple_base = 0xc0;
337 it87_gpio->simple_size = 5;
338 it87_gpio->chip.ngpio = 64;
339 break;
340 case IT8761_ID:
341 gpio_ba_reg = 0x60;
342 it87_gpio->io_size = 4;
343 it87_gpio->output_base = 0xf0;
344 it87_gpio->simple_size = 0;
345 it87_gpio->chip.ngpio = 16;
346 break;
347 case NO_DEV_ID:
348 pr_err("no device\n");
349 return -ENODEV;
350 default:
351 pr_err("Unknown Chip found, Chip %04x Revision %x\n",
352 chip_type, chip_rev);
353 return -ENODEV;
354 }
355
356 rc = superio_enter();
357 if (rc)
358 return rc;
359
360 superio_select(GPIO);
361
362 /* fetch GPIO base address */
363 it87_gpio->io_base = superio_inw(gpio_ba_reg);
364
365 superio_exit();
366
367 pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n",
368 chip_type, chip_rev, it87_gpio->chip.ngpio,
369 it87_gpio->io_base);
370
371 if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
372 KBUILD_MODNAME))
373 return -EBUSY;
374
375 /* Set up aliases for the GPIO connection.
376 *
377 * ITE documentation for recent chips such as the IT8728F
378 * refers to the GPIO lines as GPxy, with a coordinates system
379 * where x is the GPIO group (starting from 1) and y is the
380 * bit within the group.
381 *
382 * By creating these aliases, we make it easier to understand
383 * to which GPIO pin we're referring to.
384 */
385 labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"),
386 GFP_KERNEL);
387 labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *),
388 GFP_KERNEL);
389
390 if (!labels || !labels_table) {
391 rc = -ENOMEM;
392 goto labels_free;
393 }
394
395 for (i = 0; i < it87_gpio->chip.ngpio; i++) {
396 char *label = &labels[i * sizeof("it87_gpXY")];
397
398 sprintf(label, "it87_gp%u%u", 1+(i/8), i%8);
399 labels_table[i] = label;
400 }
401
402 it87_gpio->chip.names = (const char *const*)labels_table;
403
404 rc = gpiochip_add_data(&it87_gpio->chip, it87_gpio);
405 if (rc)
406 goto labels_free;
407
408 return 0;
409
410labels_free:
411 kfree(labels_table);
412 kfree(labels);
413 release_region(it87_gpio->io_base, it87_gpio->io_size);
414 return rc;
415}
416
417static void __exit it87_gpio_exit(void)
418{
419 struct it87_gpio *it87_gpio = &it87_gpio_chip;
420
421 gpiochip_remove(&it87_gpio->chip);
422 release_region(it87_gpio->io_base, it87_gpio->io_size);
423 kfree(it87_gpio->chip.names[0]);
424 kfree(it87_gpio->chip.names);
425}
426
427module_init(it87_gpio_init);
428module_exit(it87_gpio_exit);
429
430MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>");
431MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips");
432MODULE_LICENSE("GPL");
433