1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Generic driver for memory-mapped GPIO controllers.
4 *
5 * Copyright 2008 MontaVista Software, Inc.
6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 *
8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
9 * ...`` ```````..
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
13 * `````````
14 ___
15_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
16__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
17o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
18 `....trivial..'~`.```.```
19 * ```````
20 * .```````~~~~`..`.``.``.
21 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
25 * ``.`.``...``` ```.. output pins are also supported.`
26 * ^^ `````.`````````.,``~``~``~~``````
27 * . ^^
28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
32 * ..````````......``````````` \o_
33 * |
34 * ^^ / \
35 *
36 * ...`````~~`.....``.`..........``````.`.``.```........``.
37 * ` 8, 16, 32 and 64 bits registers are supported, and``.
38 * . the number of GPIOs is determined by the width of ~
39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
40 * `.......````.```
41 */
42
43#include <linux/init.h>
44#include <linux/err.h>
45#include <linux/bug.h>
46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/spinlock.h>
49#include <linux/compiler.h>
50#include <linux/types.h>
51#include <linux/errno.h>
52#include <linux/log2.h>
53#include <linux/ioport.h>
54#include <linux/io.h>
55#include <linux/gpio/driver.h>
56#include <linux/slab.h>
57#include <linux/bitops.h>
58#include <linux/platform_device.h>
59#include <linux/mod_devicetable.h>
60#include <linux/of.h>
61#include <linux/of_device.h>
62
63static void bgpio_write8(void __iomem *reg, unsigned long data)
64{
65 writeb(data, reg);
66}
67
68static unsigned long bgpio_read8(void __iomem *reg)
69{
70 return readb(reg);
71}
72
73static void bgpio_write16(void __iomem *reg, unsigned long data)
74{
75 writew(data, reg);
76}
77
78static unsigned long bgpio_read16(void __iomem *reg)
79{
80 return readw(reg);
81}
82
83static void bgpio_write32(void __iomem *reg, unsigned long data)
84{
85 writel(data, reg);
86}
87
88static unsigned long bgpio_read32(void __iomem *reg)
89{
90 return readl(reg);
91}
92
93#if BITS_PER_LONG >= 64
94static void bgpio_write64(void __iomem *reg, unsigned long data)
95{
96 writeq(data, reg);
97}
98
99static unsigned long bgpio_read64(void __iomem *reg)
100{
101 return readq(reg);
102}
103#endif /* BITS_PER_LONG >= 64 */
104
105static void bgpio_write16be(void __iomem *reg, unsigned long data)
106{
107 iowrite16be(data, reg);
108}
109
110static unsigned long bgpio_read16be(void __iomem *reg)
111{
112 return ioread16be(reg);
113}
114
115static void bgpio_write32be(void __iomem *reg, unsigned long data)
116{
117 iowrite32be(data, reg);
118}
119
120static unsigned long bgpio_read32be(void __iomem *reg)
121{
122 return ioread32be(reg);
123}
124
125static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
126{
127 if (gc->be_bits)
128 return BIT(gc->bgpio_bits - 1 - line);
129 return BIT(line);
130}
131
132static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
133{
134 unsigned long pinmask = bgpio_line2mask(gc, gpio);
135 bool dir = !!(gc->bgpio_dir & pinmask);
136
137 /*
138 * If the direction is OUT we read the value from the SET
139 * register, and if the direction is IN we read the value
140 * from the DAT register.
141 *
142 * If the direction bits are inverted, naturally this gets
143 * inverted too.
144 */
145 if (gc->bgpio_dir_inverted)
146 dir = !dir;
147
148 if (dir)
149 return !!(gc->read_reg(gc->reg_set) & pinmask);
150 else
151 return !!(gc->read_reg(gc->reg_dat) & pinmask);
152}
153
154/*
155 * This assumes that the bits in the GPIO register are in native endianness.
156 * We only assign the function pointer if we have that.
157 */
158static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
159 unsigned long *bits)
160{
161 unsigned long get_mask = 0;
162 unsigned long set_mask = 0;
163
164 /* Make sure we first clear any bits that are zero when we read the register */
165 *bits &= ~*mask;
166
167 /* Exploit the fact that we know which directions are set */
168 if (gc->bgpio_dir_inverted) {
169 set_mask = *mask & ~gc->bgpio_dir;
170 get_mask = *mask & gc->bgpio_dir;
171 } else {
172 set_mask = *mask & gc->bgpio_dir;
173 get_mask = *mask & ~gc->bgpio_dir;
174 }
175
176 if (set_mask)
177 *bits |= gc->read_reg(gc->reg_set) & set_mask;
178 if (get_mask)
179 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
180
181 return 0;
182}
183
184static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
185{
186 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
187}
188
189/*
190 * This only works if the bits in the GPIO register are in native endianness.
191 */
192static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
193 unsigned long *bits)
194{
195 /* Make sure we first clear any bits that are zero when we read the register */
196 *bits &= ~*mask;
197 *bits |= gc->read_reg(gc->reg_dat) & *mask;
198 return 0;
199}
200
201/*
202 * With big endian mirrored bit order it becomes more tedious.
203 */
204static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
205 unsigned long *bits)
206{
207 unsigned long readmask = 0;
208 unsigned long val;
209 int bit;
210
211 /* Make sure we first clear any bits that are zero when we read the register */
212 *bits &= ~*mask;
213
214 /* Create a mirrored mask */
215 bit = -1;
216 while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
217 readmask |= bgpio_line2mask(gc, bit);
218
219 /* Read the register */
220 val = gc->read_reg(gc->reg_dat) & readmask;
221
222 /*
223 * Mirror the result into the "bits" result, this will give line 0
224 * in bit 0 ... line 31 in bit 31 for a 32bit register.
225 */
226 bit = -1;
227 while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
228 *bits |= bgpio_line2mask(gc, bit);
229
230 return 0;
231}
232
233static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
234{
235}
236
237static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
238{
239 unsigned long mask = bgpio_line2mask(gc, gpio);
240 unsigned long flags;
241
242 spin_lock_irqsave(&gc->bgpio_lock, flags);
243
244 if (val)
245 gc->bgpio_data |= mask;
246 else
247 gc->bgpio_data &= ~mask;
248
249 gc->write_reg(gc->reg_dat, gc->bgpio_data);
250
251 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
252}
253
254static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
255 int val)
256{
257 unsigned long mask = bgpio_line2mask(gc, gpio);
258
259 if (val)
260 gc->write_reg(gc->reg_set, mask);
261 else
262 gc->write_reg(gc->reg_clr, mask);
263}
264
265static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
266{
267 unsigned long mask = bgpio_line2mask(gc, gpio);
268 unsigned long flags;
269
270 spin_lock_irqsave(&gc->bgpio_lock, flags);
271
272 if (val)
273 gc->bgpio_data |= mask;
274 else
275 gc->bgpio_data &= ~mask;
276
277 gc->write_reg(gc->reg_set, gc->bgpio_data);
278
279 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
280}
281
282static void bgpio_multiple_get_masks(struct gpio_chip *gc,
283 unsigned long *mask, unsigned long *bits,
284 unsigned long *set_mask,
285 unsigned long *clear_mask)
286{
287 int i;
288
289 *set_mask = 0;
290 *clear_mask = 0;
291
292 for (i = 0; i < gc->bgpio_bits; i++) {
293 if (*mask == 0)
294 break;
295 if (__test_and_clear_bit(i, mask)) {
296 if (test_bit(i, bits))
297 *set_mask |= bgpio_line2mask(gc, i);
298 else
299 *clear_mask |= bgpio_line2mask(gc, i);
300 }
301 }
302}
303
304static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
305 unsigned long *mask,
306 unsigned long *bits,
307 void __iomem *reg)
308{
309 unsigned long flags;
310 unsigned long set_mask, clear_mask;
311
312 spin_lock_irqsave(&gc->bgpio_lock, flags);
313
314 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
315
316 gc->bgpio_data |= set_mask;
317 gc->bgpio_data &= ~clear_mask;
318
319 gc->write_reg(reg, gc->bgpio_data);
320
321 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
322}
323
324static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
325 unsigned long *bits)
326{
327 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
328}
329
330static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
331 unsigned long *bits)
332{
333 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
334}
335
336static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
337 unsigned long *mask,
338 unsigned long *bits)
339{
340 unsigned long set_mask, clear_mask;
341
342 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
343
344 if (set_mask)
345 gc->write_reg(gc->reg_set, set_mask);
346 if (clear_mask)
347 gc->write_reg(gc->reg_clr, clear_mask);
348}
349
350static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
351{
352 return 0;
353}
354
355static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
356 int val)
357{
358 return -EINVAL;
359}
360
361static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
362 int val)
363{
364 gc->set(gc, gpio, val);
365
366 return 0;
367}
368
369static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
370{
371 unsigned long flags;
372
373 spin_lock_irqsave(&gc->bgpio_lock, flags);
374
375 if (gc->bgpio_dir_inverted)
376 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
377 else
378 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
379 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
380
381 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
382
383 return 0;
384}
385
386static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
387{
388 /* Return 0 if output, 1 of input */
389 if (gc->bgpio_dir_inverted)
390 return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
391 else
392 return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
393}
394
395static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
396{
397 unsigned long flags;
398
399 gc->set(gc, gpio, val);
400
401 spin_lock_irqsave(&gc->bgpio_lock, flags);
402
403 if (gc->bgpio_dir_inverted)
404 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
405 else
406 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
407 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
408
409 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
410
411 return 0;
412}
413
414static int bgpio_setup_accessors(struct device *dev,
415 struct gpio_chip *gc,
416 bool byte_be)
417{
418
419 switch (gc->bgpio_bits) {
420 case 8:
421 gc->read_reg = bgpio_read8;
422 gc->write_reg = bgpio_write8;
423 break;
424 case 16:
425 if (byte_be) {
426 gc->read_reg = bgpio_read16be;
427 gc->write_reg = bgpio_write16be;
428 } else {
429 gc->read_reg = bgpio_read16;
430 gc->write_reg = bgpio_write16;
431 }
432 break;
433 case 32:
434 if (byte_be) {
435 gc->read_reg = bgpio_read32be;
436 gc->write_reg = bgpio_write32be;
437 } else {
438 gc->read_reg = bgpio_read32;
439 gc->write_reg = bgpio_write32;
440 }
441 break;
442#if BITS_PER_LONG >= 64
443 case 64:
444 if (byte_be) {
445 dev_err(dev,
446 "64 bit big endian byte order unsupported\n");
447 return -EINVAL;
448 } else {
449 gc->read_reg = bgpio_read64;
450 gc->write_reg = bgpio_write64;
451 }
452 break;
453#endif /* BITS_PER_LONG >= 64 */
454 default:
455 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
456 return -EINVAL;
457 }
458
459 return 0;
460}
461
462/*
463 * Create the device and allocate the resources. For setting GPIO's there are
464 * three supported configurations:
465 *
466 * - single input/output register resource (named "dat").
467 * - set/clear pair (named "set" and "clr").
468 * - single output register resource and single input resource ("set" and
469 * dat").
470 *
471 * For the single output register, this drives a 1 by setting a bit and a zero
472 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
473 * in the set register and clears it by setting a bit in the clear register.
474 * The configuration is detected by which resources are present.
475 *
476 * For setting the GPIO direction, there are three supported configurations:
477 *
478 * - simple bidirection GPIO that requires no configuration.
479 * - an output direction register (named "dirout") where a 1 bit
480 * indicates the GPIO is an output.
481 * - an input direction register (named "dirin") where a 1 bit indicates
482 * the GPIO is an input.
483 */
484static int bgpio_setup_io(struct gpio_chip *gc,
485 void __iomem *dat,
486 void __iomem *set,
487 void __iomem *clr,
488 unsigned long flags)
489{
490
491 gc->reg_dat = dat;
492 if (!gc->reg_dat)
493 return -EINVAL;
494
495 if (set && clr) {
496 gc->reg_set = set;
497 gc->reg_clr = clr;
498 gc->set = bgpio_set_with_clear;
499 gc->set_multiple = bgpio_set_multiple_with_clear;
500 } else if (set && !clr) {
501 gc->reg_set = set;
502 gc->set = bgpio_set_set;
503 gc->set_multiple = bgpio_set_multiple_set;
504 } else if (flags & BGPIOF_NO_OUTPUT) {
505 gc->set = bgpio_set_none;
506 gc->set_multiple = NULL;
507 } else {
508 gc->set = bgpio_set;
509 gc->set_multiple = bgpio_set_multiple;
510 }
511
512 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
513 (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
514 gc->get = bgpio_get_set;
515 if (!gc->be_bits)
516 gc->get_multiple = bgpio_get_set_multiple;
517 /*
518 * We deliberately avoid assigning the ->get_multiple() call
519 * for big endian mirrored registers which are ALSO reflecting
520 * their value in the set register when used as output. It is
521 * simply too much complexity, let the GPIO core fall back to
522 * reading each line individually in that fringe case.
523 */
524 } else {
525 gc->get = bgpio_get;
526 if (gc->be_bits)
527 gc->get_multiple = bgpio_get_multiple_be;
528 else
529 gc->get_multiple = bgpio_get_multiple;
530 }
531
532 return 0;
533}
534
535static int bgpio_setup_direction(struct gpio_chip *gc,
536 void __iomem *dirout,
537 void __iomem *dirin,
538 unsigned long flags)
539{
540 if (dirout && dirin) {
541 return -EINVAL;
542 } else if (dirout) {
543 gc->reg_dir = dirout;
544 gc->direction_output = bgpio_dir_out;
545 gc->direction_input = bgpio_dir_in;
546 gc->get_direction = bgpio_get_dir;
547 } else if (dirin) {
548 gc->reg_dir = dirin;
549 gc->direction_output = bgpio_dir_out;
550 gc->direction_input = bgpio_dir_in;
551 gc->get_direction = bgpio_get_dir;
552 gc->bgpio_dir_inverted = true;
553 } else {
554 if (flags & BGPIOF_NO_OUTPUT)
555 gc->direction_output = bgpio_dir_out_err;
556 else
557 gc->direction_output = bgpio_simple_dir_out;
558 gc->direction_input = bgpio_simple_dir_in;
559 }
560
561 return 0;
562}
563
564static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
565{
566 if (gpio_pin < chip->ngpio)
567 return 0;
568
569 return -EINVAL;
570}
571
572/**
573 * bgpio_init() - Initialize generic GPIO accessor functions
574 * @gc: the GPIO chip to set up
575 * @dev: the parent device of the new GPIO chip (compulsory)
576 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
577 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
578 * is expected that a 1 in the corresponding bit in this register means the
579 * line is asserted
580 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
581 * expected that we write the line with 1 in this register to drive the GPIO line
582 * high.
583 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
584 * expected that we write the line with 1 in this register to drive the GPIO line
585 * low. It is allowed to leave this address as NULL, in that case the SET register
586 * will be assumed to also clear the GPIO lines, by actively writing the line
587 * with 0.
588 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
589 * that setting a line to 1 in this register will turn that line into an
590 * output line. Conversely, setting the line to 0 will turn that line into
591 * an input. Either this or @dirin can be defined, but never both.
592 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
593 * that setting a line to 1 in this register will turn that line into an
594 * input line. Conversely, setting the line to 0 will turn that line into
595 * an output. Either this or @dirout can be defined, but never both.
596 * @flags: Different flags that will affect the behaviour of the device, such as
597 * endianness etc.
598 */
599int bgpio_init(struct gpio_chip *gc, struct device *dev,
600 unsigned long sz, void __iomem *dat, void __iomem *set,
601 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
602 unsigned long flags)
603{
604 int ret;
605
606 if (!is_power_of_2(sz))
607 return -EINVAL;
608
609 gc->bgpio_bits = sz * 8;
610 if (gc->bgpio_bits > BITS_PER_LONG)
611 return -EINVAL;
612
613 spin_lock_init(&gc->bgpio_lock);
614 gc->parent = dev;
615 gc->label = dev_name(dev);
616 gc->base = -1;
617 gc->ngpio = gc->bgpio_bits;
618 gc->request = bgpio_request;
619 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
620
621 ret = bgpio_setup_io(gc, dat, set, clr, flags);
622 if (ret)
623 return ret;
624
625 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
626 if (ret)
627 return ret;
628
629 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
630 if (ret)
631 return ret;
632
633 gc->bgpio_data = gc->read_reg(gc->reg_dat);
634 if (gc->set == bgpio_set_set &&
635 !(flags & BGPIOF_UNREADABLE_REG_SET))
636 gc->bgpio_data = gc->read_reg(gc->reg_set);
637 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
638 gc->bgpio_dir = gc->read_reg(gc->reg_dir);
639
640 return ret;
641}
642EXPORT_SYMBOL_GPL(bgpio_init);
643
644#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
645
646static void __iomem *bgpio_map(struct platform_device *pdev,
647 const char *name,
648 resource_size_t sane_sz)
649{
650 struct resource *r;
651 resource_size_t sz;
652
653 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
654 if (!r)
655 return NULL;
656
657 sz = resource_size(r);
658 if (sz != sane_sz)
659 return IOMEM_ERR_PTR(-EINVAL);
660
661 return devm_ioremap_resource(&pdev->dev, r);
662}
663
664#ifdef CONFIG_OF
665static const struct of_device_id bgpio_of_match[] = {
666 { .compatible = "brcm,bcm6345-gpio" },
667 { .compatible = "wd,mbl-gpio" },
668 { .compatible = "ni,169445-nand-gpio" },
669 { }
670};
671MODULE_DEVICE_TABLE(of, bgpio_of_match);
672
673static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
674 unsigned long *flags)
675{
676 struct bgpio_pdata *pdata;
677
678 if (!of_match_device(bgpio_of_match, &pdev->dev))
679 return NULL;
680
681 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
682 GFP_KERNEL);
683 if (!pdata)
684 return ERR_PTR(-ENOMEM);
685
686 pdata->base = -1;
687
688 if (of_device_is_big_endian(pdev->dev.of_node))
689 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
690
691 if (of_property_read_bool(pdev->dev.of_node, "no-output"))
692 *flags |= BGPIOF_NO_OUTPUT;
693
694 return pdata;
695}
696#else
697static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
698 unsigned long *flags)
699{
700 return NULL;
701}
702#endif /* CONFIG_OF */
703
704static int bgpio_pdev_probe(struct platform_device *pdev)
705{
706 struct device *dev = &pdev->dev;
707 struct resource *r;
708 void __iomem *dat;
709 void __iomem *set;
710 void __iomem *clr;
711 void __iomem *dirout;
712 void __iomem *dirin;
713 unsigned long sz;
714 unsigned long flags = 0;
715 int err;
716 struct gpio_chip *gc;
717 struct bgpio_pdata *pdata;
718
719 pdata = bgpio_parse_dt(pdev, &flags);
720 if (IS_ERR(pdata))
721 return PTR_ERR(pdata);
722
723 if (!pdata) {
724 pdata = dev_get_platdata(dev);
725 flags = pdev->id_entry->driver_data;
726 }
727
728 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
729 if (!r)
730 return -EINVAL;
731
732 sz = resource_size(r);
733
734 dat = bgpio_map(pdev, "dat", sz);
735 if (IS_ERR(dat))
736 return PTR_ERR(dat);
737
738 set = bgpio_map(pdev, "set", sz);
739 if (IS_ERR(set))
740 return PTR_ERR(set);
741
742 clr = bgpio_map(pdev, "clr", sz);
743 if (IS_ERR(clr))
744 return PTR_ERR(clr);
745
746 dirout = bgpio_map(pdev, "dirout", sz);
747 if (IS_ERR(dirout))
748 return PTR_ERR(dirout);
749
750 dirin = bgpio_map(pdev, "dirin", sz);
751 if (IS_ERR(dirin))
752 return PTR_ERR(dirin);
753
754 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
755 if (!gc)
756 return -ENOMEM;
757
758 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
759 if (err)
760 return err;
761
762 if (pdata) {
763 if (pdata->label)
764 gc->label = pdata->label;
765 gc->base = pdata->base;
766 if (pdata->ngpio > 0)
767 gc->ngpio = pdata->ngpio;
768 }
769
770 platform_set_drvdata(pdev, gc);
771
772 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
773}
774
775static const struct platform_device_id bgpio_id_table[] = {
776 {
777 .name = "basic-mmio-gpio",
778 .driver_data = 0,
779 }, {
780 .name = "basic-mmio-gpio-be",
781 .driver_data = BGPIOF_BIG_ENDIAN,
782 },
783 { }
784};
785MODULE_DEVICE_TABLE(platform, bgpio_id_table);
786
787static struct platform_driver bgpio_driver = {
788 .driver = {
789 .name = "basic-mmio-gpio",
790 .of_match_table = of_match_ptr(bgpio_of_match),
791 },
792 .id_table = bgpio_id_table,
793 .probe = bgpio_pdev_probe,
794};
795
796module_platform_driver(bgpio_driver);
797
798#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
799
800MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
801MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
802MODULE_LICENSE("GPL");
803