1/*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/slab.h>
22#include <linux/irq.h>
23#include <linux/gpio/driver.h>
24#include <linux/bitops.h>
25
26#define MPC8XXX_GPIO_PINS 32
27
28#define GPIO_DIR 0x00
29#define GPIO_ODR 0x04
30#define GPIO_DAT 0x08
31#define GPIO_IER 0x0c
32#define GPIO_IMR 0x10
33#define GPIO_ICR 0x14
34#define GPIO_ICR2 0x18
35
36struct mpc8xxx_gpio_chip {
37 struct gpio_chip gc;
38 void __iomem *regs;
39 raw_spinlock_t lock;
40
41 int (*direction_output)(struct gpio_chip *chip,
42 unsigned offset, int value);
43
44 struct irq_domain *irq;
45 unsigned int irqn;
46};
47
48/*
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
51 * This inline helper give the right bitmask for a certain line.
52 */
53static inline u32 mpc_pin2mask(unsigned int offset)
54{
55 return BIT(31 - offset);
56}
57
58/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
59 * defined as output cannot be determined by reading GPDAT register,
60 * so we use shadow data register instead. The status of input pins
61 * is determined by reading GPDAT register.
62 */
63static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
64{
65 u32 val;
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
67 u32 out_mask, out_shadow;
68
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
71 out_shadow = gc->bgpio_data & out_mask;
72
73 return !!((val | out_shadow) & mpc_pin2mask(gpio));
74}
75
76static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
78{
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 28..31 are input only on MPC5121 */
81 if (gpio >= 28)
82 return -EINVAL;
83
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
85}
86
87static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
88 unsigned int gpio, int val)
89{
90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
91 /* GPIO 0..3 are input only on MPC5125 */
92 if (gpio <= 3)
93 return -EINVAL;
94
95 return mpc8xxx_gc->direction_output(gc, gpio, val);
96}
97
98static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
99{
100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
101
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
103 return irq_create_mapping(mpc8xxx_gc->irq, offset);
104 else
105 return -ENXIO;
106}
107
108static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
109{
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
111 struct irq_chip *chip = irq_desc_get_chip(desc);
112 struct gpio_chip *gc = &mpc8xxx_gc->gc;
113 unsigned int mask;
114
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
117 if (mask)
118 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
119 32 - ffs(mask)));
120 if (chip->irq_eoi)
121 chip->irq_eoi(&desc->irq_data);
122}
123
124static void mpc8xxx_irq_unmask(struct irq_data *d)
125{
126 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
127 struct gpio_chip *gc = &mpc8xxx_gc->gc;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
131
132 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
133 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
134 | mpc_pin2mask(irqd_to_hwirq(d)));
135
136 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
137}
138
139static void mpc8xxx_irq_mask(struct irq_data *d)
140{
141 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
142 struct gpio_chip *gc = &mpc8xxx_gc->gc;
143 unsigned long flags;
144
145 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
146
147 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
148 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
149 & ~mpc_pin2mask(irqd_to_hwirq(d)));
150
151 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
152}
153
154static void mpc8xxx_irq_ack(struct irq_data *d)
155{
156 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
157 struct gpio_chip *gc = &mpc8xxx_gc->gc;
158
159 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
160 mpc_pin2mask(irqd_to_hwirq(d)));
161}
162
163static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
164{
165 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
166 struct gpio_chip *gc = &mpc8xxx_gc->gc;
167 unsigned long flags;
168
169 switch (flow_type) {
170 case IRQ_TYPE_EDGE_FALLING:
171 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
172 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
173 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
174 | mpc_pin2mask(irqd_to_hwirq(d)));
175 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
176 break;
177
178 case IRQ_TYPE_EDGE_BOTH:
179 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
180 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
181 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
182 & ~mpc_pin2mask(irqd_to_hwirq(d)));
183 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
184 break;
185
186 default:
187 return -EINVAL;
188 }
189
190 return 0;
191}
192
193static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
194{
195 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
196 struct gpio_chip *gc = &mpc8xxx_gc->gc;
197 unsigned long gpio = irqd_to_hwirq(d);
198 void __iomem *reg;
199 unsigned int shift;
200 unsigned long flags;
201
202 if (gpio < 16) {
203 reg = mpc8xxx_gc->regs + GPIO_ICR;
204 shift = (15 - gpio) * 2;
205 } else {
206 reg = mpc8xxx_gc->regs + GPIO_ICR2;
207 shift = (15 - (gpio % 16)) * 2;
208 }
209
210 switch (flow_type) {
211 case IRQ_TYPE_EDGE_FALLING:
212 case IRQ_TYPE_LEVEL_LOW:
213 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
214 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
215 | (2 << shift));
216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
217 break;
218
219 case IRQ_TYPE_EDGE_RISING:
220 case IRQ_TYPE_LEVEL_HIGH:
221 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
222 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
223 | (1 << shift));
224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
225 break;
226
227 case IRQ_TYPE_EDGE_BOTH:
228 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
229 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
231 break;
232
233 default:
234 return -EINVAL;
235 }
236
237 return 0;
238}
239
240static struct irq_chip mpc8xxx_irq_chip = {
241 .name = "mpc8xxx-gpio",
242 .irq_unmask = mpc8xxx_irq_unmask,
243 .irq_mask = mpc8xxx_irq_mask,
244 .irq_ack = mpc8xxx_irq_ack,
245 /* this might get overwritten in mpc8xxx_probe() */
246 .irq_set_type = mpc8xxx_irq_set_type,
247};
248
249static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
250 irq_hw_number_t hwirq)
251{
252 irq_set_chip_data(irq, h->host_data);
253 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
254
255 return 0;
256}
257
258static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
259 .map = mpc8xxx_gpio_irq_map,
260 .xlate = irq_domain_xlate_twocell,
261};
262
263struct mpc8xxx_gpio_devtype {
264 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
265 int (*gpio_get)(struct gpio_chip *, unsigned int);
266 int (*irq_set_type)(struct irq_data *, unsigned int);
267};
268
269static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
270 .gpio_dir_out = mpc5121_gpio_dir_out,
271 .irq_set_type = mpc512x_irq_set_type,
272};
273
274static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
275 .gpio_dir_out = mpc5125_gpio_dir_out,
276 .irq_set_type = mpc512x_irq_set_type,
277};
278
279static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
280 .gpio_get = mpc8572_gpio_get,
281};
282
283static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
284 .irq_set_type = mpc8xxx_irq_set_type,
285};
286
287static const struct of_device_id mpc8xxx_gpio_ids[] = {
288 { .compatible = "fsl,mpc8349-gpio", },
289 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
290 { .compatible = "fsl,mpc8610-gpio", },
291 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
292 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
293 { .compatible = "fsl,pq3-gpio", },
294 { .compatible = "fsl,qoriq-gpio", },
295 {}
296};
297
298static int mpc8xxx_probe(struct platform_device *pdev)
299{
300 struct device_node *np = pdev->dev.of_node;
301 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
302 struct gpio_chip *gc;
303 const struct mpc8xxx_gpio_devtype *devtype =
304 of_device_get_match_data(&pdev->dev);
305 int ret;
306
307 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
308 if (!mpc8xxx_gc)
309 return -ENOMEM;
310
311 platform_set_drvdata(pdev, mpc8xxx_gc);
312
313 raw_spin_lock_init(&mpc8xxx_gc->lock);
314
315 mpc8xxx_gc->regs = of_iomap(np, 0);
316 if (!mpc8xxx_gc->regs)
317 return -ENOMEM;
318
319 gc = &mpc8xxx_gc->gc;
320
321 if (of_property_read_bool(np, "little-endian")) {
322 ret = bgpio_init(gc, &pdev->dev, 4,
323 mpc8xxx_gc->regs + GPIO_DAT,
324 NULL, NULL,
325 mpc8xxx_gc->regs + GPIO_DIR, NULL,
326 BGPIOF_BIG_ENDIAN);
327 if (ret)
328 goto err;
329 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
330 } else {
331 ret = bgpio_init(gc, &pdev->dev, 4,
332 mpc8xxx_gc->regs + GPIO_DAT,
333 NULL, NULL,
334 mpc8xxx_gc->regs + GPIO_DIR, NULL,
335 BGPIOF_BIG_ENDIAN
336 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
337 if (ret)
338 goto err;
339 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
340 }
341
342 mpc8xxx_gc->direction_output = gc->direction_output;
343
344 if (!devtype)
345 devtype = &mpc8xxx_gpio_devtype_default;
346
347 /*
348 * It's assumed that only a single type of gpio controller is available
349 * on the current machine, so overwriting global data is fine.
350 */
351 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
352
353 if (devtype->gpio_dir_out)
354 gc->direction_output = devtype->gpio_dir_out;
355 if (devtype->gpio_get)
356 gc->get = devtype->gpio_get;
357
358 gc->to_irq = mpc8xxx_gpio_to_irq;
359
360 ret = gpiochip_add_data(gc, mpc8xxx_gc);
361 if (ret) {
362 pr_err("%pOF: GPIO chip registration failed with status %d\n",
363 np, ret);
364 goto err;
365 }
366
367 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
368 if (!mpc8xxx_gc->irqn)
369 return 0;
370
371 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
372 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
373 if (!mpc8xxx_gc->irq)
374 return 0;
375
376 /* ack and mask all irqs */
377 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
378 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
379
380 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
381 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
382 return 0;
383err:
384 iounmap(mpc8xxx_gc->regs);
385 return ret;
386}
387
388static int mpc8xxx_remove(struct platform_device *pdev)
389{
390 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
391
392 if (mpc8xxx_gc->irq) {
393 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
394 irq_domain_remove(mpc8xxx_gc->irq);
395 }
396
397 gpiochip_remove(&mpc8xxx_gc->gc);
398 iounmap(mpc8xxx_gc->regs);
399
400 return 0;
401}
402
403static struct platform_driver mpc8xxx_plat_driver = {
404 .probe = mpc8xxx_probe,
405 .remove = mpc8xxx_remove,
406 .driver = {
407 .name = "gpio-mpc8xxx",
408 .of_match_table = mpc8xxx_gpio_ids,
409 },
410};
411
412static int __init mpc8xxx_init(void)
413{
414 return platform_driver_register(&mpc8xxx_plat_driver);
415}
416
417arch_initcall(mpc8xxx_init);
418