1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
4 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
5 | */ |
6 | |
7 | #include <linux/err.h> |
8 | #include <linux/gpio/driver.h> |
9 | #include <linux/interrupt.h> |
10 | #include <linux/io.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/spinlock.h> |
14 | |
15 | #define MTK_BANK_CNT 3 |
16 | #define MTK_BANK_WIDTH 32 |
17 | |
18 | #define GPIO_BANK_STRIDE 0x04 |
19 | #define GPIO_REG_CTRL 0x00 |
20 | #define GPIO_REG_POL 0x10 |
21 | #define GPIO_REG_DATA 0x20 |
22 | #define GPIO_REG_DSET 0x30 |
23 | #define GPIO_REG_DCLR 0x40 |
24 | #define GPIO_REG_REDGE 0x50 |
25 | #define GPIO_REG_FEDGE 0x60 |
26 | #define GPIO_REG_HLVL 0x70 |
27 | #define GPIO_REG_LLVL 0x80 |
28 | #define GPIO_REG_STAT 0x90 |
29 | #define GPIO_REG_EDGE 0xA0 |
30 | |
31 | struct mtk_gc { |
32 | struct irq_chip irq_chip; |
33 | struct gpio_chip chip; |
34 | spinlock_t lock; |
35 | int bank; |
36 | u32 rising; |
37 | u32 falling; |
38 | u32 hlevel; |
39 | u32 llevel; |
40 | }; |
41 | |
42 | /** |
43 | * struct mtk - state container for |
44 | * data of the platform driver. It is 3 |
45 | * separate gpio-chip each one with its |
46 | * own irq_chip. |
47 | * @dev: device instance |
48 | * @base: memory base address |
49 | * @gpio_irq: irq number from the device tree |
50 | * @gc_map: array of the gpio chips |
51 | */ |
52 | struct mtk { |
53 | struct device *dev; |
54 | void __iomem *base; |
55 | int gpio_irq; |
56 | struct mtk_gc gc_map[MTK_BANK_CNT]; |
57 | }; |
58 | |
59 | static inline struct mtk_gc * |
60 | to_mediatek_gpio(struct gpio_chip *chip) |
61 | { |
62 | return container_of(chip, struct mtk_gc, chip); |
63 | } |
64 | |
65 | static inline void |
66 | mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) |
67 | { |
68 | struct gpio_chip *gc = &rg->chip; |
69 | struct mtk *mtk = gpiochip_get_data(gc); |
70 | |
71 | offset = (rg->bank * GPIO_BANK_STRIDE) + offset; |
72 | gc->write_reg(mtk->base + offset, val); |
73 | } |
74 | |
75 | static inline u32 |
76 | mtk_gpio_r32(struct mtk_gc *rg, u32 offset) |
77 | { |
78 | struct gpio_chip *gc = &rg->chip; |
79 | struct mtk *mtk = gpiochip_get_data(gc); |
80 | |
81 | offset = (rg->bank * GPIO_BANK_STRIDE) + offset; |
82 | return gc->read_reg(mtk->base + offset); |
83 | } |
84 | |
85 | static irqreturn_t |
86 | mediatek_gpio_irq_handler(int irq, void *data) |
87 | { |
88 | struct gpio_chip *gc = data; |
89 | struct mtk_gc *rg = to_mediatek_gpio(chip: gc); |
90 | irqreturn_t ret = IRQ_NONE; |
91 | unsigned long pending; |
92 | int bit; |
93 | |
94 | pending = mtk_gpio_r32(rg, GPIO_REG_STAT); |
95 | |
96 | for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { |
97 | generic_handle_domain_irq(domain: gc->irq.domain, hwirq: bit); |
98 | mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); |
99 | ret |= IRQ_HANDLED; |
100 | } |
101 | |
102 | return ret; |
103 | } |
104 | |
105 | static void |
106 | mediatek_gpio_irq_unmask(struct irq_data *d) |
107 | { |
108 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
109 | struct mtk_gc *rg = to_mediatek_gpio(chip: gc); |
110 | int pin = d->hwirq; |
111 | unsigned long flags; |
112 | u32 rise, fall, high, low; |
113 | |
114 | gpiochip_enable_irq(gc, offset: d->hwirq); |
115 | |
116 | spin_lock_irqsave(&rg->lock, flags); |
117 | rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); |
118 | fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); |
119 | high = mtk_gpio_r32(rg, GPIO_REG_HLVL); |
120 | low = mtk_gpio_r32(rg, GPIO_REG_LLVL); |
121 | mtk_gpio_w32(rg, GPIO_REG_REDGE, val: rise | (BIT(pin) & rg->rising)); |
122 | mtk_gpio_w32(rg, GPIO_REG_FEDGE, val: fall | (BIT(pin) & rg->falling)); |
123 | mtk_gpio_w32(rg, GPIO_REG_HLVL, val: high | (BIT(pin) & rg->hlevel)); |
124 | mtk_gpio_w32(rg, GPIO_REG_LLVL, val: low | (BIT(pin) & rg->llevel)); |
125 | spin_unlock_irqrestore(lock: &rg->lock, flags); |
126 | } |
127 | |
128 | static void |
129 | mediatek_gpio_irq_mask(struct irq_data *d) |
130 | { |
131 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
132 | struct mtk_gc *rg = to_mediatek_gpio(chip: gc); |
133 | int pin = d->hwirq; |
134 | unsigned long flags; |
135 | u32 rise, fall, high, low; |
136 | |
137 | spin_lock_irqsave(&rg->lock, flags); |
138 | rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); |
139 | fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); |
140 | high = mtk_gpio_r32(rg, GPIO_REG_HLVL); |
141 | low = mtk_gpio_r32(rg, GPIO_REG_LLVL); |
142 | mtk_gpio_w32(rg, GPIO_REG_FEDGE, val: fall & ~BIT(pin)); |
143 | mtk_gpio_w32(rg, GPIO_REG_REDGE, val: rise & ~BIT(pin)); |
144 | mtk_gpio_w32(rg, GPIO_REG_HLVL, val: high & ~BIT(pin)); |
145 | mtk_gpio_w32(rg, GPIO_REG_LLVL, val: low & ~BIT(pin)); |
146 | spin_unlock_irqrestore(lock: &rg->lock, flags); |
147 | |
148 | gpiochip_disable_irq(gc, offset: d->hwirq); |
149 | } |
150 | |
151 | static int |
152 | mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) |
153 | { |
154 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
155 | struct mtk_gc *rg = to_mediatek_gpio(chip: gc); |
156 | int pin = d->hwirq; |
157 | u32 mask = BIT(pin); |
158 | |
159 | if (type == IRQ_TYPE_PROBE) { |
160 | if ((rg->rising | rg->falling | |
161 | rg->hlevel | rg->llevel) & mask) |
162 | return 0; |
163 | |
164 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
165 | } |
166 | |
167 | rg->rising &= ~mask; |
168 | rg->falling &= ~mask; |
169 | rg->hlevel &= ~mask; |
170 | rg->llevel &= ~mask; |
171 | |
172 | switch (type & IRQ_TYPE_SENSE_MASK) { |
173 | case IRQ_TYPE_EDGE_BOTH: |
174 | rg->rising |= mask; |
175 | rg->falling |= mask; |
176 | break; |
177 | case IRQ_TYPE_EDGE_RISING: |
178 | rg->rising |= mask; |
179 | break; |
180 | case IRQ_TYPE_EDGE_FALLING: |
181 | rg->falling |= mask; |
182 | break; |
183 | case IRQ_TYPE_LEVEL_HIGH: |
184 | rg->hlevel |= mask; |
185 | break; |
186 | case IRQ_TYPE_LEVEL_LOW: |
187 | rg->llevel |= mask; |
188 | break; |
189 | } |
190 | |
191 | return 0; |
192 | } |
193 | |
194 | static int |
195 | mediatek_gpio_xlate(struct gpio_chip *chip, |
196 | const struct of_phandle_args *spec, u32 *flags) |
197 | { |
198 | int gpio = spec->args[0]; |
199 | struct mtk_gc *rg = to_mediatek_gpio(chip); |
200 | |
201 | if (rg->bank != gpio / MTK_BANK_WIDTH) |
202 | return -EINVAL; |
203 | |
204 | if (flags) |
205 | *flags = spec->args[1]; |
206 | |
207 | return gpio % MTK_BANK_WIDTH; |
208 | } |
209 | |
210 | static const struct irq_chip mt7621_irq_chip = { |
211 | .name = "mt7621-gpio" , |
212 | .irq_mask_ack = mediatek_gpio_irq_mask, |
213 | .irq_mask = mediatek_gpio_irq_mask, |
214 | .irq_unmask = mediatek_gpio_irq_unmask, |
215 | .irq_set_type = mediatek_gpio_irq_type, |
216 | .flags = IRQCHIP_IMMUTABLE, |
217 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
218 | }; |
219 | |
220 | static int |
221 | mediatek_gpio_bank_probe(struct device *dev, int bank) |
222 | { |
223 | struct mtk *mtk = dev_get_drvdata(dev); |
224 | struct mtk_gc *rg; |
225 | void __iomem *dat, *set, *ctrl, *diro; |
226 | int ret; |
227 | |
228 | rg = &mtk->gc_map[bank]; |
229 | memset(rg, 0, sizeof(*rg)); |
230 | |
231 | spin_lock_init(&rg->lock); |
232 | rg->bank = bank; |
233 | |
234 | dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); |
235 | set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); |
236 | ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); |
237 | diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); |
238 | |
239 | ret = bgpio_init(gc: &rg->chip, dev, sz: 4, dat, set, clr: ctrl, dirout: diro, NULL, |
240 | BGPIOF_NO_SET_ON_INPUT); |
241 | if (ret) { |
242 | dev_err(dev, "bgpio_init() failed\n" ); |
243 | return ret; |
244 | } |
245 | |
246 | rg->chip.of_gpio_n_cells = 2; |
247 | rg->chip.of_xlate = mediatek_gpio_xlate; |
248 | rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, fmt: "%s-bank%d" , |
249 | dev_name(dev), bank); |
250 | if (!rg->chip.label) |
251 | return -ENOMEM; |
252 | |
253 | rg->chip.offset = bank * MTK_BANK_WIDTH; |
254 | |
255 | if (mtk->gpio_irq) { |
256 | struct gpio_irq_chip *girq; |
257 | |
258 | /* |
259 | * Directly request the irq here instead of passing |
260 | * a flow-handler because the irq is shared. |
261 | */ |
262 | ret = devm_request_irq(dev, irq: mtk->gpio_irq, |
263 | handler: mediatek_gpio_irq_handler, IRQF_SHARED, |
264 | devname: rg->chip.label, dev_id: &rg->chip); |
265 | |
266 | if (ret) { |
267 | dev_err(dev, "Error requesting IRQ %d: %d\n" , |
268 | mtk->gpio_irq, ret); |
269 | return ret; |
270 | } |
271 | |
272 | girq = &rg->chip.irq; |
273 | gpio_irq_chip_set_chip(girq, chip: &mt7621_irq_chip); |
274 | /* This will let us handle the parent IRQ in the driver */ |
275 | girq->parent_handler = NULL; |
276 | girq->num_parents = 0; |
277 | girq->parents = NULL; |
278 | girq->default_type = IRQ_TYPE_NONE; |
279 | girq->handler = handle_simple_irq; |
280 | } |
281 | |
282 | ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); |
283 | if (ret < 0) { |
284 | dev_err(dev, "Could not register gpio %d, ret=%d\n" , |
285 | rg->chip.ngpio, ret); |
286 | return ret; |
287 | } |
288 | |
289 | /* set polarity to low for all gpios */ |
290 | mtk_gpio_w32(rg, GPIO_REG_POL, val: 0); |
291 | |
292 | dev_info(dev, "registering %d gpios\n" , rg->chip.ngpio); |
293 | |
294 | return 0; |
295 | } |
296 | |
297 | static int |
298 | mediatek_gpio_probe(struct platform_device *pdev) |
299 | { |
300 | struct device *dev = &pdev->dev; |
301 | struct mtk *mtk; |
302 | int i; |
303 | int ret; |
304 | |
305 | mtk = devm_kzalloc(dev, size: sizeof(*mtk), GFP_KERNEL); |
306 | if (!mtk) |
307 | return -ENOMEM; |
308 | |
309 | mtk->base = devm_platform_ioremap_resource(pdev, index: 0); |
310 | if (IS_ERR(ptr: mtk->base)) |
311 | return PTR_ERR(ptr: mtk->base); |
312 | |
313 | mtk->gpio_irq = platform_get_irq(pdev, 0); |
314 | if (mtk->gpio_irq < 0) |
315 | return mtk->gpio_irq; |
316 | |
317 | mtk->dev = dev; |
318 | platform_set_drvdata(pdev, data: mtk); |
319 | |
320 | for (i = 0; i < MTK_BANK_CNT; i++) { |
321 | ret = mediatek_gpio_bank_probe(dev, bank: i); |
322 | if (ret) |
323 | return ret; |
324 | } |
325 | |
326 | return 0; |
327 | } |
328 | |
329 | static const struct of_device_id mediatek_gpio_match[] = { |
330 | { .compatible = "mediatek,mt7621-gpio" }, |
331 | {}, |
332 | }; |
333 | MODULE_DEVICE_TABLE(of, mediatek_gpio_match); |
334 | |
335 | static struct platform_driver mediatek_gpio_driver = { |
336 | .probe = mediatek_gpio_probe, |
337 | .driver = { |
338 | .name = "mt7621_gpio" , |
339 | .of_match_table = mediatek_gpio_match, |
340 | }, |
341 | }; |
342 | |
343 | builtin_platform_driver(mediatek_gpio_driver); |
344 | |