1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for Marvell SoCs
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * Andrew Lunn <andrew@lunn.ch>
9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 *
11 * This driver is a fairly straightforward GPIO driver for the
12 * complete family of Marvell EBU SoC platforms (Orion, Dove,
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
14 * driver is the different register layout that exists between the
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
18 * block:
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
25 * registers.
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
30 * interrupts.
31 */
32
33#include <linux/bitops.h>
34#include <linux/clk.h>
35#include <linux/err.h>
36#include <linux/gpio/driver.h>
37#include <linux/gpio/consumer.h>
38#include <linux/gpio/machine.h>
39#include <linux/init.h>
40#include <linux/io.h>
41#include <linux/irq.h>
42#include <linux/irqchip/chained_irq.h>
43#include <linux/irqdomain.h>
44#include <linux/mfd/syscon.h>
45#include <linux/of.h>
46#include <linux/pinctrl/consumer.h>
47#include <linux/platform_device.h>
48#include <linux/property.h>
49#include <linux/pwm.h>
50#include <linux/regmap.h>
51#include <linux/slab.h>
52
53/*
54 * GPIO unit register offsets.
55 */
56#define GPIO_OUT_OFF 0x0000
57#define GPIO_IO_CONF_OFF 0x0004
58#define GPIO_BLINK_EN_OFF 0x0008
59#define GPIO_IN_POL_OFF 0x000c
60#define GPIO_DATA_IN_OFF 0x0010
61#define GPIO_EDGE_CAUSE_OFF 0x0014
62#define GPIO_EDGE_MASK_OFF 0x0018
63#define GPIO_LEVEL_MASK_OFF 0x001c
64#define GPIO_BLINK_CNT_SELECT_OFF 0x0020
65
66/*
67 * PWM register offsets.
68 */
69#define PWM_BLINK_ON_DURATION_OFF 0x0
70#define PWM_BLINK_OFF_DURATION_OFF 0x4
71#define PWM_BLINK_COUNTER_B_OFF 0x8
72
73/* Armada 8k variant gpios register offsets */
74#define AP80X_GPIO0_OFF_A8K 0x1040
75#define CP11X_GPIO0_OFF_A8K 0x100
76#define CP11X_GPIO1_OFF_A8K 0x140
77
78/* The MV78200 has per-CPU registers for edge mask and level mask */
79#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
80#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
81
82/*
83 * The Armada XP has per-CPU registers for interrupt cause, interrupt
84 * mask and interrupt level mask. Those are in percpu_regs range.
85 */
86#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
87#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
88#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
89
90#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
91#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
92#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
93#define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
94
95#define MVEBU_MAX_GPIO_PER_BANK 32
96
97struct mvebu_pwm {
98 struct regmap *regs;
99 u32 offset;
100 unsigned long clk_rate;
101 struct gpio_desc *gpiod;
102 struct pwm_chip chip;
103 spinlock_t lock;
104 struct mvebu_gpio_chip *mvchip;
105
106 /* Used to preserve GPIO/PWM registers across suspend/resume */
107 u32 blink_select;
108 u32 blink_on_duration;
109 u32 blink_off_duration;
110};
111
112struct mvebu_gpio_chip {
113 struct gpio_chip chip;
114 struct regmap *regs;
115 u32 offset;
116 struct regmap *percpu_regs;
117 int irqbase;
118 struct irq_domain *domain;
119 int soc_variant;
120
121 /* Used for PWM support */
122 struct clk *clk;
123 struct mvebu_pwm *mvpwm;
124
125 /* Used to preserve GPIO registers across suspend/resume */
126 u32 out_reg;
127 u32 io_conf_reg;
128 u32 blink_en_reg;
129 u32 in_pol_reg;
130 u32 edge_mask_regs[4];
131 u32 level_mask_regs[4];
132};
133
134/*
135 * Functions returning addresses of individual registers for a given
136 * GPIO controller.
137 */
138
139static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
140 struct regmap **map, unsigned int *offset)
141{
142 int cpu;
143
144 switch (mvchip->soc_variant) {
145 case MVEBU_GPIO_SOC_VARIANT_ORION:
146 case MVEBU_GPIO_SOC_VARIANT_MV78200:
147 case MVEBU_GPIO_SOC_VARIANT_A8K:
148 *map = mvchip->regs;
149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
150 break;
151 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
152 cpu = smp_processor_id();
153 *map = mvchip->percpu_regs;
154 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
155 break;
156 default:
157 BUG();
158 }
159}
160
161static u32
162mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
163{
164 struct regmap *map;
165 unsigned int offset;
166 u32 val;
167
168 mvebu_gpioreg_edge_cause(mvchip, map: &map, offset: &offset);
169 regmap_read(map, reg: offset, val: &val);
170
171 return val;
172}
173
174static void
175mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
176{
177 struct regmap *map;
178 unsigned int offset;
179
180 mvebu_gpioreg_edge_cause(mvchip, map: &map, offset: &offset);
181 regmap_write(map, reg: offset, val);
182}
183
184static inline void
185mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
186 struct regmap **map, unsigned int *offset)
187{
188 int cpu;
189
190 switch (mvchip->soc_variant) {
191 case MVEBU_GPIO_SOC_VARIANT_ORION:
192 case MVEBU_GPIO_SOC_VARIANT_A8K:
193 *map = mvchip->regs;
194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
195 break;
196 case MVEBU_GPIO_SOC_VARIANT_MV78200:
197 cpu = smp_processor_id();
198 *map = mvchip->regs;
199 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
200 break;
201 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
202 cpu = smp_processor_id();
203 *map = mvchip->percpu_regs;
204 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
205 break;
206 default:
207 BUG();
208 }
209}
210
211static u32
212mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
213{
214 struct regmap *map;
215 unsigned int offset;
216 u32 val;
217
218 mvebu_gpioreg_edge_mask(mvchip, map: &map, offset: &offset);
219 regmap_read(map, reg: offset, val: &val);
220
221 return val;
222}
223
224static void
225mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
226{
227 struct regmap *map;
228 unsigned int offset;
229
230 mvebu_gpioreg_edge_mask(mvchip, map: &map, offset: &offset);
231 regmap_write(map, reg: offset, val);
232}
233
234static void
235mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
236 struct regmap **map, unsigned int *offset)
237{
238 int cpu;
239
240 switch (mvchip->soc_variant) {
241 case MVEBU_GPIO_SOC_VARIANT_ORION:
242 case MVEBU_GPIO_SOC_VARIANT_A8K:
243 *map = mvchip->regs;
244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
245 break;
246 case MVEBU_GPIO_SOC_VARIANT_MV78200:
247 cpu = smp_processor_id();
248 *map = mvchip->regs;
249 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
250 break;
251 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
252 cpu = smp_processor_id();
253 *map = mvchip->percpu_regs;
254 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
255 break;
256 default:
257 BUG();
258 }
259}
260
261static u32
262mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
263{
264 struct regmap *map;
265 unsigned int offset;
266 u32 val;
267
268 mvebu_gpioreg_level_mask(mvchip, map: &map, offset: &offset);
269 regmap_read(map, reg: offset, val: &val);
270
271 return val;
272}
273
274static void
275mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
276{
277 struct regmap *map;
278 unsigned int offset;
279
280 mvebu_gpioreg_level_mask(mvchip, map: &map, offset: &offset);
281 regmap_write(map, reg: offset, val);
282}
283
284/*
285 * Functions returning offsets of individual registers for a given
286 * PWM controller.
287 */
288static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
289{
290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
291}
292
293static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
294{
295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
296}
297
298/*
299 * Functions implementing the gpio_chip methods
300 */
301static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
302{
303 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
304
305 regmap_update_bits(map: mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
306 BIT(pin), val: value ? BIT(pin) : 0);
307}
308
309static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
310{
311 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
312 u32 u;
313
314 regmap_read(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, val: &u);
315
316 if (u & BIT(pin)) {
317 u32 data_in, in_pol;
318
319 regmap_read(map: mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
320 val: &data_in);
321 regmap_read(map: mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
322 val: &in_pol);
323 u = data_in ^ in_pol;
324 } else {
325 regmap_read(map: mvchip->regs, GPIO_OUT_OFF + mvchip->offset, val: &u);
326 }
327
328 return (u >> pin) & 1;
329}
330
331static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
332 int value)
333{
334 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
335
336 regmap_update_bits(map: mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
337 BIT(pin), val: value ? BIT(pin) : 0);
338}
339
340static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
341{
342 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
343 int ret;
344
345 /*
346 * Check with the pinctrl driver whether this pin is usable as
347 * an input GPIO
348 */
349 ret = pinctrl_gpio_direction_input(gc: chip, offset: pin);
350 if (ret)
351 return ret;
352
353 regmap_update_bits(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
354 BIT(pin), BIT(pin));
355
356 return 0;
357}
358
359static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
360 int value)
361{
362 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
363 int ret;
364
365 /*
366 * Check with the pinctrl driver whether this pin is usable as
367 * an output GPIO
368 */
369 ret = pinctrl_gpio_direction_output(gc: chip, offset: pin);
370 if (ret)
371 return ret;
372
373 mvebu_gpio_blink(chip, pin, value: 0);
374 mvebu_gpio_set(chip, pin, value);
375
376 regmap_update_bits(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
377 BIT(pin), val: 0);
378
379 return 0;
380}
381
382static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
383{
384 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
385 u32 u;
386
387 regmap_read(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, val: &u);
388
389 if (u & BIT(pin))
390 return GPIO_LINE_DIRECTION_IN;
391
392 return GPIO_LINE_DIRECTION_OUT;
393}
394
395static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
396{
397 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
398
399 return irq_create_mapping(host: mvchip->domain, hwirq: pin);
400}
401
402/*
403 * Functions implementing the irq_chip methods
404 */
405static void mvebu_gpio_irq_ack(struct irq_data *d)
406{
407 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
408 struct mvebu_gpio_chip *mvchip = gc->private;
409 u32 mask = d->mask;
410
411 irq_gc_lock(gc);
412 mvebu_gpio_write_edge_cause(mvchip, val: ~mask);
413 irq_gc_unlock(gc);
414}
415
416static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
417{
418 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
419 struct mvebu_gpio_chip *mvchip = gc->private;
420 struct irq_chip_type *ct = irq_data_get_chip_type(d);
421 u32 mask = d->mask;
422
423 irq_gc_lock(gc);
424 ct->mask_cache_priv &= ~mask;
425 mvebu_gpio_write_edge_mask(mvchip, val: ct->mask_cache_priv);
426 irq_gc_unlock(gc);
427}
428
429static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
430{
431 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
432 struct mvebu_gpio_chip *mvchip = gc->private;
433 struct irq_chip_type *ct = irq_data_get_chip_type(d);
434 u32 mask = d->mask;
435
436 irq_gc_lock(gc);
437 mvebu_gpio_write_edge_cause(mvchip, val: ~mask);
438 ct->mask_cache_priv |= mask;
439 mvebu_gpio_write_edge_mask(mvchip, val: ct->mask_cache_priv);
440 irq_gc_unlock(gc);
441}
442
443static void mvebu_gpio_level_irq_mask(struct irq_data *d)
444{
445 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
446 struct mvebu_gpio_chip *mvchip = gc->private;
447 struct irq_chip_type *ct = irq_data_get_chip_type(d);
448 u32 mask = d->mask;
449
450 irq_gc_lock(gc);
451 ct->mask_cache_priv &= ~mask;
452 mvebu_gpio_write_level_mask(mvchip, val: ct->mask_cache_priv);
453 irq_gc_unlock(gc);
454}
455
456static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
457{
458 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
459 struct mvebu_gpio_chip *mvchip = gc->private;
460 struct irq_chip_type *ct = irq_data_get_chip_type(d);
461 u32 mask = d->mask;
462
463 irq_gc_lock(gc);
464 ct->mask_cache_priv |= mask;
465 mvebu_gpio_write_level_mask(mvchip, val: ct->mask_cache_priv);
466 irq_gc_unlock(gc);
467}
468
469/*****************************************************************************
470 * MVEBU GPIO IRQ
471 *
472 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
473 * value of the line or the opposite value.
474 *
475 * Level IRQ handlers: DATA_IN is used directly as cause register.
476 * Interrupt are masked by LEVEL_MASK registers.
477 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
478 * Interrupt are masked by EDGE_MASK registers.
479 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
480 * the polarity to catch the next line transaction.
481 * This is a race condition that might not perfectly
482 * work on some use cases.
483 *
484 * Every eight GPIO lines are grouped (OR'ed) before going up to main
485 * cause register.
486 *
487 * EDGE cause mask
488 * data-in /--------| |-----| |----\
489 * -----| |----- ---- to main cause reg
490 * X \----------------| |----/
491 * polarity LEVEL mask
492 *
493 ****************************************************************************/
494
495static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
496{
497 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498 struct irq_chip_type *ct = irq_data_get_chip_type(d);
499 struct mvebu_gpio_chip *mvchip = gc->private;
500 int pin;
501 u32 u;
502
503 pin = d->hwirq;
504
505 regmap_read(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, val: &u);
506 if ((u & BIT(pin)) == 0)
507 return -EINVAL;
508
509 type &= IRQ_TYPE_SENSE_MASK;
510 if (type == IRQ_TYPE_NONE)
511 return -EINVAL;
512
513 /* Check if we need to change chip and handler */
514 if (!(ct->type & type))
515 if (irq_setup_alt_chip(d, type))
516 return -EINVAL;
517
518 /*
519 * Configure interrupt polarity.
520 */
521 switch (type) {
522 case IRQ_TYPE_EDGE_RISING:
523 case IRQ_TYPE_LEVEL_HIGH:
524 regmap_update_bits(map: mvchip->regs,
525 GPIO_IN_POL_OFF + mvchip->offset,
526 BIT(pin), val: 0);
527 break;
528 case IRQ_TYPE_EDGE_FALLING:
529 case IRQ_TYPE_LEVEL_LOW:
530 regmap_update_bits(map: mvchip->regs,
531 GPIO_IN_POL_OFF + mvchip->offset,
532 BIT(pin), BIT(pin));
533 break;
534 case IRQ_TYPE_EDGE_BOTH: {
535 u32 data_in, in_pol, val;
536
537 regmap_read(map: mvchip->regs,
538 GPIO_IN_POL_OFF + mvchip->offset, val: &in_pol);
539 regmap_read(map: mvchip->regs,
540 GPIO_DATA_IN_OFF + mvchip->offset, val: &data_in);
541
542 /*
543 * set initial polarity based on current input level
544 */
545 if ((data_in ^ in_pol) & BIT(pin))
546 val = BIT(pin); /* falling */
547 else
548 val = 0; /* raising */
549
550 regmap_update_bits(map: mvchip->regs,
551 GPIO_IN_POL_OFF + mvchip->offset,
552 BIT(pin), val);
553 break;
554 }
555 }
556 return 0;
557}
558
559static void mvebu_gpio_irq_handler(struct irq_desc *desc)
560{
561 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
562 struct irq_chip *chip = irq_desc_get_chip(desc);
563 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
564 int i;
565
566 if (mvchip == NULL)
567 return;
568
569 chained_irq_enter(chip, desc);
570
571 regmap_read(map: mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, val: &data_in);
572 level_mask = mvebu_gpio_read_level_mask(mvchip);
573 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
574 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
575
576 cause = (data_in & level_mask) | (edge_cause & edge_mask);
577
578 for (i = 0; i < mvchip->chip.ngpio; i++) {
579 int irq;
580
581 irq = irq_find_mapping(domain: mvchip->domain, hwirq: i);
582
583 if (!(cause & BIT(i)))
584 continue;
585
586 type = irq_get_trigger_type(irq);
587 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
588 /* Swap polarity (race with GPIO line) */
589 u32 polarity;
590
591 regmap_read(map: mvchip->regs,
592 GPIO_IN_POL_OFF + mvchip->offset,
593 val: &polarity);
594 polarity ^= BIT(i);
595 regmap_write(map: mvchip->regs,
596 GPIO_IN_POL_OFF + mvchip->offset,
597 val: polarity);
598 }
599
600 generic_handle_irq(irq);
601 }
602
603 chained_irq_exit(chip, desc);
604}
605
606static const struct regmap_config mvebu_gpio_regmap_config = {
607 .reg_bits = 32,
608 .reg_stride = 4,
609 .val_bits = 32,
610 .fast_io = true,
611};
612
613/*
614 * Functions implementing the pwm_chip methods
615 */
616static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
617{
618 return container_of(chip, struct mvebu_pwm, chip);
619}
620
621static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
622{
623 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
624 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
625 struct gpio_desc *desc;
626 unsigned long flags;
627 int ret = 0;
628
629 spin_lock_irqsave(&mvpwm->lock, flags);
630
631 if (mvpwm->gpiod) {
632 ret = -EBUSY;
633 } else {
634 desc = gpiochip_request_own_desc(gc: &mvchip->chip,
635 hwnum: pwm->hwpwm, label: "mvebu-pwm",
636 lflags: GPIO_ACTIVE_HIGH,
637 dflags: GPIOD_OUT_LOW);
638 if (IS_ERR(ptr: desc)) {
639 ret = PTR_ERR(ptr: desc);
640 goto out;
641 }
642
643 mvpwm->gpiod = desc;
644 }
645out:
646 spin_unlock_irqrestore(lock: &mvpwm->lock, flags);
647 return ret;
648}
649
650static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
651{
652 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
653 unsigned long flags;
654
655 spin_lock_irqsave(&mvpwm->lock, flags);
656 gpiochip_free_own_desc(desc: mvpwm->gpiod);
657 mvpwm->gpiod = NULL;
658 spin_unlock_irqrestore(lock: &mvpwm->lock, flags);
659}
660
661static int mvebu_pwm_get_state(struct pwm_chip *chip,
662 struct pwm_device *pwm,
663 struct pwm_state *state)
664{
665
666 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
667 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
668 unsigned long long val;
669 unsigned long flags;
670 u32 u;
671
672 spin_lock_irqsave(&mvpwm->lock, flags);
673
674 regmap_read(map: mvpwm->regs, reg: mvebu_pwmreg_blink_on_duration(mvpwm), val: &u);
675 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
676 if (u > 0)
677 val = u;
678 else
679 val = UINT_MAX + 1ULL;
680 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
681 mvpwm->clk_rate);
682
683 regmap_read(map: mvpwm->regs, reg: mvebu_pwmreg_blink_off_duration(mvpwm), val: &u);
684 /* period = on + off duration */
685 if (u > 0)
686 val += u;
687 else
688 val += UINT_MAX + 1ULL;
689 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
690
691 regmap_read(map: mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, val: &u);
692 if (u)
693 state->enabled = true;
694 else
695 state->enabled = false;
696
697 spin_unlock_irqrestore(lock: &mvpwm->lock, flags);
698
699 return 0;
700}
701
702static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
703 const struct pwm_state *state)
704{
705 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
706 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
707 unsigned long long val;
708 unsigned long flags;
709 unsigned int on, off;
710
711 if (state->polarity != PWM_POLARITY_NORMAL)
712 return -EINVAL;
713
714 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
715 do_div(val, NSEC_PER_SEC);
716 if (val > UINT_MAX + 1ULL)
717 return -EINVAL;
718 /*
719 * Zero on/off values don't work as expected. Experimentation shows
720 * that zero value is treated as 2^32. This behavior is not documented.
721 */
722 if (val == UINT_MAX + 1ULL)
723 on = 0;
724 else if (val)
725 on = val;
726 else
727 on = 1;
728
729 val = (unsigned long long) mvpwm->clk_rate * state->period;
730 do_div(val, NSEC_PER_SEC);
731 val -= on;
732 if (val > UINT_MAX + 1ULL)
733 return -EINVAL;
734 if (val == UINT_MAX + 1ULL)
735 off = 0;
736 else if (val)
737 off = val;
738 else
739 off = 1;
740
741 spin_lock_irqsave(&mvpwm->lock, flags);
742
743 regmap_write(map: mvpwm->regs, reg: mvebu_pwmreg_blink_on_duration(mvpwm), val: on);
744 regmap_write(map: mvpwm->regs, reg: mvebu_pwmreg_blink_off_duration(mvpwm), val: off);
745 if (state->enabled)
746 mvebu_gpio_blink(chip: &mvchip->chip, pin: pwm->hwpwm, value: 1);
747 else
748 mvebu_gpio_blink(chip: &mvchip->chip, pin: pwm->hwpwm, value: 0);
749
750 spin_unlock_irqrestore(lock: &mvpwm->lock, flags);
751
752 return 0;
753}
754
755static const struct pwm_ops mvebu_pwm_ops = {
756 .request = mvebu_pwm_request,
757 .free = mvebu_pwm_free,
758 .get_state = mvebu_pwm_get_state,
759 .apply = mvebu_pwm_apply,
760 .owner = THIS_MODULE,
761};
762
763static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
764{
765 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
766
767 regmap_read(map: mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
768 val: &mvpwm->blink_select);
769 regmap_read(map: mvpwm->regs, reg: mvebu_pwmreg_blink_on_duration(mvpwm),
770 val: &mvpwm->blink_on_duration);
771 regmap_read(map: mvpwm->regs, reg: mvebu_pwmreg_blink_off_duration(mvpwm),
772 val: &mvpwm->blink_off_duration);
773}
774
775static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
776{
777 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
778
779 regmap_write(map: mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
780 val: mvpwm->blink_select);
781 regmap_write(map: mvpwm->regs, reg: mvebu_pwmreg_blink_on_duration(mvpwm),
782 val: mvpwm->blink_on_duration);
783 regmap_write(map: mvpwm->regs, reg: mvebu_pwmreg_blink_off_duration(mvpwm),
784 val: mvpwm->blink_off_duration);
785}
786
787static int mvebu_pwm_probe(struct platform_device *pdev,
788 struct mvebu_gpio_chip *mvchip,
789 int id)
790{
791 struct device *dev = &pdev->dev;
792 struct mvebu_pwm *mvpwm;
793 void __iomem *base;
794 u32 offset;
795 u32 set;
796
797 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
798 int ret = of_property_read_u32(np: dev->of_node,
799 propname: "marvell,pwm-offset", out_value: &offset);
800 if (ret < 0)
801 return 0;
802 } else {
803 /*
804 * There are only two sets of PWM configuration registers for
805 * all the GPIO lines on those SoCs which this driver reserves
806 * for the first two GPIO chips. So if the resource is missing
807 * we can't treat it as an error.
808 */
809 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
810 return 0;
811 offset = 0;
812 }
813
814 if (IS_ERR(ptr: mvchip->clk))
815 return PTR_ERR(ptr: mvchip->clk);
816
817 mvpwm = devm_kzalloc(dev, size: sizeof(struct mvebu_pwm), GFP_KERNEL);
818 if (!mvpwm)
819 return -ENOMEM;
820 mvchip->mvpwm = mvpwm;
821 mvpwm->mvchip = mvchip;
822 mvpwm->offset = offset;
823
824 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
825 mvpwm->regs = mvchip->regs;
826
827 switch (mvchip->offset) {
828 case AP80X_GPIO0_OFF_A8K:
829 case CP11X_GPIO0_OFF_A8K:
830 /* Blink counter A */
831 set = 0;
832 break;
833 case CP11X_GPIO1_OFF_A8K:
834 /* Blink counter B */
835 set = U32_MAX;
836 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
837 break;
838 default:
839 return -EINVAL;
840 }
841 } else {
842 base = devm_platform_ioremap_resource_byname(pdev, name: "pwm");
843 if (IS_ERR(ptr: base))
844 return PTR_ERR(ptr: base);
845
846 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
847 &mvebu_gpio_regmap_config);
848 if (IS_ERR(ptr: mvpwm->regs))
849 return PTR_ERR(ptr: mvpwm->regs);
850
851 /*
852 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
853 * with id 1. Don't allow further GPIO chips to be used for PWM.
854 */
855 if (id == 0)
856 set = 0;
857 else if (id == 1)
858 set = U32_MAX;
859 else
860 return -EINVAL;
861 }
862
863 regmap_write(map: mvchip->regs,
864 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, val: set);
865
866 mvpwm->clk_rate = clk_get_rate(clk: mvchip->clk);
867 if (!mvpwm->clk_rate) {
868 dev_err(dev, "failed to get clock rate\n");
869 return -EINVAL;
870 }
871
872 mvpwm->chip.dev = dev;
873 mvpwm->chip.ops = &mvebu_pwm_ops;
874 mvpwm->chip.npwm = mvchip->chip.ngpio;
875
876 spin_lock_init(&mvpwm->lock);
877
878 return devm_pwmchip_add(dev, chip: &mvpwm->chip);
879}
880
881#ifdef CONFIG_DEBUG_FS
882#include <linux/seq_file.h>
883
884static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
885{
886 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(gc: chip);
887 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
888 const char *label;
889 int i;
890
891 regmap_read(map: mvchip->regs, GPIO_OUT_OFF + mvchip->offset, val: &out);
892 regmap_read(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, val: &io_conf);
893 regmap_read(map: mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, val: &blink);
894 regmap_read(map: mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, val: &in_pol);
895 regmap_read(map: mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, val: &data_in);
896 cause = mvebu_gpio_read_edge_cause(mvchip);
897 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
898 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
899
900 for_each_requested_gpio(chip, i, label) {
901 u32 msk;
902 bool is_out;
903
904 msk = BIT(i);
905 is_out = !(io_conf & msk);
906
907 seq_printf(m: s, fmt: " gpio-%-3d (%-20.20s)", chip->base + i, label);
908
909 if (is_out) {
910 seq_printf(m: s, fmt: " out %s %s\n",
911 out & msk ? "hi" : "lo",
912 blink & msk ? "(blink )" : "");
913 continue;
914 }
915
916 seq_printf(m: s, fmt: " in %s (act %s) - IRQ",
917 (data_in ^ in_pol) & msk ? "hi" : "lo",
918 in_pol & msk ? "lo" : "hi");
919 if (!((edg_msk | lvl_msk) & msk)) {
920 seq_puts(m: s, s: " disabled\n");
921 continue;
922 }
923 if (edg_msk & msk)
924 seq_puts(m: s, s: " edge ");
925 if (lvl_msk & msk)
926 seq_puts(m: s, s: " level");
927 seq_printf(m: s, fmt: " (%s)\n", cause & msk ? "pending" : "clear ");
928 }
929}
930#else
931#define mvebu_gpio_dbg_show NULL
932#endif
933
934static const struct of_device_id mvebu_gpio_of_match[] = {
935 {
936 .compatible = "marvell,orion-gpio",
937 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
938 },
939 {
940 .compatible = "marvell,mv78200-gpio",
941 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
942 },
943 {
944 .compatible = "marvell,armadaxp-gpio",
945 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
946 },
947 {
948 .compatible = "marvell,armada-370-gpio",
949 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
950 },
951 {
952 .compatible = "marvell,armada-8k-gpio",
953 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
954 },
955 {
956 /* sentinel */
957 },
958};
959
960static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
961{
962 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
963 int i;
964
965 regmap_read(map: mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
966 val: &mvchip->out_reg);
967 regmap_read(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
968 val: &mvchip->io_conf_reg);
969 regmap_read(map: mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
970 val: &mvchip->blink_en_reg);
971 regmap_read(map: mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
972 val: &mvchip->in_pol_reg);
973
974 switch (mvchip->soc_variant) {
975 case MVEBU_GPIO_SOC_VARIANT_ORION:
976 case MVEBU_GPIO_SOC_VARIANT_A8K:
977 regmap_read(map: mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
978 val: &mvchip->edge_mask_regs[0]);
979 regmap_read(map: mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
980 val: &mvchip->level_mask_regs[0]);
981 break;
982 case MVEBU_GPIO_SOC_VARIANT_MV78200:
983 for (i = 0; i < 2; i++) {
984 regmap_read(map: mvchip->regs,
985 GPIO_EDGE_MASK_MV78200_OFF(i),
986 val: &mvchip->edge_mask_regs[i]);
987 regmap_read(map: mvchip->regs,
988 GPIO_LEVEL_MASK_MV78200_OFF(i),
989 val: &mvchip->level_mask_regs[i]);
990 }
991 break;
992 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
993 for (i = 0; i < 4; i++) {
994 regmap_read(map: mvchip->regs,
995 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
996 val: &mvchip->edge_mask_regs[i]);
997 regmap_read(map: mvchip->regs,
998 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
999 val: &mvchip->level_mask_regs[i]);
1000 }
1001 break;
1002 default:
1003 BUG();
1004 }
1005
1006 if (IS_REACHABLE(CONFIG_PWM))
1007 mvebu_pwm_suspend(mvchip);
1008
1009 return 0;
1010}
1011
1012static int mvebu_gpio_resume(struct platform_device *pdev)
1013{
1014 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1015 int i;
1016
1017 regmap_write(map: mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1018 val: mvchip->out_reg);
1019 regmap_write(map: mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1020 val: mvchip->io_conf_reg);
1021 regmap_write(map: mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1022 val: mvchip->blink_en_reg);
1023 regmap_write(map: mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1024 val: mvchip->in_pol_reg);
1025
1026 switch (mvchip->soc_variant) {
1027 case MVEBU_GPIO_SOC_VARIANT_ORION:
1028 case MVEBU_GPIO_SOC_VARIANT_A8K:
1029 regmap_write(map: mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1030 val: mvchip->edge_mask_regs[0]);
1031 regmap_write(map: mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1032 val: mvchip->level_mask_regs[0]);
1033 break;
1034 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1035 for (i = 0; i < 2; i++) {
1036 regmap_write(map: mvchip->regs,
1037 GPIO_EDGE_MASK_MV78200_OFF(i),
1038 val: mvchip->edge_mask_regs[i]);
1039 regmap_write(map: mvchip->regs,
1040 GPIO_LEVEL_MASK_MV78200_OFF(i),
1041 val: mvchip->level_mask_regs[i]);
1042 }
1043 break;
1044 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1045 for (i = 0; i < 4; i++) {
1046 regmap_write(map: mvchip->regs,
1047 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1048 val: mvchip->edge_mask_regs[i]);
1049 regmap_write(map: mvchip->regs,
1050 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1051 val: mvchip->level_mask_regs[i]);
1052 }
1053 break;
1054 default:
1055 BUG();
1056 }
1057
1058 if (IS_REACHABLE(CONFIG_PWM))
1059 mvebu_pwm_resume(mvchip);
1060
1061 return 0;
1062}
1063
1064static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1065 struct mvebu_gpio_chip *mvchip)
1066{
1067 void __iomem *base;
1068
1069 base = devm_platform_ioremap_resource(pdev, index: 0);
1070 if (IS_ERR(ptr: base))
1071 return PTR_ERR(ptr: base);
1072
1073 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1074 &mvebu_gpio_regmap_config);
1075 if (IS_ERR(ptr: mvchip->regs))
1076 return PTR_ERR(ptr: mvchip->regs);
1077
1078 /*
1079 * For the legacy SoCs, the regmap directly maps to the GPIO
1080 * registers, so no offset is needed.
1081 */
1082 mvchip->offset = 0;
1083
1084 /*
1085 * The Armada XP has a second range of registers for the
1086 * per-CPU registers
1087 */
1088 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1089 base = devm_platform_ioremap_resource(pdev, index: 1);
1090 if (IS_ERR(ptr: base))
1091 return PTR_ERR(ptr: base);
1092
1093 mvchip->percpu_regs =
1094 devm_regmap_init_mmio(&pdev->dev, base,
1095 &mvebu_gpio_regmap_config);
1096 if (IS_ERR(ptr: mvchip->percpu_regs))
1097 return PTR_ERR(ptr: mvchip->percpu_regs);
1098 }
1099
1100 return 0;
1101}
1102
1103static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1104 struct mvebu_gpio_chip *mvchip)
1105{
1106 mvchip->regs = syscon_node_to_regmap(np: pdev->dev.parent->of_node);
1107 if (IS_ERR(ptr: mvchip->regs))
1108 return PTR_ERR(ptr: mvchip->regs);
1109
1110 if (of_property_read_u32(np: pdev->dev.of_node, propname: "offset", out_value: &mvchip->offset))
1111 return -EINVAL;
1112
1113 return 0;
1114}
1115
1116static void mvebu_gpio_remove_irq_domain(void *data)
1117{
1118 struct irq_domain *domain = data;
1119
1120 irq_domain_remove(host: domain);
1121}
1122
1123static int mvebu_gpio_probe(struct platform_device *pdev)
1124{
1125 struct mvebu_gpio_chip *mvchip;
1126 struct device_node *np = pdev->dev.of_node;
1127 struct irq_chip_generic *gc;
1128 struct irq_chip_type *ct;
1129 unsigned int ngpios;
1130 bool have_irqs;
1131 int soc_variant;
1132 int i, cpu, id;
1133 int err;
1134
1135 soc_variant = (unsigned long)device_get_match_data(dev: &pdev->dev);
1136
1137 /* Some gpio controllers do not provide irq support */
1138 err = platform_irq_count(pdev);
1139 if (err < 0)
1140 return err;
1141
1142 have_irqs = err != 0;
1143
1144 mvchip = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct mvebu_gpio_chip),
1145 GFP_KERNEL);
1146 if (!mvchip)
1147 return -ENOMEM;
1148
1149 platform_set_drvdata(pdev, data: mvchip);
1150
1151 if (of_property_read_u32(np: pdev->dev.of_node, propname: "ngpios", out_value: &ngpios)) {
1152 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1153 return -ENODEV;
1154 }
1155
1156 id = of_alias_get_id(np: pdev->dev.of_node, stem: "gpio");
1157 if (id < 0) {
1158 dev_err(&pdev->dev, "Couldn't get OF id\n");
1159 return id;
1160 }
1161
1162 mvchip->clk = devm_clk_get(dev: &pdev->dev, NULL);
1163 /* Not all SoCs require a clock.*/
1164 if (!IS_ERR(ptr: mvchip->clk))
1165 clk_prepare_enable(clk: mvchip->clk);
1166
1167 mvchip->soc_variant = soc_variant;
1168 mvchip->chip.label = dev_name(dev: &pdev->dev);
1169 mvchip->chip.parent = &pdev->dev;
1170 mvchip->chip.request = gpiochip_generic_request;
1171 mvchip->chip.free = gpiochip_generic_free;
1172 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1173 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1174 mvchip->chip.get = mvebu_gpio_get;
1175 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1176 mvchip->chip.set = mvebu_gpio_set;
1177 if (have_irqs)
1178 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1179 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1180 mvchip->chip.ngpio = ngpios;
1181 mvchip->chip.can_sleep = false;
1182 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1183
1184 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1185 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1186 else
1187 err = mvebu_gpio_probe_raw(pdev, mvchip);
1188
1189 if (err)
1190 return err;
1191
1192 /*
1193 * Mask and clear GPIO interrupts.
1194 */
1195 switch (soc_variant) {
1196 case MVEBU_GPIO_SOC_VARIANT_ORION:
1197 case MVEBU_GPIO_SOC_VARIANT_A8K:
1198 regmap_write(map: mvchip->regs,
1199 GPIO_EDGE_CAUSE_OFF + mvchip->offset, val: 0);
1200 regmap_write(map: mvchip->regs,
1201 GPIO_EDGE_MASK_OFF + mvchip->offset, val: 0);
1202 regmap_write(map: mvchip->regs,
1203 GPIO_LEVEL_MASK_OFF + mvchip->offset, val: 0);
1204 break;
1205 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1206 regmap_write(map: mvchip->regs, GPIO_EDGE_CAUSE_OFF, val: 0);
1207 for (cpu = 0; cpu < 2; cpu++) {
1208 regmap_write(map: mvchip->regs,
1209 GPIO_EDGE_MASK_MV78200_OFF(cpu), val: 0);
1210 regmap_write(map: mvchip->regs,
1211 GPIO_LEVEL_MASK_MV78200_OFF(cpu), val: 0);
1212 }
1213 break;
1214 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1215 regmap_write(map: mvchip->regs, GPIO_EDGE_CAUSE_OFF, val: 0);
1216 regmap_write(map: mvchip->regs, GPIO_EDGE_MASK_OFF, val: 0);
1217 regmap_write(map: mvchip->regs, GPIO_LEVEL_MASK_OFF, val: 0);
1218 for (cpu = 0; cpu < 4; cpu++) {
1219 regmap_write(map: mvchip->percpu_regs,
1220 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), val: 0);
1221 regmap_write(map: mvchip->percpu_regs,
1222 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), val: 0);
1223 regmap_write(map: mvchip->percpu_regs,
1224 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), val: 0);
1225 }
1226 break;
1227 default:
1228 BUG();
1229 }
1230
1231 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1232
1233 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1234 if (IS_REACHABLE(CONFIG_PWM)) {
1235 err = mvebu_pwm_probe(pdev, mvchip, id);
1236 if (err)
1237 return err;
1238 }
1239
1240 /* Some gpio controllers do not provide irq support */
1241 if (!have_irqs)
1242 return 0;
1243
1244 mvchip->domain =
1245 irq_domain_add_linear(of_node: np, size: ngpios, ops: &irq_generic_chip_ops, NULL);
1246 if (!mvchip->domain) {
1247 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1248 mvchip->chip.label);
1249 return -ENODEV;
1250 }
1251
1252 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1253 mvchip->domain);
1254 if (err)
1255 return err;
1256
1257 err = irq_alloc_domain_generic_chips(
1258 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1259 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1260 if (err) {
1261 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1262 mvchip->chip.label);
1263 return err;
1264 }
1265
1266 /*
1267 * NOTE: The common accessors cannot be used because of the percpu
1268 * access to the mask registers
1269 */
1270 gc = irq_get_domain_generic_chip(d: mvchip->domain, hw_irq: 0);
1271 gc->private = mvchip;
1272 ct = &gc->chip_types[0];
1273 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1274 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1275 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1276 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1277 ct->chip.name = mvchip->chip.label;
1278
1279 ct = &gc->chip_types[1];
1280 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1281 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1282 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1283 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1284 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1285 ct->handler = handle_edge_irq;
1286 ct->chip.name = mvchip->chip.label;
1287
1288 /*
1289 * Setup the interrupt handlers. Each chip can have up to 4
1290 * interrupt handlers, with each handler dealing with 8 GPIO
1291 * pins.
1292 */
1293 for (i = 0; i < 4; i++) {
1294 int irq = platform_get_irq_optional(pdev, i);
1295
1296 if (irq < 0)
1297 continue;
1298 irq_set_chained_handler_and_data(irq, handle: mvebu_gpio_irq_handler,
1299 data: mvchip);
1300 }
1301
1302 return 0;
1303}
1304
1305static struct platform_driver mvebu_gpio_driver = {
1306 .driver = {
1307 .name = "mvebu-gpio",
1308 .of_match_table = mvebu_gpio_of_match,
1309 },
1310 .probe = mvebu_gpio_probe,
1311 .suspend = mvebu_gpio_suspend,
1312 .resume = mvebu_gpio_resume,
1313};
1314builtin_platform_driver(mvebu_gpio_driver);
1315

source code of linux/drivers/gpio/gpio-mvebu.c