Warning: That file was not part of the compilation database. It may have many parsing errors.

1/*
2 * Copyright (C) 2008, 2009 Provigent Ltd.
3 *
4 * Author: Baruch Siach <baruch@tkos.co.il>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
11 *
12 * Data sheet: ARM DDI 0190B, September 2000
13 */
14#include <linux/spinlock.h>
15#include <linux/errno.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/bitops.h>
23#include <linux/gpio/driver.h>
24#include <linux/device.h>
25#include <linux/amba/bus.h>
26#include <linux/slab.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/pm.h>
29
30#define GPIODIR 0x400
31#define GPIOIS 0x404
32#define GPIOIBE 0x408
33#define GPIOIEV 0x40C
34#define GPIOIE 0x410
35#define GPIORIS 0x414
36#define GPIOMIS 0x418
37#define GPIOIC 0x41C
38
39#define PL061_GPIO_NR 8
40
41#ifdef CONFIG_PM
42struct pl061_context_save_regs {
43 u8 gpio_data;
44 u8 gpio_dir;
45 u8 gpio_is;
46 u8 gpio_ibe;
47 u8 gpio_iev;
48 u8 gpio_ie;
49};
50#endif
51
52struct pl061 {
53 raw_spinlock_t lock;
54
55 void __iomem *base;
56 struct gpio_chip gc;
57 struct irq_chip irq_chip;
58 int parent_irq;
59
60#ifdef CONFIG_PM
61 struct pl061_context_save_regs csave_regs;
62#endif
63};
64
65static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
66{
67 struct pl061 *pl061 = gpiochip_get_data(gc);
68
69 return !(readb(pl061->base + GPIODIR) & BIT(offset));
70}
71
72static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
73{
74 struct pl061 *pl061 = gpiochip_get_data(gc);
75 unsigned long flags;
76 unsigned char gpiodir;
77
78 raw_spin_lock_irqsave(&pl061->lock, flags);
79 gpiodir = readb(pl061->base + GPIODIR);
80 gpiodir &= ~(BIT(offset));
81 writeb(gpiodir, pl061->base + GPIODIR);
82 raw_spin_unlock_irqrestore(&pl061->lock, flags);
83
84 return 0;
85}
86
87static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
88 int value)
89{
90 struct pl061 *pl061 = gpiochip_get_data(gc);
91 unsigned long flags;
92 unsigned char gpiodir;
93
94 raw_spin_lock_irqsave(&pl061->lock, flags);
95 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
96 gpiodir = readb(pl061->base + GPIODIR);
97 gpiodir |= BIT(offset);
98 writeb(gpiodir, pl061->base + GPIODIR);
99
100 /*
101 * gpio value is set again, because pl061 doesn't allow to set value of
102 * a gpio pin before configuring it in OUT mode.
103 */
104 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
105 raw_spin_unlock_irqrestore(&pl061->lock, flags);
106
107 return 0;
108}
109
110static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
111{
112 struct pl061 *pl061 = gpiochip_get_data(gc);
113
114 return !!readb(pl061->base + (BIT(offset + 2)));
115}
116
117static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
118{
119 struct pl061 *pl061 = gpiochip_get_data(gc);
120
121 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
122}
123
124static int pl061_irq_type(struct irq_data *d, unsigned trigger)
125{
126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
127 struct pl061 *pl061 = gpiochip_get_data(gc);
128 int offset = irqd_to_hwirq(d);
129 unsigned long flags;
130 u8 gpiois, gpioibe, gpioiev;
131 u8 bit = BIT(offset);
132
133 if (offset < 0 || offset >= PL061_GPIO_NR)
134 return -EINVAL;
135
136 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
137 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
138 {
139 dev_err(gc->parent,
140 "trying to configure line %d for both level and edge "
141 "detection, choose one!\n",
142 offset);
143 return -EINVAL;
144 }
145
146
147 raw_spin_lock_irqsave(&pl061->lock, flags);
148
149 gpioiev = readb(pl061->base + GPIOIEV);
150 gpiois = readb(pl061->base + GPIOIS);
151 gpioibe = readb(pl061->base + GPIOIBE);
152
153 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
154 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
155
156 /* Disable edge detection */
157 gpioibe &= ~bit;
158 /* Enable level detection */
159 gpiois |= bit;
160 /* Select polarity */
161 if (polarity)
162 gpioiev |= bit;
163 else
164 gpioiev &= ~bit;
165 irq_set_handler_locked(d, handle_level_irq);
166 dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
167 offset,
168 polarity ? "HIGH" : "LOW");
169 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
170 /* Disable level detection */
171 gpiois &= ~bit;
172 /* Select both edges, setting this makes GPIOEV be ignored */
173 gpioibe |= bit;
174 irq_set_handler_locked(d, handle_edge_irq);
175 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
176 } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
177 (trigger & IRQ_TYPE_EDGE_FALLING)) {
178 bool rising = trigger & IRQ_TYPE_EDGE_RISING;
179
180 /* Disable level detection */
181 gpiois &= ~bit;
182 /* Clear detection on both edges */
183 gpioibe &= ~bit;
184 /* Select edge */
185 if (rising)
186 gpioiev |= bit;
187 else
188 gpioiev &= ~bit;
189 irq_set_handler_locked(d, handle_edge_irq);
190 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
191 offset,
192 rising ? "RISING" : "FALLING");
193 } else {
194 /* No trigger: disable everything */
195 gpiois &= ~bit;
196 gpioibe &= ~bit;
197 gpioiev &= ~bit;
198 irq_set_handler_locked(d, handle_bad_irq);
199 dev_warn(gc->parent, "no trigger selected for line %d\n",
200 offset);
201 }
202
203 writeb(gpiois, pl061->base + GPIOIS);
204 writeb(gpioibe, pl061->base + GPIOIBE);
205 writeb(gpioiev, pl061->base + GPIOIEV);
206
207 raw_spin_unlock_irqrestore(&pl061->lock, flags);
208
209 return 0;
210}
211
212static void pl061_irq_handler(struct irq_desc *desc)
213{
214 unsigned long pending;
215 int offset;
216 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
217 struct pl061 *pl061 = gpiochip_get_data(gc);
218 struct irq_chip *irqchip = irq_desc_get_chip(desc);
219
220 chained_irq_enter(irqchip, desc);
221
222 pending = readb(pl061->base + GPIOMIS);
223 if (pending) {
224 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
225 generic_handle_irq(irq_find_mapping(gc->irq.domain,
226 offset));
227 }
228
229 chained_irq_exit(irqchip, desc);
230}
231
232static void pl061_irq_mask(struct irq_data *d)
233{
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct pl061 *pl061 = gpiochip_get_data(gc);
236 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
237 u8 gpioie;
238
239 raw_spin_lock(&pl061->lock);
240 gpioie = readb(pl061->base + GPIOIE) & ~mask;
241 writeb(gpioie, pl061->base + GPIOIE);
242 raw_spin_unlock(&pl061->lock);
243}
244
245static void pl061_irq_unmask(struct irq_data *d)
246{
247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
248 struct pl061 *pl061 = gpiochip_get_data(gc);
249 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
250 u8 gpioie;
251
252 raw_spin_lock(&pl061->lock);
253 gpioie = readb(pl061->base + GPIOIE) | mask;
254 writeb(gpioie, pl061->base + GPIOIE);
255 raw_spin_unlock(&pl061->lock);
256}
257
258/**
259 * pl061_irq_ack() - ACK an edge IRQ
260 * @d: IRQ data for this IRQ
261 *
262 * This gets called from the edge IRQ handler to ACK the edge IRQ
263 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
264 * not needed: these go away when the level signal goes away.
265 */
266static void pl061_irq_ack(struct irq_data *d)
267{
268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269 struct pl061 *pl061 = gpiochip_get_data(gc);
270 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
271
272 raw_spin_lock(&pl061->lock);
273 writeb(mask, pl061->base + GPIOIC);
274 raw_spin_unlock(&pl061->lock);
275}
276
277static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
278{
279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
280 struct pl061 *pl061 = gpiochip_get_data(gc);
281
282 return irq_set_irq_wake(pl061->parent_irq, state);
283}
284
285static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
286{
287 struct device *dev = &adev->dev;
288 struct pl061 *pl061;
289 int ret, irq;
290
291 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
292 if (pl061 == NULL)
293 return -ENOMEM;
294
295 pl061->base = devm_ioremap_resource(dev, &adev->res);
296 if (IS_ERR(pl061->base))
297 return PTR_ERR(pl061->base);
298
299 raw_spin_lock_init(&pl061->lock);
300 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
301 pl061->gc.request = gpiochip_generic_request;
302 pl061->gc.free = gpiochip_generic_free;
303 }
304
305 pl061->gc.base = -1;
306 pl061->gc.get_direction = pl061_get_direction;
307 pl061->gc.direction_input = pl061_direction_input;
308 pl061->gc.direction_output = pl061_direction_output;
309 pl061->gc.get = pl061_get_value;
310 pl061->gc.set = pl061_set_value;
311 pl061->gc.ngpio = PL061_GPIO_NR;
312 pl061->gc.label = dev_name(dev);
313 pl061->gc.parent = dev;
314 pl061->gc.owner = THIS_MODULE;
315
316 ret = gpiochip_add_data(&pl061->gc, pl061);
317 if (ret)
318 return ret;
319
320 /*
321 * irq_chip support
322 */
323 pl061->irq_chip.name = dev_name(dev);
324 pl061->irq_chip.irq_ack = pl061_irq_ack;
325 pl061->irq_chip.irq_mask = pl061_irq_mask;
326 pl061->irq_chip.irq_unmask = pl061_irq_unmask;
327 pl061->irq_chip.irq_set_type = pl061_irq_type;
328 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
329
330 writeb(0, pl061->base + GPIOIE); /* disable irqs */
331 irq = adev->irq[0];
332 if (irq < 0) {
333 dev_err(&adev->dev, "invalid IRQ\n");
334 return -ENODEV;
335 }
336 pl061->parent_irq = irq;
337
338 ret = gpiochip_irqchip_add(&pl061->gc, &pl061->irq_chip,
339 0, handle_bad_irq,
340 IRQ_TYPE_NONE);
341 if (ret) {
342 dev_info(&adev->dev, "could not add irqchip\n");
343 return ret;
344 }
345 gpiochip_set_chained_irqchip(&pl061->gc, &pl061->irq_chip,
346 irq, pl061_irq_handler);
347
348 amba_set_drvdata(adev, pl061);
349 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
350 &adev->res.start);
351
352 return 0;
353}
354
355#ifdef CONFIG_PM
356static int pl061_suspend(struct device *dev)
357{
358 struct pl061 *pl061 = dev_get_drvdata(dev);
359 int offset;
360
361 pl061->csave_regs.gpio_data = 0;
362 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
363 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
364 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
365 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
366 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
367
368 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
369 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
370 pl061->csave_regs.gpio_data |=
371 pl061_get_value(&pl061->gc, offset) << offset;
372 }
373
374 return 0;
375}
376
377static int pl061_resume(struct device *dev)
378{
379 struct pl061 *pl061 = dev_get_drvdata(dev);
380 int offset;
381
382 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
383 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
384 pl061_direction_output(&pl061->gc, offset,
385 pl061->csave_regs.gpio_data &
386 (BIT(offset)));
387 else
388 pl061_direction_input(&pl061->gc, offset);
389 }
390
391 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
392 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
393 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
394 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
395
396 return 0;
397}
398
399static const struct dev_pm_ops pl061_dev_pm_ops = {
400 .suspend = pl061_suspend,
401 .resume = pl061_resume,
402 .freeze = pl061_suspend,
403 .restore = pl061_resume,
404};
405#endif
406
407static const struct amba_id pl061_ids[] = {
408 {
409 .id = 0x00041061,
410 .mask = 0x000fffff,
411 },
412 { 0, 0 },
413};
414
415static struct amba_driver pl061_gpio_driver = {
416 .drv = {
417 .name = "pl061_gpio",
418#ifdef CONFIG_PM
419 .pm = &pl061_dev_pm_ops,
420#endif
421 },
422 .id_table = pl061_ids,
423 .probe = pl061_probe,
424};
425
426static int __init pl061_gpio_init(void)
427{
428 return amba_driver_register(&pl061_gpio_driver);
429}
430device_initcall(pl061_gpio_init);
431

Warning: That file was not part of the compilation database. It may have many parsing errors.