1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO interface for Intel Sodaville SoCs.
4 *
5 * Copyright (c) 2010, 2011 Intel Corporation
6 *
7 * Author: Hans J. Koch <hjk@linutronix.de>
8 */
9
10#include <linux/errno.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#define DRV_NAME "sdv_gpio"
22#define SDV_NUM_PUB_GPIOS 12
23#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
24#define GPIO_BAR 0
25
26#define GPOUTR 0x00
27#define GPOER 0x04
28#define GPINR 0x08
29
30#define GPSTR 0x0c
31#define GPIT1R0 0x10
32#define GPIO_INT 0x14
33#define GPIT1R1 0x18
34
35#define GPMUXCTL 0x1c
36
37struct sdv_gpio_chip_data {
38 int irq_base;
39 void __iomem *gpio_pub_base;
40 struct irq_domain *id;
41 struct irq_chip_generic *gc;
42 struct gpio_chip chip;
43};
44
45static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
46{
47 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
48 struct sdv_gpio_chip_data *sd = gc->private;
49 void __iomem *type_reg;
50 u32 reg;
51
52 if (d->hwirq < 8)
53 type_reg = sd->gpio_pub_base + GPIT1R0;
54 else
55 type_reg = sd->gpio_pub_base + GPIT1R1;
56
57 reg = readl(type_reg);
58
59 switch (type) {
60 case IRQ_TYPE_LEVEL_HIGH:
61 reg &= ~BIT(4 * (d->hwirq % 8));
62 break;
63
64 case IRQ_TYPE_LEVEL_LOW:
65 reg |= BIT(4 * (d->hwirq % 8));
66 break;
67
68 default:
69 return -EINVAL;
70 }
71
72 writel(reg, type_reg);
73 return 0;
74}
75
76static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
77{
78 struct sdv_gpio_chip_data *sd = data;
79 unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
80 int irq_bit;
81
82 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
83 if (!irq_stat)
84 return IRQ_NONE;
85
86 for_each_set_bit(irq_bit, &irq_stat, 32)
87 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
88
89 return IRQ_HANDLED;
90}
91
92static int sdv_xlate(struct irq_domain *h, struct device_node *node,
93 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
94 u32 *out_type)
95{
96 u32 line, type;
97
98 if (node != irq_domain_get_of_node(h))
99 return -EINVAL;
100
101 if (intsize < 2)
102 return -EINVAL;
103
104 line = *intspec;
105 *out_hwirq = line;
106
107 intspec++;
108 type = *intspec;
109
110 switch (type) {
111 case IRQ_TYPE_LEVEL_LOW:
112 case IRQ_TYPE_LEVEL_HIGH:
113 *out_type = type;
114 break;
115 default:
116 return -EINVAL;
117 }
118 return 0;
119}
120
121static const struct irq_domain_ops irq_domain_sdv_ops = {
122 .xlate = sdv_xlate,
123};
124
125static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
126 struct pci_dev *pdev)
127{
128 struct irq_chip_type *ct;
129 int ret;
130
131 sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
132 SDV_NUM_PUB_GPIOS, -1);
133 if (sd->irq_base < 0)
134 return sd->irq_base;
135
136 /* mask + ACK all interrupt sources */
137 writel(0, sd->gpio_pub_base + GPIO_INT);
138 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
139
140 ret = devm_request_irq(&pdev->dev, pdev->irq,
141 sdv_gpio_pub_irq_handler, IRQF_SHARED,
142 "sdv_gpio", sd);
143 if (ret)
144 return ret;
145
146 /*
147 * This gpio irq controller latches level irqs. Testing shows that if
148 * we unmask & ACK the IRQ before the source of the interrupt is gone
149 * then the interrupt is active again.
150 */
151 sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
152 sd->irq_base,
153 sd->gpio_pub_base,
154 handle_fasteoi_irq);
155 if (!sd->gc)
156 return -ENOMEM;
157
158 sd->gc->private = sd;
159 ct = sd->gc->chip_types;
160 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
161 ct->regs.eoi = GPSTR;
162 ct->regs.mask = GPIO_INT;
163 ct->chip.irq_mask = irq_gc_mask_clr_bit;
164 ct->chip.irq_unmask = irq_gc_mask_set_bit;
165 ct->chip.irq_eoi = irq_gc_eoi;
166 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
167
168 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
169 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
170 IRQ_LEVEL | IRQ_NOPROBE);
171
172 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
173 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
174 if (!sd->id)
175 return -ENODEV;
176
177 return 0;
178}
179
180static int sdv_gpio_probe(struct pci_dev *pdev,
181 const struct pci_device_id *pci_id)
182{
183 struct sdv_gpio_chip_data *sd;
184 int ret;
185 u32 mux_val;
186
187 sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
188 if (!sd)
189 return -ENOMEM;
190
191 ret = pcim_enable_device(pdev);
192 if (ret) {
193 dev_err(&pdev->dev, "can't enable device.\n");
194 return ret;
195 }
196
197 ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
198 if (ret) {
199 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
200 return ret;
201 }
202
203 sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
204
205 ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
206 if (!ret)
207 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
208
209 ret = bgpio_init(&sd->chip, &pdev->dev, 4,
210 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
211 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
212 if (ret)
213 return ret;
214
215 sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
216
217 ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
218 if (ret < 0) {
219 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
220 return ret;
221 }
222
223 ret = sdv_register_irqsupport(sd, pdev);
224 if (ret)
225 return ret;
226
227 pci_set_drvdata(pdev, sd);
228 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
229 return 0;
230}
231
232static const struct pci_device_id sdv_gpio_pci_ids[] = {
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
234 { 0, },
235};
236
237static struct pci_driver sdv_gpio_driver = {
238 .driver = {
239 .suppress_bind_attrs = true,
240 },
241 .name = DRV_NAME,
242 .id_table = sdv_gpio_pci_ids,
243 .probe = sdv_gpio_probe,
244};
245builtin_pci_driver(sdv_gpio_driver);
246