1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2018 Spreadtrum Communications Inc. |
4 | * Copyright (C) 2018 Linaro Ltd. |
5 | */ |
6 | |
7 | #include <linux/bitops.h> |
8 | #include <linux/gpio/driver.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/spinlock.h> |
14 | |
15 | /* GPIO registers definition */ |
16 | #define SPRD_GPIO_DATA 0x0 |
17 | #define SPRD_GPIO_DMSK 0x4 |
18 | #define SPRD_GPIO_DIR 0x8 |
19 | #define SPRD_GPIO_IS 0xc |
20 | #define SPRD_GPIO_IBE 0x10 |
21 | #define SPRD_GPIO_IEV 0x14 |
22 | #define SPRD_GPIO_IE 0x18 |
23 | #define SPRD_GPIO_RIS 0x1c |
24 | #define SPRD_GPIO_MIS 0x20 |
25 | #define SPRD_GPIO_IC 0x24 |
26 | #define SPRD_GPIO_INEN 0x28 |
27 | |
28 | /* We have 16 banks GPIOs and each bank contain 16 GPIOs */ |
29 | #define SPRD_GPIO_BANK_NR 16 |
30 | #define SPRD_GPIO_NR 256 |
31 | #define SPRD_GPIO_BANK_SIZE 0x80 |
32 | #define SPRD_GPIO_BANK_MASK GENMASK(15, 0) |
33 | #define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_BANK_NR - 1)) |
34 | |
35 | struct sprd_gpio { |
36 | struct gpio_chip chip; |
37 | void __iomem *base; |
38 | spinlock_t lock; |
39 | int irq; |
40 | }; |
41 | |
42 | static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio, |
43 | unsigned int bank) |
44 | { |
45 | return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank; |
46 | } |
47 | |
48 | static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, |
49 | u16 reg, int val) |
50 | { |
51 | struct sprd_gpio *sprd_gpio = gpiochip_get_data(gc: chip); |
52 | void __iomem *base = sprd_gpio_bank_base(sprd_gpio, |
53 | bank: offset / SPRD_GPIO_BANK_NR); |
54 | unsigned long flags; |
55 | u32 tmp; |
56 | |
57 | spin_lock_irqsave(&sprd_gpio->lock, flags); |
58 | tmp = readl_relaxed(base + reg); |
59 | |
60 | if (val) |
61 | tmp |= BIT(SPRD_GPIO_BIT(offset)); |
62 | else |
63 | tmp &= ~BIT(SPRD_GPIO_BIT(offset)); |
64 | |
65 | writel_relaxed(tmp, base + reg); |
66 | spin_unlock_irqrestore(lock: &sprd_gpio->lock, flags); |
67 | } |
68 | |
69 | static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg) |
70 | { |
71 | struct sprd_gpio *sprd_gpio = gpiochip_get_data(gc: chip); |
72 | void __iomem *base = sprd_gpio_bank_base(sprd_gpio, |
73 | bank: offset / SPRD_GPIO_BANK_NR); |
74 | |
75 | return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); |
76 | } |
77 | |
78 | static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) |
79 | { |
80 | sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, val: 1); |
81 | return 0; |
82 | } |
83 | |
84 | static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) |
85 | { |
86 | sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, val: 0); |
87 | } |
88 | |
89 | static int sprd_gpio_direction_input(struct gpio_chip *chip, |
90 | unsigned int offset) |
91 | { |
92 | sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, val: 0); |
93 | sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, val: 1); |
94 | return 0; |
95 | } |
96 | |
97 | static int sprd_gpio_direction_output(struct gpio_chip *chip, |
98 | unsigned int offset, int value) |
99 | { |
100 | sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, val: 1); |
101 | sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, val: 0); |
102 | sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, val: value); |
103 | return 0; |
104 | } |
105 | |
106 | static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset) |
107 | { |
108 | return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA); |
109 | } |
110 | |
111 | static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset, |
112 | int value) |
113 | { |
114 | sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, val: value); |
115 | } |
116 | |
117 | static void sprd_gpio_irq_mask(struct irq_data *data) |
118 | { |
119 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data); |
120 | u32 offset = irqd_to_hwirq(d: data); |
121 | |
122 | sprd_gpio_update(chip, offset, SPRD_GPIO_IE, val: 0); |
123 | gpiochip_disable_irq(gc: chip, offset); |
124 | } |
125 | |
126 | static void sprd_gpio_irq_ack(struct irq_data *data) |
127 | { |
128 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data); |
129 | u32 offset = irqd_to_hwirq(d: data); |
130 | |
131 | sprd_gpio_update(chip, offset, SPRD_GPIO_IC, val: 1); |
132 | } |
133 | |
134 | static void sprd_gpio_irq_unmask(struct irq_data *data) |
135 | { |
136 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data); |
137 | u32 offset = irqd_to_hwirq(d: data); |
138 | |
139 | sprd_gpio_update(chip, offset, SPRD_GPIO_IE, val: 1); |
140 | gpiochip_enable_irq(gc: chip, offset); |
141 | } |
142 | |
143 | static int sprd_gpio_irq_set_type(struct irq_data *data, |
144 | unsigned int flow_type) |
145 | { |
146 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data); |
147 | u32 offset = irqd_to_hwirq(d: data); |
148 | |
149 | switch (flow_type) { |
150 | case IRQ_TYPE_EDGE_RISING: |
151 | sprd_gpio_update(chip, offset, SPRD_GPIO_IS, val: 0); |
152 | sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, val: 0); |
153 | sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, val: 1); |
154 | sprd_gpio_update(chip, offset, SPRD_GPIO_IC, val: 1); |
155 | irq_set_handler_locked(data, handler: handle_edge_irq); |
156 | break; |
157 | case IRQ_TYPE_EDGE_FALLING: |
158 | sprd_gpio_update(chip, offset, SPRD_GPIO_IS, val: 0); |
159 | sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, val: 0); |
160 | sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, val: 0); |
161 | sprd_gpio_update(chip, offset, SPRD_GPIO_IC, val: 1); |
162 | irq_set_handler_locked(data, handler: handle_edge_irq); |
163 | break; |
164 | case IRQ_TYPE_EDGE_BOTH: |
165 | sprd_gpio_update(chip, offset, SPRD_GPIO_IS, val: 0); |
166 | sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, val: 1); |
167 | sprd_gpio_update(chip, offset, SPRD_GPIO_IC, val: 1); |
168 | irq_set_handler_locked(data, handler: handle_edge_irq); |
169 | break; |
170 | case IRQ_TYPE_LEVEL_HIGH: |
171 | sprd_gpio_update(chip, offset, SPRD_GPIO_IS, val: 1); |
172 | sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, val: 0); |
173 | sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, val: 1); |
174 | irq_set_handler_locked(data, handler: handle_level_irq); |
175 | break; |
176 | case IRQ_TYPE_LEVEL_LOW: |
177 | sprd_gpio_update(chip, offset, SPRD_GPIO_IS, val: 1); |
178 | sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, val: 0); |
179 | sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, val: 0); |
180 | irq_set_handler_locked(data, handler: handle_level_irq); |
181 | break; |
182 | default: |
183 | return -EINVAL; |
184 | } |
185 | |
186 | return 0; |
187 | } |
188 | |
189 | static void sprd_gpio_irq_handler(struct irq_desc *desc) |
190 | { |
191 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
192 | struct irq_chip *ic = irq_desc_get_chip(desc); |
193 | struct sprd_gpio *sprd_gpio = gpiochip_get_data(gc: chip); |
194 | u32 bank, n; |
195 | |
196 | chained_irq_enter(chip: ic, desc); |
197 | |
198 | for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) { |
199 | void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank); |
200 | unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) & |
201 | SPRD_GPIO_BANK_MASK; |
202 | |
203 | for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR) |
204 | generic_handle_domain_irq(domain: chip->irq.domain, |
205 | hwirq: bank * SPRD_GPIO_BANK_NR + n); |
206 | } |
207 | chained_irq_exit(chip: ic, desc); |
208 | } |
209 | |
210 | static const struct irq_chip sprd_gpio_irqchip = { |
211 | .name = "sprd-gpio" , |
212 | .irq_ack = sprd_gpio_irq_ack, |
213 | .irq_mask = sprd_gpio_irq_mask, |
214 | .irq_unmask = sprd_gpio_irq_unmask, |
215 | .irq_set_type = sprd_gpio_irq_set_type, |
216 | .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, |
217 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
218 | }; |
219 | |
220 | static int sprd_gpio_probe(struct platform_device *pdev) |
221 | { |
222 | struct gpio_irq_chip *irq; |
223 | struct sprd_gpio *sprd_gpio; |
224 | |
225 | sprd_gpio = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sprd_gpio), GFP_KERNEL); |
226 | if (!sprd_gpio) |
227 | return -ENOMEM; |
228 | |
229 | sprd_gpio->irq = platform_get_irq(pdev, 0); |
230 | if (sprd_gpio->irq < 0) |
231 | return sprd_gpio->irq; |
232 | |
233 | sprd_gpio->base = devm_platform_ioremap_resource(pdev, index: 0); |
234 | if (IS_ERR(ptr: sprd_gpio->base)) |
235 | return PTR_ERR(ptr: sprd_gpio->base); |
236 | |
237 | spin_lock_init(&sprd_gpio->lock); |
238 | |
239 | sprd_gpio->chip.label = dev_name(dev: &pdev->dev); |
240 | sprd_gpio->chip.ngpio = SPRD_GPIO_NR; |
241 | sprd_gpio->chip.base = -1; |
242 | sprd_gpio->chip.parent = &pdev->dev; |
243 | sprd_gpio->chip.request = sprd_gpio_request; |
244 | sprd_gpio->chip.free = sprd_gpio_free; |
245 | sprd_gpio->chip.get = sprd_gpio_get; |
246 | sprd_gpio->chip.set = sprd_gpio_set; |
247 | sprd_gpio->chip.direction_input = sprd_gpio_direction_input; |
248 | sprd_gpio->chip.direction_output = sprd_gpio_direction_output; |
249 | |
250 | irq = &sprd_gpio->chip.irq; |
251 | gpio_irq_chip_set_chip(girq: irq, chip: &sprd_gpio_irqchip); |
252 | irq->handler = handle_bad_irq; |
253 | irq->default_type = IRQ_TYPE_NONE; |
254 | irq->parent_handler = sprd_gpio_irq_handler; |
255 | irq->parent_handler_data = sprd_gpio; |
256 | irq->num_parents = 1; |
257 | irq->parents = &sprd_gpio->irq; |
258 | |
259 | return devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio); |
260 | } |
261 | |
262 | static const struct of_device_id sprd_gpio_of_match[] = { |
263 | { .compatible = "sprd,sc9860-gpio" , }, |
264 | { /* end of list */ } |
265 | }; |
266 | MODULE_DEVICE_TABLE(of, sprd_gpio_of_match); |
267 | |
268 | static struct platform_driver sprd_gpio_driver = { |
269 | .probe = sprd_gpio_probe, |
270 | .driver = { |
271 | .name = "sprd-gpio" , |
272 | .of_match_table = sprd_gpio_of_match, |
273 | }, |
274 | }; |
275 | |
276 | module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe); |
277 | |
278 | MODULE_DESCRIPTION("Spreadtrum GPIO driver" ); |
279 | MODULE_LICENSE("GPL v2" ); |
280 | |