1/*
2 * SYSCON GPIO driver
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/err.h>
13#include <linux/gpio/driver.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/mfd/syscon.h>
20
21#define GPIO_SYSCON_FEAT_IN BIT(0)
22#define GPIO_SYSCON_FEAT_OUT BIT(1)
23#define GPIO_SYSCON_FEAT_DIR BIT(2)
24
25/* SYSCON driver is designed to use 32-bit wide registers */
26#define SYSCON_REG_SIZE (4)
27#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
28
29/**
30 * struct syscon_gpio_data - Configuration for the device.
31 * compatible: SYSCON driver compatible string.
32 * flags: Set of GPIO_SYSCON_FEAT_ flags:
33 * GPIO_SYSCON_FEAT_IN: GPIOs supports input,
34 * GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
35 * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
36 * bit_count: Number of bits used as GPIOs.
37 * dat_bit_offset: Offset (in bits) to the first GPIO bit.
38 * dir_bit_offset: Optional offset (in bits) to the first bit to switch
39 * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
40 * set: HW specific callback to assigns output value
41 * for signal "offset"
42 */
43
44struct syscon_gpio_data {
45 const char *compatible;
46 unsigned int flags;
47 unsigned int bit_count;
48 unsigned int dat_bit_offset;
49 unsigned int dir_bit_offset;
50 void (*set)(struct gpio_chip *chip,
51 unsigned offset, int value);
52};
53
54struct syscon_gpio_priv {
55 struct gpio_chip chip;
56 struct regmap *syscon;
57 const struct syscon_gpio_data *data;
58 u32 dreg_offset;
59 u32 dir_reg_offset;
60};
61
62static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
63{
64 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
65 unsigned int val, offs;
66 int ret;
67
68 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
69
70 ret = regmap_read(priv->syscon,
71 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
72 if (ret)
73 return ret;
74
75 return !!(val & BIT(offs % SYSCON_REG_BITS));
76}
77
78static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
79{
80 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
81 unsigned int offs;
82
83 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
84
85 regmap_update_bits(priv->syscon,
86 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
87 BIT(offs % SYSCON_REG_BITS),
88 val ? BIT(offs % SYSCON_REG_BITS) : 0);
89}
90
91static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
92{
93 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
94
95 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
96 unsigned int offs;
97
98 offs = priv->dir_reg_offset +
99 priv->data->dir_bit_offset + offset;
100
101 regmap_update_bits(priv->syscon,
102 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
103 BIT(offs % SYSCON_REG_BITS), 0);
104 }
105
106 return 0;
107}
108
109static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
110{
111 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
112
113 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
114 unsigned int offs;
115
116 offs = priv->dir_reg_offset +
117 priv->data->dir_bit_offset + offset;
118
119 regmap_update_bits(priv->syscon,
120 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
121 BIT(offs % SYSCON_REG_BITS),
122 BIT(offs % SYSCON_REG_BITS));
123 }
124
125 chip->set(chip, offset, val);
126
127 return 0;
128}
129
130static const struct syscon_gpio_data clps711x_mctrl_gpio = {
131 /* ARM CLPS711X SYSFLG1 Bits 8-10 */
132 .compatible = "cirrus,ep7209-syscon1",
133 .flags = GPIO_SYSCON_FEAT_IN,
134 .bit_count = 3,
135 .dat_bit_offset = 0x40 * 8 + 8,
136};
137
138static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
139 int val)
140{
141 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
142 unsigned int offs;
143 u8 bit;
144 u32 data;
145 int ret;
146
147 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
148 bit = offs % SYSCON_REG_BITS;
149 data = (val ? BIT(bit) : 0) | BIT(bit + 16);
150 ret = regmap_write(priv->syscon,
151 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
152 data);
153 if (ret < 0)
154 dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
155}
156
157static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
158 /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
159 .flags = GPIO_SYSCON_FEAT_OUT,
160 .bit_count = 1,
161 .dat_bit_offset = 0x0428 * 8 + 1,
162 .set = rockchip_gpio_set,
163};
164
165#define KEYSTONE_LOCK_BIT BIT(0)
166
167static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
168{
169 struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
170 unsigned int offs;
171 int ret;
172
173 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
174
175 if (!val)
176 return;
177
178 ret = regmap_update_bits(
179 priv->syscon,
180 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
181 BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
182 BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
183 if (ret < 0)
184 dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
185}
186
187static const struct syscon_gpio_data keystone_dsp_gpio = {
188 /* ARM Keystone 2 */
189 .compatible = NULL,
190 .flags = GPIO_SYSCON_FEAT_OUT,
191 .bit_count = 28,
192 .dat_bit_offset = 4,
193 .set = keystone_gpio_set,
194};
195
196static const struct of_device_id syscon_gpio_ids[] = {
197 {
198 .compatible = "cirrus,ep7209-mctrl-gpio",
199 .data = &clps711x_mctrl_gpio,
200 },
201 {
202 .compatible = "ti,keystone-dsp-gpio",
203 .data = &keystone_dsp_gpio,
204 },
205 {
206 .compatible = "rockchip,rk3328-grf-gpio",
207 .data = &rockchip_rk3328_gpio_mute,
208 },
209 { }
210};
211MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
212
213static int syscon_gpio_probe(struct platform_device *pdev)
214{
215 struct device *dev = &pdev->dev;
216 struct syscon_gpio_priv *priv;
217 struct device_node *np = dev->of_node;
218 int ret;
219
220 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
221 if (!priv)
222 return -ENOMEM;
223
224 priv->data = of_device_get_match_data(dev);
225
226 if (priv->data->compatible) {
227 priv->syscon = syscon_regmap_lookup_by_compatible(
228 priv->data->compatible);
229 if (IS_ERR(priv->syscon))
230 return PTR_ERR(priv->syscon);
231 } else {
232 priv->syscon =
233 syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
234 if (IS_ERR(priv->syscon) && np->parent)
235 priv->syscon = syscon_node_to_regmap(np->parent);
236 if (IS_ERR(priv->syscon))
237 return PTR_ERR(priv->syscon);
238
239 ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
240 &priv->dreg_offset);
241 if (ret)
242 dev_err(dev, "can't read the data register offset!\n");
243
244 priv->dreg_offset <<= 3;
245
246 ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
247 &priv->dir_reg_offset);
248 if (ret)
249 dev_dbg(dev, "can't read the dir register offset!\n");
250
251 priv->dir_reg_offset <<= 3;
252 }
253
254 priv->chip.parent = dev;
255 priv->chip.owner = THIS_MODULE;
256 priv->chip.label = dev_name(dev);
257 priv->chip.base = -1;
258 priv->chip.ngpio = priv->data->bit_count;
259 priv->chip.get = syscon_gpio_get;
260 if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
261 priv->chip.direction_input = syscon_gpio_dir_in;
262 if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
263 priv->chip.set = priv->data->set ? : syscon_gpio_set;
264 priv->chip.direction_output = syscon_gpio_dir_out;
265 }
266
267 platform_set_drvdata(pdev, priv);
268
269 return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
270}
271
272static struct platform_driver syscon_gpio_driver = {
273 .driver = {
274 .name = "gpio-syscon",
275 .of_match_table = syscon_gpio_ids,
276 },
277 .probe = syscon_gpio_probe,
278};
279module_platform_driver(syscon_gpio_driver);
280
281MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
282MODULE_DESCRIPTION("SYSCON GPIO driver");
283MODULE_LICENSE("GPL");
284