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1/* Abilis Systems MODULE DESCRIPTION
2 *
3 * Copyright (C) Abilis Systems 2013
4 *
5 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
6 * Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/gpio/driver.h>
26#include <linux/slab.h>
27#include <linux/irq.h>
28#include <linux/irqdomain.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/of_platform.h>
33#include <linux/spinlock.h>
34#include <linux/bitops.h>
35#include <linux/pinctrl/consumer.h>
36
37#define TB10X_GPIO_DIR_IN (0x00000000)
38#define TB10X_GPIO_DIR_OUT (0x00000001)
39#define OFFSET_TO_REG_DDR (0x00)
40#define OFFSET_TO_REG_DATA (0x04)
41#define OFFSET_TO_REG_INT_EN (0x08)
42#define OFFSET_TO_REG_CHANGE (0x0C)
43#define OFFSET_TO_REG_WRMASK (0x10)
44#define OFFSET_TO_REG_INT_TYPE (0x14)
45
46
47/**
48 * @base: register base address
49 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
50 * @irq: Interrupt line of parent interrupt controller
51 * @gc: gpio_chip structure associated to this GPIO controller
52 */
53struct tb10x_gpio {
54 void __iomem *base;
55 struct irq_domain *domain;
56 int irq;
57 struct gpio_chip gc;
58};
59
60static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
61{
62 return ioread32(gpio->base + offs);
63}
64
65static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
66 u32 val)
67{
68 iowrite32(val, gpio->base + offs);
69}
70
71static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
72 u32 mask, u32 val)
73{
74 u32 r;
75 unsigned long flags;
76
77 spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
78
79 r = tb10x_reg_read(gpio, offs);
80 r = (r & ~mask) | (val & mask);
81
82 tb10x_reg_write(gpio, offs, r);
83
84 spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
85}
86
87static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
88{
89 struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
90
91 return irq_create_mapping(tb10x_gpio->domain, offset);
92}
93
94static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
95{
96 if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
97 pr_err("Only (both) edge triggered interrupts supported.\n");
98 return -EINVAL;
99 }
100
101 irqd_set_trigger_type(data, type);
102
103 return IRQ_SET_MASK_OK;
104}
105
106static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
107{
108 struct tb10x_gpio *tb10x_gpio = data;
109 u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
110 u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
111 const unsigned long bits = r & m;
112 int i;
113
114 for_each_set_bit(i, &bits, 32)
115 generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
116
117 return IRQ_HANDLED;
118}
119
120static int tb10x_gpio_probe(struct platform_device *pdev)
121{
122 struct tb10x_gpio *tb10x_gpio;
123 struct resource *mem;
124 struct device *dev = &pdev->dev;
125 struct device_node *np = dev->of_node;
126 int ret = -EBUSY;
127 u32 ngpio;
128
129 if (!np)
130 return -EINVAL;
131
132 if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
133 return -EINVAL;
134
135 tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
136 if (tb10x_gpio == NULL)
137 return -ENOMEM;
138
139 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
140 tb10x_gpio->base = devm_ioremap_resource(dev, mem);
141 if (IS_ERR(tb10x_gpio->base))
142 return PTR_ERR(tb10x_gpio->base);
143
144 tb10x_gpio->gc.label =
145 devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
146 if (!tb10x_gpio->gc.label)
147 return -ENOMEM;
148
149 /*
150 * Initialize generic GPIO with one single register for reading and setting
151 * the lines, no special set or clear registers and a data direction register
152 * wher 1 means "output".
153 */
154 ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
155 tb10x_gpio->base + OFFSET_TO_REG_DATA,
156 NULL,
157 NULL,
158 tb10x_gpio->base + OFFSET_TO_REG_DDR,
159 NULL,
160 0);
161 if (ret) {
162 dev_err(dev, "unable to init generic GPIO\n");
163 return ret;
164 }
165 tb10x_gpio->gc.base = -1;
166 tb10x_gpio->gc.parent = dev;
167 tb10x_gpio->gc.owner = THIS_MODULE;
168 /*
169 * ngpio is set by bgpio_init() but we override it, this .request()
170 * callback also overrides the one set up by generic GPIO.
171 */
172 tb10x_gpio->gc.ngpio = ngpio;
173 tb10x_gpio->gc.request = gpiochip_generic_request;
174 tb10x_gpio->gc.free = gpiochip_generic_free;
175
176 ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
177 if (ret < 0) {
178 dev_err(dev, "Could not add gpiochip.\n");
179 return ret;
180 }
181
182 platform_set_drvdata(pdev, tb10x_gpio);
183
184 if (of_find_property(np, "interrupt-controller", NULL)) {
185 struct irq_chip_generic *gc;
186
187 ret = platform_get_irq(pdev, 0);
188 if (ret < 0) {
189 dev_err(dev, "No interrupt specified.\n");
190 return ret;
191 }
192
193 tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
194 tb10x_gpio->irq = ret;
195
196 ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
197 IRQF_TRIGGER_NONE | IRQF_SHARED,
198 dev_name(dev), tb10x_gpio);
199 if (ret != 0)
200 return ret;
201
202 tb10x_gpio->domain = irq_domain_add_linear(np,
203 tb10x_gpio->gc.ngpio,
204 &irq_generic_chip_ops, NULL);
205 if (!tb10x_gpio->domain) {
206 return -ENOMEM;
207 }
208
209 ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
210 tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
211 handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
212 IRQ_GC_INIT_MASK_CACHE);
213 if (ret)
214 return ret;
215
216 gc = tb10x_gpio->domain->gc->gc[0];
217 gc->reg_base = tb10x_gpio->base;
218 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
219 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
220 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
221 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
222 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
223 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
224 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
225 }
226
227 return 0;
228}
229
230static int tb10x_gpio_remove(struct platform_device *pdev)
231{
232 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
233
234 if (tb10x_gpio->gc.to_irq) {
235 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
236 BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
237 kfree(tb10x_gpio->domain->gc);
238 irq_domain_remove(tb10x_gpio->domain);
239 }
240
241 return 0;
242}
243
244static const struct of_device_id tb10x_gpio_dt_ids[] = {
245 { .compatible = "abilis,tb10x-gpio" },
246 { }
247};
248MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
249
250static struct platform_driver tb10x_gpio_driver = {
251 .probe = tb10x_gpio_probe,
252 .remove = tb10x_gpio_remove,
253 .driver = {
254 .name = "tb10x-gpio",
255 .of_match_table = tb10x_gpio_dt_ids,
256 }
257};
258
259module_platform_driver(tb10x_gpio_driver);
260MODULE_LICENSE("GPL");
261MODULE_DESCRIPTION("tb10x gpio.");
262MODULE_VERSION("0.0.1");
263

Warning: That file was not part of the compilation database. It may have many parsing errors.