1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/err.h>
22#include <linux/init.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/gpio/driver.h>
27#include <linux/of_device.h>
28#include <linux/platform_device.h>
29#include <linux/module.h>
30#include <linux/irqdomain.h>
31#include <linux/irqchip/chained_irq.h>
32#include <linux/pinctrl/consumer.h>
33#include <linux/pm.h>
34
35#define GPIO_BANK(x) ((x) >> 5)
36#define GPIO_PORT(x) (((x) >> 3) & 0x3)
37#define GPIO_BIT(x) ((x) & 0x7)
38
39#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
40 GPIO_PORT(x) * 4)
41
42#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
43#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
44#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
45#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
46#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
47#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
48#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
49#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
50#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
51
52
53#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
54#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
55#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
56#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
57#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
58#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
59#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
60
61#define GPIO_INT_LVL_MASK 0x010101
62#define GPIO_INT_LVL_EDGE_RISING 0x000101
63#define GPIO_INT_LVL_EDGE_FALLING 0x000100
64#define GPIO_INT_LVL_EDGE_BOTH 0x010100
65#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
66#define GPIO_INT_LVL_LEVEL_LOW 0x000000
67
68struct tegra_gpio_info;
69
70struct tegra_gpio_bank {
71 unsigned int bank;
72 unsigned int irq;
73 spinlock_t lvl_lock[4];
74 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
75#ifdef CONFIG_PM_SLEEP
76 u32 cnf[4];
77 u32 out[4];
78 u32 oe[4];
79 u32 int_enb[4];
80 u32 int_lvl[4];
81 u32 wake_enb[4];
82 u32 dbc_enb[4];
83#endif
84 u32 dbc_cnt[4];
85 struct tegra_gpio_info *tgi;
86};
87
88struct tegra_gpio_soc_config {
89 bool debounce_supported;
90 u32 bank_stride;
91 u32 upper_offset;
92};
93
94struct tegra_gpio_info {
95 struct device *dev;
96 void __iomem *regs;
97 struct irq_domain *irq_domain;
98 struct tegra_gpio_bank *bank_info;
99 const struct tegra_gpio_soc_config *soc;
100 struct gpio_chip gc;
101 struct irq_chip ic;
102 u32 bank_count;
103};
104
105static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
106 u32 val, u32 reg)
107{
108 __raw_writel(val, tgi->regs + reg);
109}
110
111static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
112{
113 return __raw_readl(tgi->regs + reg);
114}
115
116static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
117 unsigned int bit)
118{
119 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
120}
121
122static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
123 unsigned int gpio, u32 value)
124{
125 u32 val;
126
127 val = 0x100 << GPIO_BIT(gpio);
128 if (value)
129 val |= 1 << GPIO_BIT(gpio);
130 tegra_gpio_writel(tgi, val, reg);
131}
132
133static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
134{
135 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
136}
137
138static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
139{
140 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
141}
142
143static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
144{
145 return pinctrl_gpio_request(chip->base + offset);
146}
147
148static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
149{
150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
151
152 pinctrl_gpio_free(chip->base + offset);
153 tegra_gpio_disable(tgi, offset);
154}
155
156static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
157 int value)
158{
159 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
160
161 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
162}
163
164static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
165{
166 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
167 unsigned int bval = BIT(GPIO_BIT(offset));
168
169 /* If gpio is in output mode then read from the out value */
170 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
171 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
172
173 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
174}
175
176static int tegra_gpio_direction_input(struct gpio_chip *chip,
177 unsigned int offset)
178{
179 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
180 int ret;
181
182 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
183 tegra_gpio_enable(tgi, offset);
184
185 ret = pinctrl_gpio_direction_input(chip->base + offset);
186 if (ret < 0)
187 dev_err(tgi->dev,
188 "Failed to set pinctrl input direction of GPIO %d: %d",
189 chip->base + offset, ret);
190
191 return ret;
192}
193
194static int tegra_gpio_direction_output(struct gpio_chip *chip,
195 unsigned int offset,
196 int value)
197{
198 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
199 int ret;
200
201 tegra_gpio_set(chip, offset, value);
202 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
203 tegra_gpio_enable(tgi, offset);
204
205 ret = pinctrl_gpio_direction_output(chip->base + offset);
206 if (ret < 0)
207 dev_err(tgi->dev,
208 "Failed to set pinctrl output direction of GPIO %d: %d",
209 chip->base + offset, ret);
210
211 return ret;
212}
213
214static int tegra_gpio_get_direction(struct gpio_chip *chip,
215 unsigned int offset)
216{
217 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
218 u32 pin_mask = BIT(GPIO_BIT(offset));
219 u32 cnf, oe;
220
221 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
222 if (!(cnf & pin_mask))
223 return -EINVAL;
224
225 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
226
227 return !(oe & pin_mask);
228}
229
230static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
231 unsigned int debounce)
232{
233 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
234 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
235 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
236 unsigned long flags;
237 unsigned int port;
238
239 if (!debounce_ms) {
240 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
241 offset, 0);
242 return 0;
243 }
244
245 debounce_ms = min(debounce_ms, 255U);
246 port = GPIO_PORT(offset);
247
248 /* There is only one debounce count register per port and hence
249 * set the maximum of current and requested debounce time.
250 */
251 spin_lock_irqsave(&bank->dbc_lock[port], flags);
252 if (bank->dbc_cnt[port] < debounce_ms) {
253 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
254 bank->dbc_cnt[port] = debounce_ms;
255 }
256 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
257
258 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
259
260 return 0;
261}
262
263static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
264 unsigned long config)
265{
266 u32 debounce;
267
268 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
269 return -ENOTSUPP;
270
271 debounce = pinconf_to_config_argument(config);
272 return tegra_gpio_set_debounce(chip, offset, debounce);
273}
274
275static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
276{
277 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
278
279 return irq_find_mapping(tgi->irq_domain, offset);
280}
281
282static void tegra_gpio_irq_ack(struct irq_data *d)
283{
284 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
285 struct tegra_gpio_info *tgi = bank->tgi;
286 unsigned int gpio = d->hwirq;
287
288 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
289}
290
291static void tegra_gpio_irq_mask(struct irq_data *d)
292{
293 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
294 struct tegra_gpio_info *tgi = bank->tgi;
295 unsigned int gpio = d->hwirq;
296
297 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
298}
299
300static void tegra_gpio_irq_unmask(struct irq_data *d)
301{
302 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
303 struct tegra_gpio_info *tgi = bank->tgi;
304 unsigned int gpio = d->hwirq;
305
306 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
307}
308
309static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
310{
311 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
312 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
313 struct tegra_gpio_info *tgi = bank->tgi;
314 unsigned long flags;
315 u32 val;
316 int ret;
317
318 switch (type & IRQ_TYPE_SENSE_MASK) {
319 case IRQ_TYPE_EDGE_RISING:
320 lvl_type = GPIO_INT_LVL_EDGE_RISING;
321 break;
322
323 case IRQ_TYPE_EDGE_FALLING:
324 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
325 break;
326
327 case IRQ_TYPE_EDGE_BOTH:
328 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
329 break;
330
331 case IRQ_TYPE_LEVEL_HIGH:
332 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
333 break;
334
335 case IRQ_TYPE_LEVEL_LOW:
336 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
337 break;
338
339 default:
340 return -EINVAL;
341 }
342
343 spin_lock_irqsave(&bank->lvl_lock[port], flags);
344
345 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
346 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
347 val |= lvl_type << GPIO_BIT(gpio);
348 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
349
350 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
351
352 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
353 tegra_gpio_enable(tgi, gpio);
354
355 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
356 if (ret) {
357 dev_err(tgi->dev,
358 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
359 tegra_gpio_disable(tgi, gpio);
360 return ret;
361 }
362
363 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
364 irq_set_handler_locked(d, handle_level_irq);
365 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
366 irq_set_handler_locked(d, handle_edge_irq);
367
368 return 0;
369}
370
371static void tegra_gpio_irq_shutdown(struct irq_data *d)
372{
373 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
374 struct tegra_gpio_info *tgi = bank->tgi;
375 unsigned int gpio = d->hwirq;
376
377 gpiochip_unlock_as_irq(&tgi->gc, gpio);
378}
379
380static void tegra_gpio_irq_handler(struct irq_desc *desc)
381{
382 unsigned int port, pin, gpio;
383 bool unmasked = false;
384 u32 lvl;
385 unsigned long sta;
386 struct irq_chip *chip = irq_desc_get_chip(desc);
387 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
388 struct tegra_gpio_info *tgi = bank->tgi;
389
390 chained_irq_enter(chip, desc);
391
392 for (port = 0; port < 4; port++) {
393 gpio = tegra_gpio_compose(bank->bank, port, 0);
394 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
395 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
396 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
397
398 for_each_set_bit(pin, &sta, 8) {
399 tegra_gpio_writel(tgi, 1 << pin,
400 GPIO_INT_CLR(tgi, gpio));
401
402 /* if gpio is edge triggered, clear condition
403 * before executing the handler so that we don't
404 * miss edges
405 */
406 if (!unmasked && lvl & (0x100 << pin)) {
407 unmasked = true;
408 chained_irq_exit(chip, desc);
409 }
410
411 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
412 gpio + pin));
413 }
414 }
415
416 if (!unmasked)
417 chained_irq_exit(chip, desc);
418
419}
420
421#ifdef CONFIG_PM_SLEEP
422static int tegra_gpio_resume(struct device *dev)
423{
424 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
425 unsigned long flags;
426 unsigned int b, p;
427
428 local_irq_save(flags);
429
430 for (b = 0; b < tgi->bank_count; b++) {
431 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
432
433 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
434 unsigned int gpio = (b << 5) | (p << 3);
435
436 tegra_gpio_writel(tgi, bank->cnf[p],
437 GPIO_CNF(tgi, gpio));
438
439 if (tgi->soc->debounce_supported) {
440 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
441 GPIO_DBC_CNT(tgi, gpio));
442 tegra_gpio_writel(tgi, bank->dbc_enb[p],
443 GPIO_MSK_DBC_EN(tgi, gpio));
444 }
445
446 tegra_gpio_writel(tgi, bank->out[p],
447 GPIO_OUT(tgi, gpio));
448 tegra_gpio_writel(tgi, bank->oe[p],
449 GPIO_OE(tgi, gpio));
450 tegra_gpio_writel(tgi, bank->int_lvl[p],
451 GPIO_INT_LVL(tgi, gpio));
452 tegra_gpio_writel(tgi, bank->int_enb[p],
453 GPIO_INT_ENB(tgi, gpio));
454 }
455 }
456
457 local_irq_restore(flags);
458 return 0;
459}
460
461static int tegra_gpio_suspend(struct device *dev)
462{
463 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
464 unsigned long flags;
465 unsigned int b, p;
466
467 local_irq_save(flags);
468 for (b = 0; b < tgi->bank_count; b++) {
469 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
470
471 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
472 unsigned int gpio = (b << 5) | (p << 3);
473
474 bank->cnf[p] = tegra_gpio_readl(tgi,
475 GPIO_CNF(tgi, gpio));
476 bank->out[p] = tegra_gpio_readl(tgi,
477 GPIO_OUT(tgi, gpio));
478 bank->oe[p] = tegra_gpio_readl(tgi,
479 GPIO_OE(tgi, gpio));
480 if (tgi->soc->debounce_supported) {
481 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
482 GPIO_MSK_DBC_EN(tgi, gpio));
483 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
484 bank->dbc_enb[p];
485 }
486
487 bank->int_enb[p] = tegra_gpio_readl(tgi,
488 GPIO_INT_ENB(tgi, gpio));
489 bank->int_lvl[p] = tegra_gpio_readl(tgi,
490 GPIO_INT_LVL(tgi, gpio));
491
492 /* Enable gpio irq for wake up source */
493 tegra_gpio_writel(tgi, bank->wake_enb[p],
494 GPIO_INT_ENB(tgi, gpio));
495 }
496 }
497 local_irq_restore(flags);
498 return 0;
499}
500
501static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
502{
503 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
504 unsigned int gpio = d->hwirq;
505 u32 port, bit, mask;
506
507 port = GPIO_PORT(gpio);
508 bit = GPIO_BIT(gpio);
509 mask = BIT(bit);
510
511 if (enable)
512 bank->wake_enb[port] |= mask;
513 else
514 bank->wake_enb[port] &= ~mask;
515
516 return irq_set_irq_wake(bank->irq, enable);
517}
518#endif
519
520#ifdef CONFIG_DEBUG_FS
521
522#include <linux/debugfs.h>
523#include <linux/seq_file.h>
524
525static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
526{
527 struct tegra_gpio_info *tgi = s->private;
528 unsigned int i, j;
529
530 for (i = 0; i < tgi->bank_count; i++) {
531 for (j = 0; j < 4; j++) {
532 unsigned int gpio = tegra_gpio_compose(i, j, 0);
533
534 seq_printf(s,
535 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
536 i, j,
537 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
538 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
539 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
540 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
541 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
542 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
543 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
544 }
545 }
546 return 0;
547}
548
549DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
550
551static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
552{
553 (void) debugfs_create_file("tegra_gpio", 0444,
554 NULL, tgi, &tegra_dbg_gpio_fops);
555}
556
557#else
558
559static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
560{
561}
562
563#endif
564
565static const struct dev_pm_ops tegra_gpio_pm_ops = {
566 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
567};
568
569static int tegra_gpio_probe(struct platform_device *pdev)
570{
571 struct tegra_gpio_info *tgi;
572 struct resource *res;
573 struct tegra_gpio_bank *bank;
574 unsigned int gpio, i, j;
575 int ret;
576
577 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
578 if (!tgi)
579 return -ENODEV;
580
581 tgi->soc = of_device_get_match_data(&pdev->dev);
582 tgi->dev = &pdev->dev;
583
584 ret = platform_irq_count(pdev);
585 if (ret < 0)
586 return ret;
587
588 tgi->bank_count = ret;
589
590 if (!tgi->bank_count) {
591 dev_err(&pdev->dev, "Missing IRQ resource\n");
592 return -ENODEV;
593 }
594
595 tgi->gc.label = "tegra-gpio";
596 tgi->gc.request = tegra_gpio_request;
597 tgi->gc.free = tegra_gpio_free;
598 tgi->gc.direction_input = tegra_gpio_direction_input;
599 tgi->gc.get = tegra_gpio_get;
600 tgi->gc.direction_output = tegra_gpio_direction_output;
601 tgi->gc.set = tegra_gpio_set;
602 tgi->gc.get_direction = tegra_gpio_get_direction;
603 tgi->gc.to_irq = tegra_gpio_to_irq;
604 tgi->gc.base = 0;
605 tgi->gc.ngpio = tgi->bank_count * 32;
606 tgi->gc.parent = &pdev->dev;
607 tgi->gc.of_node = pdev->dev.of_node;
608
609 tgi->ic.name = "GPIO";
610 tgi->ic.irq_ack = tegra_gpio_irq_ack;
611 tgi->ic.irq_mask = tegra_gpio_irq_mask;
612 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
613 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
614 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
615#ifdef CONFIG_PM_SLEEP
616 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
617#endif
618
619 platform_set_drvdata(pdev, tgi);
620
621 if (tgi->soc->debounce_supported)
622 tgi->gc.set_config = tegra_gpio_set_config;
623
624 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
625 sizeof(*tgi->bank_info), GFP_KERNEL);
626 if (!tgi->bank_info)
627 return -ENOMEM;
628
629 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
630 tgi->gc.ngpio,
631 &irq_domain_simple_ops, NULL);
632 if (!tgi->irq_domain)
633 return -ENODEV;
634
635 for (i = 0; i < tgi->bank_count; i++) {
636 ret = platform_get_irq(pdev, i);
637 if (ret < 0) {
638 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
639 return ret;
640 }
641
642 bank = &tgi->bank_info[i];
643 bank->bank = i;
644 bank->irq = ret;
645 bank->tgi = tgi;
646 }
647
648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
650 if (IS_ERR(tgi->regs))
651 return PTR_ERR(tgi->regs);
652
653 for (i = 0; i < tgi->bank_count; i++) {
654 for (j = 0; j < 4; j++) {
655 int gpio = tegra_gpio_compose(i, j, 0);
656
657 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
658 }
659 }
660
661 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
662 if (ret < 0) {
663 irq_domain_remove(tgi->irq_domain);
664 return ret;
665 }
666
667 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
668 int irq = irq_create_mapping(tgi->irq_domain, gpio);
669 /* No validity check; all Tegra GPIOs are valid IRQs */
670
671 bank = &tgi->bank_info[GPIO_BANK(gpio)];
672
673 irq_set_chip_data(irq, bank);
674 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
675 }
676
677 for (i = 0; i < tgi->bank_count; i++) {
678 bank = &tgi->bank_info[i];
679
680 irq_set_chained_handler_and_data(bank->irq,
681 tegra_gpio_irq_handler, bank);
682
683 for (j = 0; j < 4; j++) {
684 spin_lock_init(&bank->lvl_lock[j]);
685 spin_lock_init(&bank->dbc_lock[j]);
686 }
687 }
688
689 tegra_gpio_debuginit(tgi);
690
691 return 0;
692}
693
694static const struct tegra_gpio_soc_config tegra20_gpio_config = {
695 .bank_stride = 0x80,
696 .upper_offset = 0x800,
697};
698
699static const struct tegra_gpio_soc_config tegra30_gpio_config = {
700 .bank_stride = 0x100,
701 .upper_offset = 0x80,
702};
703
704static const struct tegra_gpio_soc_config tegra210_gpio_config = {
705 .debounce_supported = true,
706 .bank_stride = 0x100,
707 .upper_offset = 0x80,
708};
709
710static const struct of_device_id tegra_gpio_of_match[] = {
711 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
712 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
713 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
714 { },
715};
716
717static struct platform_driver tegra_gpio_driver = {
718 .driver = {
719 .name = "tegra-gpio",
720 .pm = &tegra_gpio_pm_ops,
721 .of_match_table = tegra_gpio_of_match,
722 },
723 .probe = tegra_gpio_probe,
724};
725
726static int __init tegra_gpio_init(void)
727{
728 return platform_driver_register(&tegra_gpio_driver);
729}
730subsys_initcall(tegra_gpio_init);
731