1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/slab.h>
22
23/* Register Offset Definitions */
24#define XGPIO_DATA_OFFSET (0x0) /* Data register */
25#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
26
27#define XGPIO_CHANNEL0_OFFSET 0x0
28#define XGPIO_CHANNEL1_OFFSET 0x8
29
30#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31#define XGPIO_GIER_IE BIT(31)
32#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
34
35/* Read/Write access to the GPIO registers */
36#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37# define xgpio_readreg(offset) readl(offset)
38# define xgpio_writereg(offset, val) writel(val, offset)
39#else
40# define xgpio_readreg(offset) __raw_readl(offset)
41# define xgpio_writereg(offset, val) __raw_writel(val, offset)
42#endif
43
44/**
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
55 * @irqchip: IRQ chip
56 * @enable: GPIO IRQ enable/disable bitfield
57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
59 * @clk: clock resource for this driver
60 */
61struct xgpio_instance {
62 struct gpio_chip gc;
63 void __iomem *regs;
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
69 spinlock_t gpio_lock; /* For serializing operations */
70 int irq;
71 DECLARE_BITMAP(enable, 64);
72 DECLARE_BITMAP(rising_edge, 64);
73 DECLARE_BITMAP(falling_edge, 64);
74 struct clk *clk;
75};
76
77static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
78{
79 return bitmap_bitremap(oldbit: bit, old: chip->hw_map, new: chip->sw_map, bits: 64);
80}
81
82static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
83{
84 return bitmap_bitremap(oldbit: gpio, old: chip->sw_map, new: chip->hw_map, bits: 64);
85}
86
87static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
88{
89 const size_t index = BIT_WORD(bit);
90 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
91
92 return (map[index] >> offset) & 0xFFFFFFFFul;
93}
94
95static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
96{
97 const size_t index = BIT_WORD(bit);
98 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
99
100 map[index] &= ~(0xFFFFFFFFul << offset);
101 map[index] |= (unsigned long)v << offset;
102}
103
104static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
105{
106 switch (ch) {
107 case 0:
108 return XGPIO_CHANNEL0_OFFSET;
109 case 1:
110 return XGPIO_CHANNEL1_OFFSET;
111 default:
112 return -EINVAL;
113 }
114}
115
116static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
117{
118 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, ch: bit / 32);
119
120 xgpio_set_value32(map: a, bit, xgpio_readreg(addr));
121}
122
123static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
124{
125 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, ch: bit / 32);
126
127 xgpio_writereg(addr, xgpio_get_value32(a, bit));
128}
129
130static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
131{
132 int bit, lastbit = xgpio_to_bit(chip, gpio: chip->gc.ngpio - 1);
133
134 for (bit = 0; bit <= lastbit ; bit += 32)
135 xgpio_read_ch(chip, reg, bit, a);
136}
137
138static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
139{
140 int bit, lastbit = xgpio_to_bit(chip, gpio: chip->gc.ngpio - 1);
141
142 for (bit = 0; bit <= lastbit ; bit += 32)
143 xgpio_write_ch(chip, reg, bit, a);
144}
145
146/**
147 * xgpio_get - Read the specified signal of the GPIO device.
148 * @gc: Pointer to gpio_chip device structure.
149 * @gpio: GPIO signal number.
150 *
151 * This function reads the specified signal of the GPIO device.
152 *
153 * Return:
154 * 0 if direction of GPIO signals is set as input otherwise it
155 * returns negative error value.
156 */
157static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
158{
159 struct xgpio_instance *chip = gpiochip_get_data(gc);
160 int bit = xgpio_to_bit(chip, gpio);
161 DECLARE_BITMAP(state, 64);
162
163 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, a: state);
164
165 return test_bit(bit, state);
166}
167
168/**
169 * xgpio_set - Write the specified signal of the GPIO device.
170 * @gc: Pointer to gpio_chip device structure.
171 * @gpio: GPIO signal number.
172 * @val: Value to be written to specified signal.
173 *
174 * This function writes the specified value in to the specified signal of the
175 * GPIO device.
176 */
177static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
178{
179 unsigned long flags;
180 struct xgpio_instance *chip = gpiochip_get_data(gc);
181 int bit = xgpio_to_bit(chip, gpio);
182
183 spin_lock_irqsave(&chip->gpio_lock, flags);
184
185 /* Write to GPIO signal and set its direction to output */
186 __assign_bit(nr: bit, addr: chip->state, value: val);
187
188 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->state);
189
190 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
191}
192
193/**
194 * xgpio_set_multiple - Write the specified signals of the GPIO device.
195 * @gc: Pointer to gpio_chip device structure.
196 * @mask: Mask of the GPIOS to modify.
197 * @bits: Value to be wrote on each GPIO
198 *
199 * This function writes the specified values into the specified signals of the
200 * GPIO devices.
201 */
202static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
203 unsigned long *bits)
204{
205 DECLARE_BITMAP(hw_mask, 64);
206 DECLARE_BITMAP(hw_bits, 64);
207 DECLARE_BITMAP(state, 64);
208 unsigned long flags;
209 struct xgpio_instance *chip = gpiochip_get_data(gc);
210
211 bitmap_remap(dst: hw_mask, src: mask, old: chip->sw_map, new: chip->hw_map, nbits: 64);
212 bitmap_remap(dst: hw_bits, src: bits, old: chip->sw_map, new: chip->hw_map, nbits: 64);
213
214 spin_lock_irqsave(&chip->gpio_lock, flags);
215
216 bitmap_replace(dst: state, old: chip->state, new: hw_bits, mask: hw_mask, nbits: 64);
217
218 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, a: state);
219
220 bitmap_copy(dst: chip->state, src: state, nbits: 64);
221
222 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
223}
224
225/**
226 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
227 * @gc: Pointer to gpio_chip device structure.
228 * @gpio: GPIO signal number.
229 *
230 * Return:
231 * 0 - if direction of GPIO signals is set as input
232 * otherwise it returns negative error value.
233 */
234static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
235{
236 unsigned long flags;
237 struct xgpio_instance *chip = gpiochip_get_data(gc);
238 int bit = xgpio_to_bit(chip, gpio);
239
240 spin_lock_irqsave(&chip->gpio_lock, flags);
241
242 /* Set the GPIO bit in shadow register and set direction as input */
243 __set_bit(bit, chip->dir);
244 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, a: chip->dir);
245
246 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
247
248 return 0;
249}
250
251/**
252 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
253 * @gc: Pointer to gpio_chip device structure.
254 * @gpio: GPIO signal number.
255 * @val: Value to be written to specified signal.
256 *
257 * This function sets the direction of specified GPIO signal as output.
258 *
259 * Return:
260 * If all GPIO signals of GPIO chip is configured as input then it returns
261 * error otherwise it returns 0.
262 */
263static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
264{
265 unsigned long flags;
266 struct xgpio_instance *chip = gpiochip_get_data(gc);
267 int bit = xgpio_to_bit(chip, gpio);
268
269 spin_lock_irqsave(&chip->gpio_lock, flags);
270
271 /* Write state of GPIO signal */
272 __assign_bit(nr: bit, addr: chip->state, value: val);
273 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->state);
274
275 /* Clear the GPIO bit in shadow register and set direction as output */
276 __clear_bit(bit, chip->dir);
277 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, a: chip->dir);
278
279 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
280
281 return 0;
282}
283
284/**
285 * xgpio_save_regs - Set initial values of GPIO pins
286 * @chip: Pointer to GPIO instance
287 */
288static void xgpio_save_regs(struct xgpio_instance *chip)
289{
290 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, a: chip->state);
291 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, a: chip->dir);
292}
293
294static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
295{
296 int ret;
297
298 ret = pm_runtime_get_sync(dev: chip->parent);
299 /*
300 * If the device is already active pm_runtime_get() will return 1 on
301 * success, but gpio_request still needs to return 0.
302 */
303 return ret < 0 ? ret : 0;
304}
305
306static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
307{
308 pm_runtime_put(dev: chip->parent);
309}
310
311static int __maybe_unused xgpio_suspend(struct device *dev)
312{
313 struct xgpio_instance *gpio = dev_get_drvdata(dev);
314 struct irq_data *data = irq_get_irq_data(irq: gpio->irq);
315
316 if (!data) {
317 dev_dbg(dev, "IRQ not connected\n");
318 return pm_runtime_force_suspend(dev);
319 }
320
321 if (!irqd_is_wakeup_set(d: data))
322 return pm_runtime_force_suspend(dev);
323
324 return 0;
325}
326
327/**
328 * xgpio_remove - Remove method for the GPIO device.
329 * @pdev: pointer to the platform device
330 *
331 * This function remove gpiochips and frees all the allocated resources.
332 *
333 * Return: 0 always
334 */
335static void xgpio_remove(struct platform_device *pdev)
336{
337 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
338
339 pm_runtime_get_sync(dev: &pdev->dev);
340 pm_runtime_put_noidle(dev: &pdev->dev);
341 pm_runtime_disable(dev: &pdev->dev);
342 clk_disable_unprepare(clk: gpio->clk);
343}
344
345/**
346 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
347 * @irq_data: per IRQ and chip data passed down to chip functions
348 * This currently does nothing, but irq_ack is unconditionally called by
349 * handle_edge_irq and therefore must be defined.
350 */
351static void xgpio_irq_ack(struct irq_data *irq_data)
352{
353}
354
355static int __maybe_unused xgpio_resume(struct device *dev)
356{
357 struct xgpio_instance *gpio = dev_get_drvdata(dev);
358 struct irq_data *data = irq_get_irq_data(irq: gpio->irq);
359
360 if (!data) {
361 dev_dbg(dev, "IRQ not connected\n");
362 return pm_runtime_force_resume(dev);
363 }
364
365 if (!irqd_is_wakeup_set(d: data))
366 return pm_runtime_force_resume(dev);
367
368 return 0;
369}
370
371static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
372{
373 struct xgpio_instance *gpio = dev_get_drvdata(dev);
374
375 clk_disable(clk: gpio->clk);
376
377 return 0;
378}
379
380static int __maybe_unused xgpio_runtime_resume(struct device *dev)
381{
382 struct xgpio_instance *gpio = dev_get_drvdata(dev);
383
384 return clk_enable(clk: gpio->clk);
385}
386
387static const struct dev_pm_ops xgpio_dev_pm_ops = {
388 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
389 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
390 xgpio_runtime_resume, NULL)
391};
392
393/**
394 * xgpio_irq_mask - Write the specified signal of the GPIO device.
395 * @irq_data: per IRQ and chip data passed down to chip functions
396 */
397static void xgpio_irq_mask(struct irq_data *irq_data)
398{
399 unsigned long flags;
400 struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data);
401 int irq_offset = irqd_to_hwirq(d: irq_data);
402 int bit = xgpio_to_bit(chip, gpio: irq_offset);
403 u32 mask = BIT(bit / 32), temp;
404
405 spin_lock_irqsave(&chip->gpio_lock, flags);
406
407 __clear_bit(bit, chip->enable);
408
409 if (xgpio_get_value32(map: chip->enable, bit) == 0) {
410 /* Disable per channel interrupt */
411 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
412 temp &= ~mask;
413 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
414 }
415 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
416
417 gpiochip_disable_irq(gc: &chip->gc, offset: irq_offset);
418}
419
420/**
421 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
422 * @irq_data: per IRQ and chip data passed down to chip functions
423 */
424static void xgpio_irq_unmask(struct irq_data *irq_data)
425{
426 unsigned long flags;
427 struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data);
428 int irq_offset = irqd_to_hwirq(d: irq_data);
429 int bit = xgpio_to_bit(chip, gpio: irq_offset);
430 u32 old_enable = xgpio_get_value32(map: chip->enable, bit);
431 u32 mask = BIT(bit / 32), val;
432
433 gpiochip_enable_irq(gc: &chip->gc, offset: irq_offset);
434
435 spin_lock_irqsave(&chip->gpio_lock, flags);
436
437 __set_bit(bit, chip->enable);
438
439 if (old_enable == 0) {
440 /* Clear any existing per-channel interrupts */
441 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
442 val &= mask;
443 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
444
445 /* Update GPIO IRQ read data before enabling interrupt*/
446 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->last_irq_read);
447
448 /* Enable per channel interrupt */
449 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
450 val |= mask;
451 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
452 }
453
454 spin_unlock_irqrestore(lock: &chip->gpio_lock, flags);
455}
456
457/**
458 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
459 * @irq_data: Per IRQ and chip data passed down to chip functions
460 * @type: Interrupt type that is to be set for the gpio pin
461 *
462 * Return:
463 * 0 if interrupt type is supported otherwise -EINVAL
464 */
465static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
466{
467 struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data);
468 int irq_offset = irqd_to_hwirq(d: irq_data);
469 int bit = xgpio_to_bit(chip, gpio: irq_offset);
470
471 /*
472 * The Xilinx GPIO hardware provides a single interrupt status
473 * indication for any state change in a given GPIO channel (bank).
474 * Therefore, only rising edge or falling edge triggers are
475 * supported.
476 */
477 switch (type & IRQ_TYPE_SENSE_MASK) {
478 case IRQ_TYPE_EDGE_BOTH:
479 __set_bit(bit, chip->rising_edge);
480 __set_bit(bit, chip->falling_edge);
481 break;
482 case IRQ_TYPE_EDGE_RISING:
483 __set_bit(bit, chip->rising_edge);
484 __clear_bit(bit, chip->falling_edge);
485 break;
486 case IRQ_TYPE_EDGE_FALLING:
487 __clear_bit(bit, chip->rising_edge);
488 __set_bit(bit, chip->falling_edge);
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 irq_set_handler_locked(data: irq_data, handler: handle_edge_irq);
495 return 0;
496}
497
498/**
499 * xgpio_irqhandler - Gpio interrupt service routine
500 * @desc: Pointer to interrupt description
501 */
502static void xgpio_irqhandler(struct irq_desc *desc)
503{
504 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
505 struct gpio_chip *gc = &chip->gc;
506 struct irq_chip *irqchip = irq_desc_get_chip(desc);
507 DECLARE_BITMAP(rising, 64);
508 DECLARE_BITMAP(falling, 64);
509 DECLARE_BITMAP(all, 64);
510 int irq_offset;
511 u32 status;
512 u32 bit;
513
514 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
515 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
516
517 chained_irq_enter(chip: irqchip, desc);
518
519 spin_lock(lock: &chip->gpio_lock);
520
521 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, a: all);
522
523 bitmap_complement(dst: rising, src: chip->last_irq_read, nbits: 64);
524 bitmap_and(dst: rising, src1: rising, src2: all, nbits: 64);
525 bitmap_and(dst: rising, src1: rising, src2: chip->enable, nbits: 64);
526 bitmap_and(dst: rising, src1: rising, src2: chip->rising_edge, nbits: 64);
527
528 bitmap_complement(dst: falling, src: all, nbits: 64);
529 bitmap_and(dst: falling, src1: falling, src2: chip->last_irq_read, nbits: 64);
530 bitmap_and(dst: falling, src1: falling, src2: chip->enable, nbits: 64);
531 bitmap_and(dst: falling, src1: falling, src2: chip->falling_edge, nbits: 64);
532
533 bitmap_copy(dst: chip->last_irq_read, src: all, nbits: 64);
534 bitmap_or(dst: all, src1: rising, src2: falling, nbits: 64);
535
536 spin_unlock(lock: &chip->gpio_lock);
537
538 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
539
540 for_each_set_bit(bit, all, 64) {
541 irq_offset = xgpio_from_bit(chip, bit);
542 generic_handle_domain_irq(domain: gc->irq.domain, hwirq: irq_offset);
543 }
544
545 chained_irq_exit(chip: irqchip, desc);
546}
547
548static const struct irq_chip xgpio_irq_chip = {
549 .name = "gpio-xilinx",
550 .irq_ack = xgpio_irq_ack,
551 .irq_mask = xgpio_irq_mask,
552 .irq_unmask = xgpio_irq_unmask,
553 .irq_set_type = xgpio_set_irq_type,
554 .flags = IRQCHIP_IMMUTABLE,
555 GPIOCHIP_IRQ_RESOURCE_HELPERS,
556};
557
558/**
559 * xgpio_probe - Probe method for the GPIO device.
560 * @pdev: pointer to the platform device
561 *
562 * Return:
563 * It returns 0, if the driver is bound to the GPIO device, or
564 * a negative value if there is an error.
565 */
566static int xgpio_probe(struct platform_device *pdev)
567{
568 struct xgpio_instance *chip;
569 int status = 0;
570 struct device_node *np = pdev->dev.of_node;
571 u32 is_dual = 0;
572 u32 width[2];
573 u32 state[2];
574 u32 dir[2];
575 struct gpio_irq_chip *girq;
576 u32 temp;
577
578 chip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*chip), GFP_KERNEL);
579 if (!chip)
580 return -ENOMEM;
581
582 platform_set_drvdata(pdev, data: chip);
583
584 /* First, check if the device is dual-channel */
585 of_property_read_u32(np, propname: "xlnx,is-dual", out_value: &is_dual);
586
587 /* Setup defaults */
588 memset32(s: width, v: 0, ARRAY_SIZE(width));
589 memset32(s: state, v: 0, ARRAY_SIZE(state));
590 memset32(s: dir, v: 0xFFFFFFFF, ARRAY_SIZE(dir));
591
592 /* Update GPIO state shadow register with default value */
593 of_property_read_u32(np, propname: "xlnx,dout-default", out_value: &state[0]);
594 of_property_read_u32(np, propname: "xlnx,dout-default-2", out_value: &state[1]);
595
596 bitmap_from_arr32(bitmap: chip->state, buf: state, nbits: 64);
597
598 /* Update GPIO direction shadow register with default value */
599 of_property_read_u32(np, propname: "xlnx,tri-default", out_value: &dir[0]);
600 of_property_read_u32(np, propname: "xlnx,tri-default-2", out_value: &dir[1]);
601
602 bitmap_from_arr32(bitmap: chip->dir, buf: dir, nbits: 64);
603
604 /*
605 * Check device node and parent device node for device width
606 * and assume default width of 32
607 */
608 if (of_property_read_u32(np, propname: "xlnx,gpio-width", out_value: &width[0]))
609 width[0] = 32;
610
611 if (width[0] > 32)
612 return -EINVAL;
613
614 if (is_dual && of_property_read_u32(np, propname: "xlnx,gpio2-width", out_value: &width[1]))
615 width[1] = 32;
616
617 if (width[1] > 32)
618 return -EINVAL;
619
620 /* Setup software pin mapping */
621 bitmap_set(map: chip->sw_map, start: 0, nbits: width[0] + width[1]);
622
623 /* Setup hardware pin mapping */
624 bitmap_set(map: chip->hw_map, start: 0, nbits: width[0]);
625 bitmap_set(map: chip->hw_map, start: 32, nbits: width[1]);
626
627 spin_lock_init(&chip->gpio_lock);
628
629 chip->gc.base = -1;
630 chip->gc.ngpio = bitmap_weight(src: chip->hw_map, nbits: 64);
631 chip->gc.parent = &pdev->dev;
632 chip->gc.direction_input = xgpio_dir_in;
633 chip->gc.direction_output = xgpio_dir_out;
634 chip->gc.get = xgpio_get;
635 chip->gc.set = xgpio_set;
636 chip->gc.request = xgpio_request;
637 chip->gc.free = xgpio_free;
638 chip->gc.set_multiple = xgpio_set_multiple;
639
640 chip->gc.label = dev_name(dev: &pdev->dev);
641
642 chip->regs = devm_platform_ioremap_resource(pdev, index: 0);
643 if (IS_ERR(ptr: chip->regs)) {
644 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
645 return PTR_ERR(ptr: chip->regs);
646 }
647
648 chip->clk = devm_clk_get_optional(dev: &pdev->dev, NULL);
649 if (IS_ERR(ptr: chip->clk))
650 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: chip->clk), fmt: "input clock not found.\n");
651
652 status = clk_prepare_enable(clk: chip->clk);
653 if (status < 0) {
654 dev_err(&pdev->dev, "Failed to prepare clk\n");
655 return status;
656 }
657 pm_runtime_get_noresume(dev: &pdev->dev);
658 pm_runtime_set_active(dev: &pdev->dev);
659 pm_runtime_enable(dev: &pdev->dev);
660
661 xgpio_save_regs(chip);
662
663 chip->irq = platform_get_irq_optional(pdev, 0);
664 if (chip->irq <= 0)
665 goto skip_irq;
666
667 /* Disable per-channel interrupts */
668 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
669 /* Clear any existing per-channel interrupts */
670 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
671 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
672 /* Enable global interrupts */
673 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
674
675 girq = &chip->gc.irq;
676 gpio_irq_chip_set_chip(girq, chip: &xgpio_irq_chip);
677 girq->parent_handler = xgpio_irqhandler;
678 girq->num_parents = 1;
679 girq->parents = devm_kcalloc(dev: &pdev->dev, n: 1,
680 size: sizeof(*girq->parents),
681 GFP_KERNEL);
682 if (!girq->parents) {
683 status = -ENOMEM;
684 goto err_pm_put;
685 }
686 girq->parents[0] = chip->irq;
687 girq->default_type = IRQ_TYPE_NONE;
688 girq->handler = handle_bad_irq;
689
690skip_irq:
691 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
692 if (status) {
693 dev_err(&pdev->dev, "failed to add GPIO chip\n");
694 goto err_pm_put;
695 }
696
697 pm_runtime_put(dev: &pdev->dev);
698 return 0;
699
700err_pm_put:
701 pm_runtime_disable(dev: &pdev->dev);
702 pm_runtime_put_noidle(dev: &pdev->dev);
703 clk_disable_unprepare(clk: chip->clk);
704 return status;
705}
706
707static const struct of_device_id xgpio_of_match[] = {
708 { .compatible = "xlnx,xps-gpio-1.00.a", },
709 { /* end of list */ },
710};
711
712MODULE_DEVICE_TABLE(of, xgpio_of_match);
713
714static struct platform_driver xgpio_plat_driver = {
715 .probe = xgpio_probe,
716 .remove_new = xgpio_remove,
717 .driver = {
718 .name = "gpio-xilinx",
719 .of_match_table = xgpio_of_match,
720 .pm = &xgpio_dev_pm_ops,
721 },
722};
723
724static int __init xgpio_init(void)
725{
726 return platform_driver_register(&xgpio_plat_driver);
727}
728
729subsys_initcall(xgpio_init);
730
731static void __exit xgpio_exit(void)
732{
733 platform_driver_unregister(&xgpio_plat_driver);
734}
735module_exit(xgpio_exit);
736
737MODULE_AUTHOR("Xilinx, Inc.");
738MODULE_DESCRIPTION("Xilinx GPIO driver");
739MODULE_LICENSE("GPL");
740

source code of linux/drivers/gpio/gpio-xilinx.c