1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2013 TangoTec Ltd. |
4 | * Author: Baruch Siach <baruch@tkos.co.il> |
5 | * |
6 | * Driver for the Xtensa LX4 GPIO32 Option |
7 | * |
8 | * Documentation: Xtensa LX4 Microprocessor Data Book, Section 2.22 |
9 | * |
10 | * GPIO32 is a standard optional extension to the Xtensa architecture core that |
11 | * provides preconfigured output and input ports for intra SoC signaling. The |
12 | * GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE) |
13 | * output state called EXPSTATE, and 32bit input wire called IMPWIRE. This |
14 | * driver treats input and output states as two distinct devices. |
15 | * |
16 | * Access to GPIO32 specific instructions is controlled by the CPENABLE |
17 | * (Coprocessor Enable Bits) register. By default Xtensa Linux startup code |
18 | * disables access to all coprocessors. This driver sets the CPENABLE bit |
19 | * corresponding to GPIO32 before any GPIO32 specific instruction, and restores |
20 | * CPENABLE state after that. |
21 | * |
22 | * This driver is currently incompatible with SMP. The GPIO32 extension is not |
23 | * guaranteed to be available in all cores. Moreover, each core controls a |
24 | * different set of IO wires. A theoretical SMP aware version of this driver |
25 | * would need to have a per core workqueue to do the actual GPIO manipulation. |
26 | */ |
27 | |
28 | #include <linux/err.h> |
29 | #include <linux/module.h> |
30 | #include <linux/gpio/driver.h> |
31 | #include <linux/bitops.h> |
32 | #include <linux/platform_device.h> |
33 | |
34 | #include <asm/coprocessor.h> /* CPENABLE read/write macros */ |
35 | |
36 | #ifndef XCHAL_CP_ID_XTIOP |
37 | #error GPIO32 option is not enabled for your xtensa core variant |
38 | #endif |
39 | |
40 | #if XCHAL_HAVE_CP |
41 | |
42 | static inline unsigned long enable_cp(unsigned long *cpenable) |
43 | { |
44 | unsigned long flags; |
45 | |
46 | local_irq_save(flags); |
47 | *cpenable = xtensa_get_sr(cpenable); |
48 | xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable); |
49 | return flags; |
50 | } |
51 | |
52 | static inline void disable_cp(unsigned long flags, unsigned long cpenable) |
53 | { |
54 | xtensa_set_sr(cpenable, cpenable); |
55 | local_irq_restore(flags); |
56 | } |
57 | |
58 | #else |
59 | |
60 | static inline unsigned long enable_cp(unsigned long *cpenable) |
61 | { |
62 | *cpenable = 0; /* avoid uninitialized value warning */ |
63 | return 0; |
64 | } |
65 | |
66 | static inline void disable_cp(unsigned long flags, unsigned long cpenable) |
67 | { |
68 | } |
69 | |
70 | #endif /* XCHAL_HAVE_CP */ |
71 | |
72 | static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset) |
73 | { |
74 | return GPIO_LINE_DIRECTION_IN; /* input only */ |
75 | } |
76 | |
77 | static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset) |
78 | { |
79 | unsigned long flags, saved_cpenable; |
80 | u32 impwire; |
81 | |
82 | flags = enable_cp(cpenable: &saved_cpenable); |
83 | __asm__ __volatile__("read_impwire %0" : "=a" (impwire)); |
84 | disable_cp(flags, cpenable: saved_cpenable); |
85 | |
86 | return !!(impwire & BIT(offset)); |
87 | } |
88 | |
89 | static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset, |
90 | int value) |
91 | { |
92 | BUG(); /* output only; should never be called */ |
93 | } |
94 | |
95 | static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset) |
96 | { |
97 | return GPIO_LINE_DIRECTION_OUT; /* output only */ |
98 | } |
99 | |
100 | static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset) |
101 | { |
102 | unsigned long flags, saved_cpenable; |
103 | u32 expstate; |
104 | |
105 | flags = enable_cp(cpenable: &saved_cpenable); |
106 | __asm__ __volatile__("rur.expstate %0" : "=a" (expstate)); |
107 | disable_cp(flags, cpenable: saved_cpenable); |
108 | |
109 | return !!(expstate & BIT(offset)); |
110 | } |
111 | |
112 | static void xtensa_expstate_set_value(struct gpio_chip *gc, unsigned offset, |
113 | int value) |
114 | { |
115 | unsigned long flags, saved_cpenable; |
116 | u32 mask = BIT(offset); |
117 | u32 val = value ? BIT(offset) : 0; |
118 | |
119 | flags = enable_cp(cpenable: &saved_cpenable); |
120 | __asm__ __volatile__("wrmsk_expstate %0, %1" |
121 | :: "a" (val), "a" (mask)); |
122 | disable_cp(flags, cpenable: saved_cpenable); |
123 | } |
124 | |
125 | static struct gpio_chip impwire_chip = { |
126 | .label = "impwire" , |
127 | .base = -1, |
128 | .ngpio = 32, |
129 | .get_direction = xtensa_impwire_get_direction, |
130 | .get = xtensa_impwire_get_value, |
131 | .set = xtensa_impwire_set_value, |
132 | }; |
133 | |
134 | static struct gpio_chip expstate_chip = { |
135 | .label = "expstate" , |
136 | .base = -1, |
137 | .ngpio = 32, |
138 | .get_direction = xtensa_expstate_get_direction, |
139 | .get = xtensa_expstate_get_value, |
140 | .set = xtensa_expstate_set_value, |
141 | }; |
142 | |
143 | static int xtensa_gpio_probe(struct platform_device *pdev) |
144 | { |
145 | int ret; |
146 | |
147 | ret = gpiochip_add_data(&impwire_chip, NULL); |
148 | if (ret) |
149 | return ret; |
150 | return gpiochip_add_data(&expstate_chip, NULL); |
151 | } |
152 | |
153 | static struct platform_driver xtensa_gpio_driver = { |
154 | .driver = { |
155 | .name = "xtensa-gpio" , |
156 | }, |
157 | .probe = xtensa_gpio_probe, |
158 | }; |
159 | |
160 | static int __init xtensa_gpio_init(void) |
161 | { |
162 | struct platform_device *pdev; |
163 | |
164 | pdev = platform_device_register_simple(name: "xtensa-gpio" , id: 0, NULL, num: 0); |
165 | if (IS_ERR(ptr: pdev)) |
166 | return PTR_ERR(ptr: pdev); |
167 | |
168 | return platform_driver_register(&xtensa_gpio_driver); |
169 | } |
170 | device_initcall(xtensa_gpio_init); |
171 | |
172 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>" ); |
173 | MODULE_DESCRIPTION("Xtensa LX4 GPIO32 driver" ); |
174 | MODULE_LICENSE("GPL" ); |
175 | |