1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/display/drm_dp_helper.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/drm_edid.h>
30#include <drm/drm_modeset_helper_vtables.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "atom.h"
35#include "atombios_encoders.h"
36#include "atombios_dp.h"
37#include "amdgpu_connectors.h"
38#include "amdgpu_i2c.h"
39#include "amdgpu_display.h"
40
41#include <linux/pm_runtime.h>
42
43void amdgpu_connector_hotplug(struct drm_connector *connector)
44{
45 struct drm_device *dev = connector->dev;
46 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
48
49 /* bail if the connector does not have hpd pin, e.g.,
50 * VGA, TV, etc.
51 */
52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
53 return;
54
55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
56
57 /* if the connector is already off, don't turn it back on */
58 if (connector->dpms != DRM_MODE_DPMS_ON)
59 return;
60
61 /* just deal with DP (not eDP) here. */
62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
63 struct amdgpu_connector_atom_dig *dig_connector =
64 amdgpu_connector->con_priv;
65
66 /* if existing sink type was not DP no need to retrain */
67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
68 return;
69
70 /* first get sink type as it may be reset after (un)plug */
71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
72 /* don't do anything if sink is not display port, i.e.,
73 * passive dp->(dvi|hdmi) adaptor
74 */
75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78 /* Don't start link training before we have the DPCD */
79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
80 return;
81
82 /* Turn the connector off and back on immediately, which
83 * will trigger link training
84 */
85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
87 }
88 }
89}
90
91static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
92{
93 struct drm_crtc *crtc = encoder->crtc;
94
95 if (crtc && crtc->enabled) {
96 drm_crtc_helper_set_mode(crtc, mode: &crtc->mode,
97 x: crtc->x, y: crtc->y, old_fb: crtc->primary->fb);
98 }
99}
100
101int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
102{
103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
104 struct amdgpu_connector_atom_dig *dig_connector;
105 int bpc = 8;
106 unsigned mode_clock, max_tmds_clock;
107
108 switch (connector->connector_type) {
109 case DRM_MODE_CONNECTOR_DVII:
110 case DRM_MODE_CONNECTOR_HDMIB:
111 if (amdgpu_connector->use_digital) {
112 if (connector->display_info.is_hdmi) {
113 if (connector->display_info.bpc)
114 bpc = connector->display_info.bpc;
115 }
116 }
117 break;
118 case DRM_MODE_CONNECTOR_DVID:
119 case DRM_MODE_CONNECTOR_HDMIA:
120 if (connector->display_info.is_hdmi) {
121 if (connector->display_info.bpc)
122 bpc = connector->display_info.bpc;
123 }
124 break;
125 case DRM_MODE_CONNECTOR_DisplayPort:
126 dig_connector = amdgpu_connector->con_priv;
127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
129 connector->display_info.is_hdmi) {
130 if (connector->display_info.bpc)
131 bpc = connector->display_info.bpc;
132 }
133 break;
134 case DRM_MODE_CONNECTOR_eDP:
135 case DRM_MODE_CONNECTOR_LVDS:
136 if (connector->display_info.bpc)
137 bpc = connector->display_info.bpc;
138 else {
139 const struct drm_connector_helper_funcs *connector_funcs =
140 connector->helper_private;
141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
144
145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
146 bpc = 6;
147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
148 bpc = 8;
149 }
150 break;
151 }
152
153 if (connector->display_info.is_hdmi) {
154 /*
155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
157 * 12 bpc is always supported on hdmi deep color sinks, as this is
158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
159 */
160 if (bpc > 12) {
161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
162 connector->name, bpc);
163 bpc = 12;
164 }
165
166 /* Any defined maximum tmds clock limit we must not exceed? */
167 if (connector->display_info.max_tmds_clock > 0) {
168 /* mode_clock is clock in kHz for mode to be modeset on this connector */
169 mode_clock = amdgpu_connector->pixelclock_for_modeset;
170
171 /* Maximum allowable input clock in kHz */
172 max_tmds_clock = connector->display_info.max_tmds_clock;
173
174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
175 connector->name, mode_clock, max_tmds_clock);
176
177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
180 (mode_clock * 5/4 <= max_tmds_clock))
181 bpc = 10;
182 else
183 bpc = 8;
184
185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
186 connector->name, bpc);
187 }
188
189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
190 bpc = 8;
191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
192 connector->name, bpc);
193 }
194 } else if (bpc > 8) {
195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
197 connector->name);
198 bpc = 8;
199 }
200 }
201
202 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
204 connector->name);
205 bpc = 8;
206 }
207
208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
209 connector->name, connector->display_info.bpc, bpc);
210
211 return bpc;
212}
213
214static void
215amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
216 enum drm_connector_status status)
217{
218 struct drm_encoder *best_encoder;
219 struct drm_encoder *encoder;
220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221 bool connected;
222
223 best_encoder = connector_funcs->best_encoder(connector);
224
225 drm_connector_for_each_possible_encoder(connector, encoder) {
226 if ((encoder == best_encoder) && (status == connector_status_connected))
227 connected = true;
228 else
229 connected = false;
230
231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
232 }
233}
234
235static struct drm_encoder *
236amdgpu_connector_find_encoder(struct drm_connector *connector,
237 int encoder_type)
238{
239 struct drm_encoder *encoder;
240
241 drm_connector_for_each_possible_encoder(connector, encoder) {
242 if (encoder->encoder_type == encoder_type)
243 return encoder;
244 }
245
246 return NULL;
247}
248
249struct edid *amdgpu_connector_edid(struct drm_connector *connector)
250{
251 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
252 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
253
254 if (amdgpu_connector->edid) {
255 return amdgpu_connector->edid;
256 } else if (edid_blob) {
257 struct edid *edid = kmemdup(p: edid_blob->data, size: edid_blob->length, GFP_KERNEL);
258 if (edid)
259 amdgpu_connector->edid = edid;
260 }
261 return amdgpu_connector->edid;
262}
263
264static struct edid *
265amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
266{
267 if (adev->mode_info.bios_hardcoded_edid) {
268 return kmemdup(p: (unsigned char *)adev->mode_info.bios_hardcoded_edid,
269 size: adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
270 }
271 return NULL;
272}
273
274static void amdgpu_connector_get_edid(struct drm_connector *connector)
275{
276 struct drm_device *dev = connector->dev;
277 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
278 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
279
280 if (amdgpu_connector->edid)
281 return;
282
283 /* on hw with routers, select right port */
284 if (amdgpu_connector->router.ddc_valid)
285 amdgpu_i2c_router_select_ddc_port(connector: amdgpu_connector);
286
287 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
288 ENCODER_OBJECT_ID_NONE) &&
289 amdgpu_connector->ddc_bus->has_aux) {
290 amdgpu_connector->edid = drm_get_edid(connector,
291 adapter: &amdgpu_connector->ddc_bus->aux.ddc);
292 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
294 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
295
296 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
297 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
298 amdgpu_connector->ddc_bus->has_aux)
299 amdgpu_connector->edid = drm_get_edid(connector,
300 adapter: &amdgpu_connector->ddc_bus->aux.ddc);
301 else if (amdgpu_connector->ddc_bus)
302 amdgpu_connector->edid = drm_get_edid(connector,
303 adapter: &amdgpu_connector->ddc_bus->adapter);
304 } else if (amdgpu_connector->ddc_bus) {
305 amdgpu_connector->edid = drm_get_edid(connector,
306 adapter: &amdgpu_connector->ddc_bus->adapter);
307 }
308
309 if (!amdgpu_connector->edid) {
310 /* some laptops provide a hardcoded edid in rom for LCDs */
311 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
312 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
313 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
314 drm_connector_update_edid_property(connector, edid: amdgpu_connector->edid);
315 }
316 }
317}
318
319static void amdgpu_connector_free_edid(struct drm_connector *connector)
320{
321 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
322
323 kfree(objp: amdgpu_connector->edid);
324 amdgpu_connector->edid = NULL;
325}
326
327static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
328{
329 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
330 int ret;
331
332 if (amdgpu_connector->edid) {
333 drm_connector_update_edid_property(connector, edid: amdgpu_connector->edid);
334 ret = drm_add_edid_modes(connector, edid: amdgpu_connector->edid);
335 return ret;
336 }
337 drm_connector_update_edid_property(connector, NULL);
338 return 0;
339}
340
341static struct drm_encoder *
342amdgpu_connector_best_single_encoder(struct drm_connector *connector)
343{
344 struct drm_encoder *encoder;
345
346 /* pick the first one */
347 drm_connector_for_each_possible_encoder(connector, encoder)
348 return encoder;
349
350 return NULL;
351}
352
353static void amdgpu_get_native_mode(struct drm_connector *connector)
354{
355 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
356 struct amdgpu_encoder *amdgpu_encoder;
357
358 if (encoder == NULL)
359 return;
360
361 amdgpu_encoder = to_amdgpu_encoder(encoder);
362
363 if (!list_empty(head: &connector->probed_modes)) {
364 struct drm_display_mode *preferred_mode =
365 list_first_entry(&connector->probed_modes,
366 struct drm_display_mode, head);
367
368 amdgpu_encoder->native_mode = *preferred_mode;
369 } else {
370 amdgpu_encoder->native_mode.clock = 0;
371 }
372}
373
374static struct drm_display_mode *
375amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
376{
377 struct drm_device *dev = encoder->dev;
378 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
379 struct drm_display_mode *mode = NULL;
380 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
381
382 if (native_mode->hdisplay != 0 &&
383 native_mode->vdisplay != 0 &&
384 native_mode->clock != 0) {
385 mode = drm_mode_duplicate(dev, mode: native_mode);
386 if (!mode)
387 return NULL;
388
389 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
390 drm_mode_set_name(mode);
391
392 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
393 } else if (native_mode->hdisplay != 0 &&
394 native_mode->vdisplay != 0) {
395 /* mac laptops without an edid */
396 /* Note that this is not necessarily the exact panel mode,
397 * but an approximation based on the cvt formula. For these
398 * systems we should ideally read the mode info out of the
399 * registers or add a mode table, but this works and is much
400 * simpler.
401 */
402 mode = drm_cvt_mode(dev, hdisplay: native_mode->hdisplay, vdisplay: native_mode->vdisplay, vrefresh: 60, reduced: true, interlaced: false, margins: false);
403 if (!mode)
404 return NULL;
405
406 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
407 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
408 }
409 return mode;
410}
411
412static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
413 struct drm_connector *connector)
414{
415 struct drm_device *dev = encoder->dev;
416 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
417 struct drm_display_mode *mode = NULL;
418 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
419 int i;
420 static const struct mode_size {
421 int w;
422 int h;
423 } common_modes[17] = {
424 { 640, 480},
425 { 720, 480},
426 { 800, 600},
427 { 848, 480},
428 {1024, 768},
429 {1152, 768},
430 {1280, 720},
431 {1280, 800},
432 {1280, 854},
433 {1280, 960},
434 {1280, 1024},
435 {1440, 900},
436 {1400, 1050},
437 {1680, 1050},
438 {1600, 1200},
439 {1920, 1080},
440 {1920, 1200}
441 };
442
443 for (i = 0; i < 17; i++) {
444 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
445 if (common_modes[i].w > 1024 ||
446 common_modes[i].h > 768)
447 continue;
448 }
449 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
450 if (common_modes[i].w > native_mode->hdisplay ||
451 common_modes[i].h > native_mode->vdisplay ||
452 (common_modes[i].w == native_mode->hdisplay &&
453 common_modes[i].h == native_mode->vdisplay))
454 continue;
455 }
456 if (common_modes[i].w < 320 || common_modes[i].h < 200)
457 continue;
458
459 mode = drm_cvt_mode(dev, hdisplay: common_modes[i].w, vdisplay: common_modes[i].h, vrefresh: 60, reduced: false, interlaced: false, margins: false);
460 drm_mode_probed_add(connector, mode);
461 }
462}
463
464static int amdgpu_connector_set_property(struct drm_connector *connector,
465 struct drm_property *property,
466 uint64_t val)
467{
468 struct drm_device *dev = connector->dev;
469 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
470 struct drm_encoder *encoder;
471 struct amdgpu_encoder *amdgpu_encoder;
472
473 if (property == adev->mode_info.coherent_mode_property) {
474 struct amdgpu_encoder_atom_dig *dig;
475 bool new_coherent_mode;
476
477 /* need to find digital encoder on connector */
478 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
479 if (!encoder)
480 return 0;
481
482 amdgpu_encoder = to_amdgpu_encoder(encoder);
483
484 if (!amdgpu_encoder->enc_priv)
485 return 0;
486
487 dig = amdgpu_encoder->enc_priv;
488 new_coherent_mode = val ? true : false;
489 if (dig->coherent_mode != new_coherent_mode) {
490 dig->coherent_mode = new_coherent_mode;
491 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
492 }
493 }
494
495 if (property == adev->mode_info.audio_property) {
496 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
497 /* need to find digital encoder on connector */
498 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
499 if (!encoder)
500 return 0;
501
502 amdgpu_encoder = to_amdgpu_encoder(encoder);
503
504 if (amdgpu_connector->audio != val) {
505 amdgpu_connector->audio = val;
506 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
507 }
508 }
509
510 if (property == adev->mode_info.dither_property) {
511 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
512 /* need to find digital encoder on connector */
513 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
514 if (!encoder)
515 return 0;
516
517 amdgpu_encoder = to_amdgpu_encoder(encoder);
518
519 if (amdgpu_connector->dither != val) {
520 amdgpu_connector->dither = val;
521 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
522 }
523 }
524
525 if (property == adev->mode_info.underscan_property) {
526 /* need to find digital encoder on connector */
527 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
528 if (!encoder)
529 return 0;
530
531 amdgpu_encoder = to_amdgpu_encoder(encoder);
532
533 if (amdgpu_encoder->underscan_type != val) {
534 amdgpu_encoder->underscan_type = val;
535 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
536 }
537 }
538
539 if (property == adev->mode_info.underscan_hborder_property) {
540 /* need to find digital encoder on connector */
541 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
542 if (!encoder)
543 return 0;
544
545 amdgpu_encoder = to_amdgpu_encoder(encoder);
546
547 if (amdgpu_encoder->underscan_hborder != val) {
548 amdgpu_encoder->underscan_hborder = val;
549 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
550 }
551 }
552
553 if (property == adev->mode_info.underscan_vborder_property) {
554 /* need to find digital encoder on connector */
555 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
556 if (!encoder)
557 return 0;
558
559 amdgpu_encoder = to_amdgpu_encoder(encoder);
560
561 if (amdgpu_encoder->underscan_vborder != val) {
562 amdgpu_encoder->underscan_vborder = val;
563 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
564 }
565 }
566
567 if (property == adev->mode_info.load_detect_property) {
568 struct amdgpu_connector *amdgpu_connector =
569 to_amdgpu_connector(connector);
570
571 if (val == 0)
572 amdgpu_connector->dac_load_detect = false;
573 else
574 amdgpu_connector->dac_load_detect = true;
575 }
576
577 if (property == dev->mode_config.scaling_mode_property) {
578 enum amdgpu_rmx_type rmx_type;
579
580 if (connector->encoder) {
581 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
582 } else {
583 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
584 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
585 }
586
587 switch (val) {
588 default:
589 case DRM_MODE_SCALE_NONE:
590 rmx_type = RMX_OFF;
591 break;
592 case DRM_MODE_SCALE_CENTER:
593 rmx_type = RMX_CENTER;
594 break;
595 case DRM_MODE_SCALE_ASPECT:
596 rmx_type = RMX_ASPECT;
597 break;
598 case DRM_MODE_SCALE_FULLSCREEN:
599 rmx_type = RMX_FULL;
600 break;
601 }
602
603 if (amdgpu_encoder->rmx_type == rmx_type)
604 return 0;
605
606 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
607 (amdgpu_encoder->native_mode.clock == 0))
608 return 0;
609
610 amdgpu_encoder->rmx_type = rmx_type;
611
612 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
613 }
614
615 return 0;
616}
617
618static void
619amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
620 struct drm_connector *connector)
621{
622 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
623 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
624 struct drm_display_mode *t, *mode;
625
626 /* If the EDID preferred mode doesn't match the native mode, use it */
627 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
628 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
629 if (mode->hdisplay != native_mode->hdisplay ||
630 mode->vdisplay != native_mode->vdisplay)
631 drm_mode_copy(dst: native_mode, src: mode);
632 }
633 }
634
635 /* Try to get native mode details from EDID if necessary */
636 if (!native_mode->clock) {
637 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
638 if (mode->hdisplay == native_mode->hdisplay &&
639 mode->vdisplay == native_mode->vdisplay) {
640 drm_mode_copy(dst: native_mode, src: mode);
641 drm_mode_set_crtcinfo(p: native_mode, CRTC_INTERLACE_HALVE_V);
642 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
643 break;
644 }
645 }
646 }
647
648 if (!native_mode->clock) {
649 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
650 amdgpu_encoder->rmx_type = RMX_OFF;
651 }
652}
653
654static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
655{
656 struct drm_encoder *encoder;
657 int ret = 0;
658 struct drm_display_mode *mode;
659
660 amdgpu_connector_get_edid(connector);
661 ret = amdgpu_connector_ddc_get_modes(connector);
662 if (ret > 0) {
663 encoder = amdgpu_connector_best_single_encoder(connector);
664 if (encoder) {
665 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
666 /* add scaled modes */
667 amdgpu_connector_add_common_modes(encoder, connector);
668 }
669 return ret;
670 }
671
672 encoder = amdgpu_connector_best_single_encoder(connector);
673 if (!encoder)
674 return 0;
675
676 /* we have no EDID modes */
677 mode = amdgpu_connector_lcd_native_mode(encoder);
678 if (mode) {
679 ret = 1;
680 drm_mode_probed_add(connector, mode);
681 /* add the width/height from vbios tables if available */
682 connector->display_info.width_mm = mode->width_mm;
683 connector->display_info.height_mm = mode->height_mm;
684 /* add scaled modes */
685 amdgpu_connector_add_common_modes(encoder, connector);
686 }
687
688 return ret;
689}
690
691static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
692 struct drm_display_mode *mode)
693{
694 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
695
696 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
697 return MODE_PANEL;
698
699 if (encoder) {
700 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
701 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
702
703 /* AVIVO hardware supports downscaling modes larger than the panel
704 * to the panel size, but I'm not sure this is desirable.
705 */
706 if ((mode->hdisplay > native_mode->hdisplay) ||
707 (mode->vdisplay > native_mode->vdisplay))
708 return MODE_PANEL;
709
710 /* if scaling is disabled, block non-native modes */
711 if (amdgpu_encoder->rmx_type == RMX_OFF) {
712 if ((mode->hdisplay != native_mode->hdisplay) ||
713 (mode->vdisplay != native_mode->vdisplay))
714 return MODE_PANEL;
715 }
716 }
717
718 return MODE_OK;
719}
720
721static enum drm_connector_status
722amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
723{
724 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
725 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
726 enum drm_connector_status ret = connector_status_disconnected;
727 int r;
728
729 if (!drm_kms_helper_is_poll_worker()) {
730 r = pm_runtime_get_sync(dev: connector->dev->dev);
731 if (r < 0) {
732 pm_runtime_put_autosuspend(dev: connector->dev->dev);
733 return connector_status_disconnected;
734 }
735 }
736
737 if (encoder) {
738 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
739 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
740
741 /* check if panel is valid */
742 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
743 ret = connector_status_connected;
744
745 }
746
747 /* check for edid as well */
748 amdgpu_connector_get_edid(connector);
749 if (amdgpu_connector->edid)
750 ret = connector_status_connected;
751 /* check acpi lid status ??? */
752
753 amdgpu_connector_update_scratch_regs(connector, status: ret);
754
755 if (!drm_kms_helper_is_poll_worker()) {
756 pm_runtime_mark_last_busy(dev: connector->dev->dev);
757 pm_runtime_put_autosuspend(dev: connector->dev->dev);
758 }
759
760 return ret;
761}
762
763static void amdgpu_connector_unregister(struct drm_connector *connector)
764{
765 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
766
767 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
768 drm_dp_aux_unregister(aux: &amdgpu_connector->ddc_bus->aux);
769 amdgpu_connector->ddc_bus->has_aux = false;
770 }
771}
772
773static void amdgpu_connector_destroy(struct drm_connector *connector)
774{
775 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
776
777 amdgpu_connector_free_edid(connector);
778 kfree(objp: amdgpu_connector->con_priv);
779 drm_connector_unregister(connector);
780 drm_connector_cleanup(connector);
781 kfree(objp: connector);
782}
783
784static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
785 struct drm_property *property,
786 uint64_t value)
787{
788 struct drm_device *dev = connector->dev;
789 struct amdgpu_encoder *amdgpu_encoder;
790 enum amdgpu_rmx_type rmx_type;
791
792 DRM_DEBUG_KMS("\n");
793 if (property != dev->mode_config.scaling_mode_property)
794 return 0;
795
796 if (connector->encoder)
797 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
798 else {
799 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
800 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
801 }
802
803 switch (value) {
804 case DRM_MODE_SCALE_NONE:
805 rmx_type = RMX_OFF;
806 break;
807 case DRM_MODE_SCALE_CENTER:
808 rmx_type = RMX_CENTER;
809 break;
810 case DRM_MODE_SCALE_ASPECT:
811 rmx_type = RMX_ASPECT;
812 break;
813 default:
814 case DRM_MODE_SCALE_FULLSCREEN:
815 rmx_type = RMX_FULL;
816 break;
817 }
818
819 if (amdgpu_encoder->rmx_type == rmx_type)
820 return 0;
821
822 amdgpu_encoder->rmx_type = rmx_type;
823
824 amdgpu_connector_property_change_mode(encoder: &amdgpu_encoder->base);
825 return 0;
826}
827
828
829static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
830 .get_modes = amdgpu_connector_lvds_get_modes,
831 .mode_valid = amdgpu_connector_lvds_mode_valid,
832 .best_encoder = amdgpu_connector_best_single_encoder,
833};
834
835static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
836 .dpms = drm_helper_connector_dpms,
837 .detect = amdgpu_connector_lvds_detect,
838 .fill_modes = drm_helper_probe_single_connector_modes,
839 .early_unregister = amdgpu_connector_unregister,
840 .destroy = amdgpu_connector_destroy,
841 .set_property = amdgpu_connector_set_lcd_property,
842};
843
844static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
845{
846 int ret;
847
848 amdgpu_connector_get_edid(connector);
849 ret = amdgpu_connector_ddc_get_modes(connector);
850 amdgpu_get_native_mode(connector);
851
852 return ret;
853}
854
855static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
856 struct drm_display_mode *mode)
857{
858 struct drm_device *dev = connector->dev;
859 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
860
861 /* XXX check mode bandwidth */
862
863 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
864 return MODE_CLOCK_HIGH;
865
866 return MODE_OK;
867}
868
869static enum drm_connector_status
870amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
871{
872 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
873 struct drm_encoder *encoder;
874 const struct drm_encoder_helper_funcs *encoder_funcs;
875 bool dret = false;
876 enum drm_connector_status ret = connector_status_disconnected;
877 int r;
878
879 if (!drm_kms_helper_is_poll_worker()) {
880 r = pm_runtime_get_sync(dev: connector->dev->dev);
881 if (r < 0) {
882 pm_runtime_put_autosuspend(dev: connector->dev->dev);
883 return connector_status_disconnected;
884 }
885 }
886
887 encoder = amdgpu_connector_best_single_encoder(connector);
888 if (!encoder)
889 ret = connector_status_disconnected;
890
891 if (amdgpu_connector->ddc_bus)
892 dret = amdgpu_display_ddc_probe(amdgpu_connector, use_aux: false);
893 if (dret) {
894 amdgpu_connector->detected_by_load = false;
895 amdgpu_connector_free_edid(connector);
896 amdgpu_connector_get_edid(connector);
897
898 if (!amdgpu_connector->edid) {
899 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
900 connector->name);
901 ret = connector_status_connected;
902 } else {
903 amdgpu_connector->use_digital =
904 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
905
906 /* some oems have boards with separate digital and analog connectors
907 * with a shared ddc line (often vga + hdmi)
908 */
909 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
910 amdgpu_connector_free_edid(connector);
911 ret = connector_status_disconnected;
912 } else {
913 ret = connector_status_connected;
914 }
915 }
916 } else {
917
918 /* if we aren't forcing don't do destructive polling */
919 if (!force) {
920 /* only return the previous status if we last
921 * detected a monitor via load.
922 */
923 if (amdgpu_connector->detected_by_load)
924 ret = connector->status;
925 goto out;
926 }
927
928 if (amdgpu_connector->dac_load_detect && encoder) {
929 encoder_funcs = encoder->helper_private;
930 ret = encoder_funcs->detect(encoder, connector);
931 if (ret != connector_status_disconnected)
932 amdgpu_connector->detected_by_load = true;
933 }
934 }
935
936 amdgpu_connector_update_scratch_regs(connector, status: ret);
937
938out:
939 if (!drm_kms_helper_is_poll_worker()) {
940 pm_runtime_mark_last_busy(dev: connector->dev->dev);
941 pm_runtime_put_autosuspend(dev: connector->dev->dev);
942 }
943
944 return ret;
945}
946
947static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
948 .get_modes = amdgpu_connector_vga_get_modes,
949 .mode_valid = amdgpu_connector_vga_mode_valid,
950 .best_encoder = amdgpu_connector_best_single_encoder,
951};
952
953static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
954 .dpms = drm_helper_connector_dpms,
955 .detect = amdgpu_connector_vga_detect,
956 .fill_modes = drm_helper_probe_single_connector_modes,
957 .early_unregister = amdgpu_connector_unregister,
958 .destroy = amdgpu_connector_destroy,
959 .set_property = amdgpu_connector_set_property,
960};
961
962static bool
963amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
964{
965 struct drm_device *dev = connector->dev;
966 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
967 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
968 enum drm_connector_status status;
969
970 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
971 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
972 status = connector_status_connected;
973 else
974 status = connector_status_disconnected;
975 if (connector->status == status)
976 return true;
977 }
978
979 return false;
980}
981
982/*
983 * DVI is complicated
984 * Do a DDC probe, if DDC probe passes, get the full EDID so
985 * we can do analog/digital monitor detection at this point.
986 * If the monitor is an analog monitor or we got no DDC,
987 * we need to find the DAC encoder object for this connector.
988 * If we got no DDC, we do load detection on the DAC encoder object.
989 * If we got analog DDC or load detection passes on the DAC encoder
990 * we have to check if this analog encoder is shared with anyone else (TV)
991 * if its shared we have to set the other connector to disconnected.
992 */
993static enum drm_connector_status
994amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
995{
996 struct drm_device *dev = connector->dev;
997 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
998 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
999 const struct drm_encoder_helper_funcs *encoder_funcs;
1000 int r;
1001 enum drm_connector_status ret = connector_status_disconnected;
1002 bool dret = false, broken_edid = false;
1003
1004 if (!drm_kms_helper_is_poll_worker()) {
1005 r = pm_runtime_get_sync(dev: connector->dev->dev);
1006 if (r < 0) {
1007 pm_runtime_put_autosuspend(dev: connector->dev->dev);
1008 return connector_status_disconnected;
1009 }
1010 }
1011
1012 if (amdgpu_connector->detected_hpd_without_ddc) {
1013 force = true;
1014 amdgpu_connector->detected_hpd_without_ddc = false;
1015 }
1016
1017 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1018 ret = connector->status;
1019 goto exit;
1020 }
1021
1022 if (amdgpu_connector->ddc_bus) {
1023 dret = amdgpu_display_ddc_probe(amdgpu_connector, use_aux: false);
1024
1025 /* Sometimes the pins required for the DDC probe on DVI
1026 * connectors don't make contact at the same time that the ones
1027 * for HPD do. If the DDC probe fails even though we had an HPD
1028 * signal, try again later
1029 */
1030 if (!dret && !force &&
1031 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1032 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1033 amdgpu_connector->detected_hpd_without_ddc = true;
1034 schedule_delayed_work(dwork: &adev->hotplug_work,
1035 delay: msecs_to_jiffies(m: 1000));
1036 goto exit;
1037 }
1038 }
1039 if (dret) {
1040 amdgpu_connector->detected_by_load = false;
1041 amdgpu_connector_free_edid(connector);
1042 amdgpu_connector_get_edid(connector);
1043
1044 if (!amdgpu_connector->edid) {
1045 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1046 connector->name);
1047 ret = connector_status_connected;
1048 broken_edid = true; /* defer use_digital to later */
1049 } else {
1050 amdgpu_connector->use_digital =
1051 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1052
1053 /* some oems have boards with separate digital and analog connectors
1054 * with a shared ddc line (often vga + hdmi)
1055 */
1056 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1057 amdgpu_connector_free_edid(connector);
1058 ret = connector_status_disconnected;
1059 } else {
1060 ret = connector_status_connected;
1061 }
1062
1063 /* This gets complicated. We have boards with VGA + HDMI with a
1064 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1065 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1066 * you don't really know what's connected to which port as both are digital.
1067 */
1068 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1069 struct drm_connector *list_connector;
1070 struct drm_connector_list_iter iter;
1071 struct amdgpu_connector *list_amdgpu_connector;
1072
1073 drm_connector_list_iter_begin(dev, iter: &iter);
1074 drm_for_each_connector_iter(list_connector,
1075 &iter) {
1076 if (connector == list_connector)
1077 continue;
1078 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1079 if (list_amdgpu_connector->shared_ddc &&
1080 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1081 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1082 /* cases where both connectors are digital */
1083 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1084 /* hpd is our only option in this case */
1085 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1086 amdgpu_connector_free_edid(connector);
1087 ret = connector_status_disconnected;
1088 }
1089 }
1090 }
1091 }
1092 drm_connector_list_iter_end(iter: &iter);
1093 }
1094 }
1095 }
1096
1097 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1098 goto out;
1099
1100 /* DVI-D and HDMI-A are digital only */
1101 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1102 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1103 goto out;
1104
1105 /* if we aren't forcing don't do destructive polling */
1106 if (!force) {
1107 /* only return the previous status if we last
1108 * detected a monitor via load.
1109 */
1110 if (amdgpu_connector->detected_by_load)
1111 ret = connector->status;
1112 goto out;
1113 }
1114
1115 /* find analog encoder */
1116 if (amdgpu_connector->dac_load_detect) {
1117 struct drm_encoder *encoder;
1118
1119 drm_connector_for_each_possible_encoder(connector, encoder) {
1120 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1121 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1122 continue;
1123
1124 encoder_funcs = encoder->helper_private;
1125 if (encoder_funcs->detect) {
1126 if (!broken_edid) {
1127 if (ret != connector_status_connected) {
1128 /* deal with analog monitors without DDC */
1129 ret = encoder_funcs->detect(encoder, connector);
1130 if (ret == connector_status_connected) {
1131 amdgpu_connector->use_digital = false;
1132 }
1133 if (ret != connector_status_disconnected)
1134 amdgpu_connector->detected_by_load = true;
1135 }
1136 } else {
1137 enum drm_connector_status lret;
1138 /* assume digital unless load detected otherwise */
1139 amdgpu_connector->use_digital = true;
1140 lret = encoder_funcs->detect(encoder, connector);
1141 DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1142 encoder->encoder_type, lret);
1143 if (lret == connector_status_connected)
1144 amdgpu_connector->use_digital = false;
1145 }
1146 break;
1147 }
1148 }
1149 }
1150
1151out:
1152 /* updated in get modes as well since we need to know if it's analog or digital */
1153 amdgpu_connector_update_scratch_regs(connector, status: ret);
1154
1155exit:
1156 if (!drm_kms_helper_is_poll_worker()) {
1157 pm_runtime_mark_last_busy(dev: connector->dev->dev);
1158 pm_runtime_put_autosuspend(dev: connector->dev->dev);
1159 }
1160
1161 return ret;
1162}
1163
1164/* okay need to be smart in here about which encoder to pick */
1165static struct drm_encoder *
1166amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1167{
1168 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1169 struct drm_encoder *encoder;
1170
1171 drm_connector_for_each_possible_encoder(connector, encoder) {
1172 if (amdgpu_connector->use_digital == true) {
1173 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1174 return encoder;
1175 } else {
1176 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1177 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1178 return encoder;
1179 }
1180 }
1181
1182 /* see if we have a default encoder TODO */
1183
1184 /* then check use digitial */
1185 /* pick the first one */
1186 drm_connector_for_each_possible_encoder(connector, encoder)
1187 return encoder;
1188
1189 return NULL;
1190}
1191
1192static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1193{
1194 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1195 if (connector->force == DRM_FORCE_ON)
1196 amdgpu_connector->use_digital = false;
1197 if (connector->force == DRM_FORCE_ON_DIGITAL)
1198 amdgpu_connector->use_digital = true;
1199}
1200
1201static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1202 struct drm_display_mode *mode)
1203{
1204 struct drm_device *dev = connector->dev;
1205 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1206 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1207
1208 /* XXX check mode bandwidth */
1209
1210 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1211 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1212 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1213 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1214 return MODE_OK;
1215 } else if (connector->display_info.is_hdmi) {
1216 /* HDMI 1.3+ supports max clock of 340 Mhz */
1217 if (mode->clock > 340000)
1218 return MODE_CLOCK_HIGH;
1219 else
1220 return MODE_OK;
1221 } else {
1222 return MODE_CLOCK_HIGH;
1223 }
1224 }
1225
1226 /* check against the max pixel clock */
1227 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1228 return MODE_CLOCK_HIGH;
1229
1230 return MODE_OK;
1231}
1232
1233static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1234 .get_modes = amdgpu_connector_vga_get_modes,
1235 .mode_valid = amdgpu_connector_dvi_mode_valid,
1236 .best_encoder = amdgpu_connector_dvi_encoder,
1237};
1238
1239static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1240 .dpms = drm_helper_connector_dpms,
1241 .detect = amdgpu_connector_dvi_detect,
1242 .fill_modes = drm_helper_probe_single_connector_modes,
1243 .set_property = amdgpu_connector_set_property,
1244 .early_unregister = amdgpu_connector_unregister,
1245 .destroy = amdgpu_connector_destroy,
1246 .force = amdgpu_connector_dvi_force,
1247};
1248
1249static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1250{
1251 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1252 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1253 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1254 int ret;
1255
1256 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1257 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1258 struct drm_display_mode *mode;
1259
1260 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1261 if (!amdgpu_dig_connector->edp_on)
1262 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1263 ATOM_TRANSMITTER_ACTION_POWER_ON);
1264 amdgpu_connector_get_edid(connector);
1265 ret = amdgpu_connector_ddc_get_modes(connector);
1266 if (!amdgpu_dig_connector->edp_on)
1267 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1268 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1269 } else {
1270 /* need to setup ddc on the bridge */
1271 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1272 ENCODER_OBJECT_ID_NONE) {
1273 if (encoder)
1274 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1275 }
1276 amdgpu_connector_get_edid(connector);
1277 ret = amdgpu_connector_ddc_get_modes(connector);
1278 }
1279
1280 if (ret > 0) {
1281 if (encoder) {
1282 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1283 /* add scaled modes */
1284 amdgpu_connector_add_common_modes(encoder, connector);
1285 }
1286 return ret;
1287 }
1288
1289 if (!encoder)
1290 return 0;
1291
1292 /* we have no EDID modes */
1293 mode = amdgpu_connector_lcd_native_mode(encoder);
1294 if (mode) {
1295 ret = 1;
1296 drm_mode_probed_add(connector, mode);
1297 /* add the width/height from vbios tables if available */
1298 connector->display_info.width_mm = mode->width_mm;
1299 connector->display_info.height_mm = mode->height_mm;
1300 /* add scaled modes */
1301 amdgpu_connector_add_common_modes(encoder, connector);
1302 }
1303 } else {
1304 /* need to setup ddc on the bridge */
1305 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1306 ENCODER_OBJECT_ID_NONE) {
1307 if (encoder)
1308 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1309 }
1310 amdgpu_connector_get_edid(connector);
1311 ret = amdgpu_connector_ddc_get_modes(connector);
1312
1313 amdgpu_get_native_mode(connector);
1314 }
1315
1316 return ret;
1317}
1318
1319u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1320{
1321 struct drm_encoder *encoder;
1322 struct amdgpu_encoder *amdgpu_encoder;
1323
1324 drm_connector_for_each_possible_encoder(connector, encoder) {
1325 amdgpu_encoder = to_amdgpu_encoder(encoder);
1326
1327 switch (amdgpu_encoder->encoder_id) {
1328 case ENCODER_OBJECT_ID_TRAVIS:
1329 case ENCODER_OBJECT_ID_NUTMEG:
1330 return amdgpu_encoder->encoder_id;
1331 default:
1332 break;
1333 }
1334 }
1335
1336 return ENCODER_OBJECT_ID_NONE;
1337}
1338
1339static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1340{
1341 struct drm_encoder *encoder;
1342 struct amdgpu_encoder *amdgpu_encoder;
1343 bool found = false;
1344
1345 drm_connector_for_each_possible_encoder(connector, encoder) {
1346 amdgpu_encoder = to_amdgpu_encoder(encoder);
1347 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1348 found = true;
1349 }
1350
1351 return found;
1352}
1353
1354bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1355{
1356 struct drm_device *dev = connector->dev;
1357 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1358
1359 if ((adev->clock.default_dispclk >= 53900) &&
1360 amdgpu_connector_encoder_is_hbr2(connector)) {
1361 return true;
1362 }
1363
1364 return false;
1365}
1366
1367static enum drm_connector_status
1368amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1369{
1370 struct drm_device *dev = connector->dev;
1371 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1372 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1373 enum drm_connector_status ret = connector_status_disconnected;
1374 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1375 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1376 int r;
1377
1378 if (!drm_kms_helper_is_poll_worker()) {
1379 r = pm_runtime_get_sync(dev: connector->dev->dev);
1380 if (r < 0) {
1381 pm_runtime_put_autosuspend(dev: connector->dev->dev);
1382 return connector_status_disconnected;
1383 }
1384 }
1385
1386 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1387 ret = connector->status;
1388 goto out;
1389 }
1390
1391 amdgpu_connector_free_edid(connector);
1392
1393 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1394 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1395 if (encoder) {
1396 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1397 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1398
1399 /* check if panel is valid */
1400 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1401 ret = connector_status_connected;
1402 }
1403 /* eDP is always DP */
1404 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1405 if (!amdgpu_dig_connector->edp_on)
1406 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1407 ATOM_TRANSMITTER_ACTION_POWER_ON);
1408 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1409 ret = connector_status_connected;
1410 if (!amdgpu_dig_connector->edp_on)
1411 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1412 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1413 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1414 ENCODER_OBJECT_ID_NONE) {
1415 /* DP bridges are always DP */
1416 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1417 /* get the DPCD from the bridge */
1418 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1419
1420 if (encoder) {
1421 /* setup ddc on the bridge */
1422 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1423 /* bridge chips are always aux */
1424 /* try DDC */
1425 if (amdgpu_display_ddc_probe(amdgpu_connector, use_aux: true))
1426 ret = connector_status_connected;
1427 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1428 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1429 ret = encoder_funcs->detect(encoder, connector);
1430 }
1431 }
1432 } else {
1433 amdgpu_dig_connector->dp_sink_type =
1434 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1435 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1436 ret = connector_status_connected;
1437 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1438 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1439 } else {
1440 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1441 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1442 ret = connector_status_connected;
1443 } else {
1444 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1445 if (amdgpu_display_ddc_probe(amdgpu_connector,
1446 use_aux: false))
1447 ret = connector_status_connected;
1448 }
1449 }
1450 }
1451
1452 amdgpu_connector_update_scratch_regs(connector, status: ret);
1453out:
1454 if (!drm_kms_helper_is_poll_worker()) {
1455 pm_runtime_mark_last_busy(dev: connector->dev->dev);
1456 pm_runtime_put_autosuspend(dev: connector->dev->dev);
1457 }
1458
1459 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1460 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1461 drm_dp_set_subconnector_property(connector: &amdgpu_connector->base,
1462 status: ret,
1463 dpcd: amdgpu_dig_connector->dpcd,
1464 port_cap: amdgpu_dig_connector->downstream_ports);
1465 return ret;
1466}
1467
1468static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1469 struct drm_display_mode *mode)
1470{
1471 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1472 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1473
1474 /* XXX check mode bandwidth */
1475
1476 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1477 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1478 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1479
1480 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1481 return MODE_PANEL;
1482
1483 if (encoder) {
1484 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1485 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1486
1487 /* AVIVO hardware supports downscaling modes larger than the panel
1488 * to the panel size, but I'm not sure this is desirable.
1489 */
1490 if ((mode->hdisplay > native_mode->hdisplay) ||
1491 (mode->vdisplay > native_mode->vdisplay))
1492 return MODE_PANEL;
1493
1494 /* if scaling is disabled, block non-native modes */
1495 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1496 if ((mode->hdisplay != native_mode->hdisplay) ||
1497 (mode->vdisplay != native_mode->vdisplay))
1498 return MODE_PANEL;
1499 }
1500 }
1501 return MODE_OK;
1502 } else {
1503 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1504 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1505 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1506 } else {
1507 if (connector->display_info.is_hdmi) {
1508 /* HDMI 1.3+ supports max clock of 340 Mhz */
1509 if (mode->clock > 340000)
1510 return MODE_CLOCK_HIGH;
1511 } else {
1512 if (mode->clock > 165000)
1513 return MODE_CLOCK_HIGH;
1514 }
1515 }
1516 }
1517
1518 return MODE_OK;
1519}
1520
1521static int
1522amdgpu_connector_late_register(struct drm_connector *connector)
1523{
1524 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1525 int r = 0;
1526
1527 if (amdgpu_connector->ddc_bus->has_aux) {
1528 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1529 r = drm_dp_aux_register(aux: &amdgpu_connector->ddc_bus->aux);
1530 }
1531
1532 return r;
1533}
1534
1535static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1536 .get_modes = amdgpu_connector_dp_get_modes,
1537 .mode_valid = amdgpu_connector_dp_mode_valid,
1538 .best_encoder = amdgpu_connector_dvi_encoder,
1539};
1540
1541static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1542 .dpms = drm_helper_connector_dpms,
1543 .detect = amdgpu_connector_dp_detect,
1544 .fill_modes = drm_helper_probe_single_connector_modes,
1545 .set_property = amdgpu_connector_set_property,
1546 .early_unregister = amdgpu_connector_unregister,
1547 .destroy = amdgpu_connector_destroy,
1548 .force = amdgpu_connector_dvi_force,
1549 .late_register = amdgpu_connector_late_register,
1550};
1551
1552static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1553 .dpms = drm_helper_connector_dpms,
1554 .detect = amdgpu_connector_dp_detect,
1555 .fill_modes = drm_helper_probe_single_connector_modes,
1556 .set_property = amdgpu_connector_set_lcd_property,
1557 .early_unregister = amdgpu_connector_unregister,
1558 .destroy = amdgpu_connector_destroy,
1559 .force = amdgpu_connector_dvi_force,
1560 .late_register = amdgpu_connector_late_register,
1561};
1562
1563void
1564amdgpu_connector_add(struct amdgpu_device *adev,
1565 uint32_t connector_id,
1566 uint32_t supported_device,
1567 int connector_type,
1568 struct amdgpu_i2c_bus_rec *i2c_bus,
1569 uint16_t connector_object_id,
1570 struct amdgpu_hpd *hpd,
1571 struct amdgpu_router *router)
1572{
1573 struct drm_device *dev = adev_to_drm(adev);
1574 struct drm_connector *connector;
1575 struct drm_connector_list_iter iter;
1576 struct amdgpu_connector *amdgpu_connector;
1577 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1578 struct drm_encoder *encoder;
1579 struct amdgpu_encoder *amdgpu_encoder;
1580 struct i2c_adapter *ddc = NULL;
1581 uint32_t subpixel_order = SubPixelNone;
1582 bool shared_ddc = false;
1583 bool is_dp_bridge = false;
1584 bool has_aux = false;
1585
1586 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1587 return;
1588
1589 /* see if we already added it */
1590 drm_connector_list_iter_begin(dev, iter: &iter);
1591 drm_for_each_connector_iter(connector, &iter) {
1592 amdgpu_connector = to_amdgpu_connector(connector);
1593 if (amdgpu_connector->connector_id == connector_id) {
1594 amdgpu_connector->devices |= supported_device;
1595 drm_connector_list_iter_end(iter: &iter);
1596 return;
1597 }
1598 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1599 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1600 amdgpu_connector->shared_ddc = true;
1601 shared_ddc = true;
1602 }
1603 if (amdgpu_connector->router_bus && router->ddc_valid &&
1604 (amdgpu_connector->router.router_id == router->router_id)) {
1605 amdgpu_connector->shared_ddc = false;
1606 shared_ddc = false;
1607 }
1608 }
1609 }
1610 drm_connector_list_iter_end(iter: &iter);
1611
1612 /* check if it's a dp bridge */
1613 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1614 amdgpu_encoder = to_amdgpu_encoder(encoder);
1615 if (amdgpu_encoder->devices & supported_device) {
1616 switch (amdgpu_encoder->encoder_id) {
1617 case ENCODER_OBJECT_ID_TRAVIS:
1618 case ENCODER_OBJECT_ID_NUTMEG:
1619 is_dp_bridge = true;
1620 break;
1621 default:
1622 break;
1623 }
1624 }
1625 }
1626
1627 amdgpu_connector = kzalloc(size: sizeof(struct amdgpu_connector), GFP_KERNEL);
1628 if (!amdgpu_connector)
1629 return;
1630
1631 connector = &amdgpu_connector->base;
1632
1633 amdgpu_connector->connector_id = connector_id;
1634 amdgpu_connector->devices = supported_device;
1635 amdgpu_connector->shared_ddc = shared_ddc;
1636 amdgpu_connector->connector_object_id = connector_object_id;
1637 amdgpu_connector->hpd = *hpd;
1638
1639 amdgpu_connector->router = *router;
1640 if (router->ddc_valid || router->cd_valid) {
1641 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, i2c_bus: &router->i2c_info);
1642 if (!amdgpu_connector->router_bus)
1643 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1644 }
1645
1646 if (is_dp_bridge) {
1647 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1648 if (!amdgpu_dig_connector)
1649 goto failed;
1650 amdgpu_connector->con_priv = amdgpu_dig_connector;
1651 if (i2c_bus->valid) {
1652 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1653 if (amdgpu_connector->ddc_bus) {
1654 has_aux = true;
1655 ddc = &amdgpu_connector->ddc_bus->adapter;
1656 } else {
1657 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1658 }
1659 }
1660 switch (connector_type) {
1661 case DRM_MODE_CONNECTOR_VGA:
1662 case DRM_MODE_CONNECTOR_DVIA:
1663 default:
1664 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1665 funcs: &amdgpu_connector_dp_funcs,
1666 connector_type,
1667 ddc);
1668 drm_connector_helper_add(connector: &amdgpu_connector->base,
1669 funcs: &amdgpu_connector_dp_helper_funcs);
1670 connector->interlace_allowed = true;
1671 connector->doublescan_allowed = true;
1672 amdgpu_connector->dac_load_detect = true;
1673 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1674 property: adev->mode_info.load_detect_property,
1675 init_val: 1);
1676 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1677 property: dev->mode_config.scaling_mode_property,
1678 DRM_MODE_SCALE_NONE);
1679 break;
1680 case DRM_MODE_CONNECTOR_DVII:
1681 case DRM_MODE_CONNECTOR_DVID:
1682 case DRM_MODE_CONNECTOR_HDMIA:
1683 case DRM_MODE_CONNECTOR_HDMIB:
1684 case DRM_MODE_CONNECTOR_DisplayPort:
1685 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1686 funcs: &amdgpu_connector_dp_funcs,
1687 connector_type,
1688 ddc);
1689 drm_connector_helper_add(connector: &amdgpu_connector->base,
1690 funcs: &amdgpu_connector_dp_helper_funcs);
1691 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1692 property: adev->mode_info.underscan_property,
1693 init_val: UNDERSCAN_OFF);
1694 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1695 property: adev->mode_info.underscan_hborder_property,
1696 init_val: 0);
1697 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1698 property: adev->mode_info.underscan_vborder_property,
1699 init_val: 0);
1700
1701 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1702 property: dev->mode_config.scaling_mode_property,
1703 DRM_MODE_SCALE_NONE);
1704
1705 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1706 property: adev->mode_info.dither_property,
1707 init_val: AMDGPU_FMT_DITHER_DISABLE);
1708
1709 if (amdgpu_audio != 0) {
1710 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1711 property: adev->mode_info.audio_property,
1712 init_val: AMDGPU_AUDIO_AUTO);
1713 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1714 }
1715
1716 subpixel_order = SubPixelHorizontalRGB;
1717 connector->interlace_allowed = true;
1718 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1719 connector->doublescan_allowed = true;
1720 else
1721 connector->doublescan_allowed = false;
1722 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1723 amdgpu_connector->dac_load_detect = true;
1724 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1725 property: adev->mode_info.load_detect_property,
1726 init_val: 1);
1727 }
1728 break;
1729 case DRM_MODE_CONNECTOR_LVDS:
1730 case DRM_MODE_CONNECTOR_eDP:
1731 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1732 funcs: &amdgpu_connector_edp_funcs,
1733 connector_type,
1734 ddc);
1735 drm_connector_helper_add(connector: &amdgpu_connector->base,
1736 funcs: &amdgpu_connector_dp_helper_funcs);
1737 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1738 property: dev->mode_config.scaling_mode_property,
1739 DRM_MODE_SCALE_FULLSCREEN);
1740 subpixel_order = SubPixelHorizontalRGB;
1741 connector->interlace_allowed = false;
1742 connector->doublescan_allowed = false;
1743 break;
1744 }
1745 } else {
1746 switch (connector_type) {
1747 case DRM_MODE_CONNECTOR_VGA:
1748 if (i2c_bus->valid) {
1749 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1750 if (!amdgpu_connector->ddc_bus)
1751 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1752 else
1753 ddc = &amdgpu_connector->ddc_bus->adapter;
1754 }
1755 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1756 funcs: &amdgpu_connector_vga_funcs,
1757 connector_type,
1758 ddc);
1759 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_vga_helper_funcs);
1760 amdgpu_connector->dac_load_detect = true;
1761 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1762 property: adev->mode_info.load_detect_property,
1763 init_val: 1);
1764 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1765 property: dev->mode_config.scaling_mode_property,
1766 DRM_MODE_SCALE_NONE);
1767 /* no HPD on analog connectors */
1768 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1769 connector->interlace_allowed = true;
1770 connector->doublescan_allowed = true;
1771 break;
1772 case DRM_MODE_CONNECTOR_DVIA:
1773 if (i2c_bus->valid) {
1774 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1775 if (!amdgpu_connector->ddc_bus)
1776 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1777 else
1778 ddc = &amdgpu_connector->ddc_bus->adapter;
1779 }
1780 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1781 funcs: &amdgpu_connector_vga_funcs,
1782 connector_type,
1783 ddc);
1784 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_vga_helper_funcs);
1785 amdgpu_connector->dac_load_detect = true;
1786 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1787 property: adev->mode_info.load_detect_property,
1788 init_val: 1);
1789 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1790 property: dev->mode_config.scaling_mode_property,
1791 DRM_MODE_SCALE_NONE);
1792 /* no HPD on analog connectors */
1793 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1794 connector->interlace_allowed = true;
1795 connector->doublescan_allowed = true;
1796 break;
1797 case DRM_MODE_CONNECTOR_DVII:
1798 case DRM_MODE_CONNECTOR_DVID:
1799 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1800 if (!amdgpu_dig_connector)
1801 goto failed;
1802 amdgpu_connector->con_priv = amdgpu_dig_connector;
1803 if (i2c_bus->valid) {
1804 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1805 if (!amdgpu_connector->ddc_bus)
1806 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1807 else
1808 ddc = &amdgpu_connector->ddc_bus->adapter;
1809 }
1810 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1811 funcs: &amdgpu_connector_dvi_funcs,
1812 connector_type,
1813 ddc);
1814 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_dvi_helper_funcs);
1815 subpixel_order = SubPixelHorizontalRGB;
1816 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1817 property: adev->mode_info.coherent_mode_property,
1818 init_val: 1);
1819 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1820 property: adev->mode_info.underscan_property,
1821 init_val: UNDERSCAN_OFF);
1822 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1823 property: adev->mode_info.underscan_hborder_property,
1824 init_val: 0);
1825 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1826 property: adev->mode_info.underscan_vborder_property,
1827 init_val: 0);
1828 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1829 property: dev->mode_config.scaling_mode_property,
1830 DRM_MODE_SCALE_NONE);
1831
1832 if (amdgpu_audio != 0) {
1833 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1834 property: adev->mode_info.audio_property,
1835 init_val: AMDGPU_AUDIO_AUTO);
1836 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1837 }
1838 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1839 property: adev->mode_info.dither_property,
1840 init_val: AMDGPU_FMT_DITHER_DISABLE);
1841 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1842 amdgpu_connector->dac_load_detect = true;
1843 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1844 property: adev->mode_info.load_detect_property,
1845 init_val: 1);
1846 }
1847 connector->interlace_allowed = true;
1848 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1849 connector->doublescan_allowed = true;
1850 else
1851 connector->doublescan_allowed = false;
1852 break;
1853 case DRM_MODE_CONNECTOR_HDMIA:
1854 case DRM_MODE_CONNECTOR_HDMIB:
1855 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1856 if (!amdgpu_dig_connector)
1857 goto failed;
1858 amdgpu_connector->con_priv = amdgpu_dig_connector;
1859 if (i2c_bus->valid) {
1860 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1861 if (!amdgpu_connector->ddc_bus)
1862 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1863 else
1864 ddc = &amdgpu_connector->ddc_bus->adapter;
1865 }
1866 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1867 funcs: &amdgpu_connector_dvi_funcs,
1868 connector_type,
1869 ddc);
1870 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_dvi_helper_funcs);
1871 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1872 property: adev->mode_info.coherent_mode_property,
1873 init_val: 1);
1874 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1875 property: adev->mode_info.underscan_property,
1876 init_val: UNDERSCAN_OFF);
1877 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1878 property: adev->mode_info.underscan_hborder_property,
1879 init_val: 0);
1880 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1881 property: adev->mode_info.underscan_vborder_property,
1882 init_val: 0);
1883 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1884 property: dev->mode_config.scaling_mode_property,
1885 DRM_MODE_SCALE_NONE);
1886 if (amdgpu_audio != 0) {
1887 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1888 property: adev->mode_info.audio_property,
1889 init_val: AMDGPU_AUDIO_AUTO);
1890 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1891 }
1892 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1893 property: adev->mode_info.dither_property,
1894 init_val: AMDGPU_FMT_DITHER_DISABLE);
1895 subpixel_order = SubPixelHorizontalRGB;
1896 connector->interlace_allowed = true;
1897 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1898 connector->doublescan_allowed = true;
1899 else
1900 connector->doublescan_allowed = false;
1901 break;
1902 case DRM_MODE_CONNECTOR_DisplayPort:
1903 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1904 if (!amdgpu_dig_connector)
1905 goto failed;
1906 amdgpu_connector->con_priv = amdgpu_dig_connector;
1907 if (i2c_bus->valid) {
1908 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1909 if (amdgpu_connector->ddc_bus) {
1910 has_aux = true;
1911 ddc = &amdgpu_connector->ddc_bus->adapter;
1912 } else {
1913 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1914 }
1915 }
1916 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1917 funcs: &amdgpu_connector_dp_funcs,
1918 connector_type,
1919 ddc);
1920 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_dp_helper_funcs);
1921 subpixel_order = SubPixelHorizontalRGB;
1922 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1923 property: adev->mode_info.coherent_mode_property,
1924 init_val: 1);
1925 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1926 property: adev->mode_info.underscan_property,
1927 init_val: UNDERSCAN_OFF);
1928 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1929 property: adev->mode_info.underscan_hborder_property,
1930 init_val: 0);
1931 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1932 property: adev->mode_info.underscan_vborder_property,
1933 init_val: 0);
1934 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1935 property: dev->mode_config.scaling_mode_property,
1936 DRM_MODE_SCALE_NONE);
1937 if (amdgpu_audio != 0) {
1938 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1939 property: adev->mode_info.audio_property,
1940 init_val: AMDGPU_AUDIO_AUTO);
1941 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1942 }
1943 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1944 property: adev->mode_info.dither_property,
1945 init_val: AMDGPU_FMT_DITHER_DISABLE);
1946 connector->interlace_allowed = true;
1947 /* in theory with a DP to VGA converter... */
1948 connector->doublescan_allowed = false;
1949 break;
1950 case DRM_MODE_CONNECTOR_eDP:
1951 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1952 if (!amdgpu_dig_connector)
1953 goto failed;
1954 amdgpu_connector->con_priv = amdgpu_dig_connector;
1955 if (i2c_bus->valid) {
1956 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1957 if (amdgpu_connector->ddc_bus) {
1958 has_aux = true;
1959 ddc = &amdgpu_connector->ddc_bus->adapter;
1960 } else {
1961 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1962 }
1963 }
1964 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1965 funcs: &amdgpu_connector_edp_funcs,
1966 connector_type,
1967 ddc);
1968 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_dp_helper_funcs);
1969 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1970 property: dev->mode_config.scaling_mode_property,
1971 DRM_MODE_SCALE_FULLSCREEN);
1972 subpixel_order = SubPixelHorizontalRGB;
1973 connector->interlace_allowed = false;
1974 connector->doublescan_allowed = false;
1975 break;
1976 case DRM_MODE_CONNECTOR_LVDS:
1977 amdgpu_dig_connector = kzalloc(size: sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1978 if (!amdgpu_dig_connector)
1979 goto failed;
1980 amdgpu_connector->con_priv = amdgpu_dig_connector;
1981 if (i2c_bus->valid) {
1982 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1983 if (!amdgpu_connector->ddc_bus)
1984 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1985 else
1986 ddc = &amdgpu_connector->ddc_bus->adapter;
1987 }
1988 drm_connector_init_with_ddc(dev, connector: &amdgpu_connector->base,
1989 funcs: &amdgpu_connector_lvds_funcs,
1990 connector_type,
1991 ddc);
1992 drm_connector_helper_add(connector: &amdgpu_connector->base, funcs: &amdgpu_connector_lvds_helper_funcs);
1993 drm_object_attach_property(obj: &amdgpu_connector->base.base,
1994 property: dev->mode_config.scaling_mode_property,
1995 DRM_MODE_SCALE_FULLSCREEN);
1996 subpixel_order = SubPixelHorizontalRGB;
1997 connector->interlace_allowed = false;
1998 connector->doublescan_allowed = false;
1999 break;
2000 }
2001 }
2002
2003 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2004 if (i2c_bus->valid) {
2005 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2006 DRM_CONNECTOR_POLL_DISCONNECT;
2007 }
2008 } else
2009 connector->polled = DRM_CONNECTOR_POLL_HPD;
2010
2011 connector->display_info.subpixel_order = subpixel_order;
2012
2013 if (has_aux)
2014 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2015
2016 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2017 connector_type == DRM_MODE_CONNECTOR_eDP) {
2018 drm_connector_attach_dp_subconnector_property(connector: &amdgpu_connector->base);
2019 }
2020
2021 return;
2022
2023failed:
2024 drm_connector_cleanup(connector);
2025 kfree(objp: connector);
2026}
2027

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c