1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drmP.h>
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27
28/**
29 * amdgpu_ih_ring_init - initialize the IH state
30 *
31 * @adev: amdgpu_device pointer
32 * @ih: ih ring to initialize
33 * @ring_size: ring size to allocate
34 * @use_bus_addr: true when we can use dma_alloc_coherent
35 *
36 * Initializes the IH state and allocates a buffer
37 * for the IH ring buffer.
38 * Returns 0 for success, errors for failure.
39 */
40int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
41 unsigned ring_size, bool use_bus_addr)
42{
43 u32 rb_bufsz;
44 int r;
45
46 /* Align ring size */
47 rb_bufsz = order_base_2(ring_size / 4);
48 ring_size = (1 << rb_bufsz) * 4;
49 ih->ring_size = ring_size;
50 ih->ptr_mask = ih->ring_size - 1;
51 ih->rptr = 0;
52 ih->use_bus_addr = use_bus_addr;
53
54 if (use_bus_addr) {
55 dma_addr_t dma_addr;
56
57 if (ih->ring)
58 return 0;
59
60 /* add 8 bytes for the rptr/wptr shadows and
61 * add them to the end of the ring allocation.
62 */
63 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
64 &dma_addr, GFP_KERNEL);
65 if (ih->ring == NULL)
66 return -ENOMEM;
67
68 memset((void *)ih->ring, 0, ih->ring_size + 8);
69 ih->gpu_addr = dma_addr;
70 ih->wptr_addr = dma_addr + ih->ring_size;
71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
72 ih->rptr_addr = dma_addr + ih->ring_size + 4;
73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
74 } else {
75 unsigned wptr_offs, rptr_offs;
76
77 r = amdgpu_device_wb_get(adev, &wptr_offs);
78 if (r)
79 return r;
80
81 r = amdgpu_device_wb_get(adev, &rptr_offs);
82 if (r) {
83 amdgpu_device_wb_free(adev, wptr_offs);
84 return r;
85 }
86
87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
88 AMDGPU_GEM_DOMAIN_GTT,
89 &ih->ring_obj, &ih->gpu_addr,
90 (void **)&ih->ring);
91 if (r) {
92 amdgpu_device_wb_free(adev, rptr_offs);
93 amdgpu_device_wb_free(adev, wptr_offs);
94 return r;
95 }
96
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs];
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
100 ih->rptr_cpu = &adev->wb.wb[rptr_offs];
101 }
102 return 0;
103}
104
105/**
106 * amdgpu_ih_ring_fini - tear down the IH state
107 *
108 * @adev: amdgpu_device pointer
109 * @ih: ih ring to tear down
110 *
111 * Tears down the IH state and frees buffer
112 * used for the IH ring buffer.
113 */
114void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
115{
116 if (ih->use_bus_addr) {
117 if (!ih->ring)
118 return;
119
120 /* add 8 bytes for the rptr/wptr shadows and
121 * add them to the end of the ring allocation.
122 */
123 dma_free_coherent(adev->dev, ih->ring_size + 8,
124 (void *)ih->ring, ih->gpu_addr);
125 ih->ring = NULL;
126 } else {
127 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
128 (void **)&ih->ring);
129 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
130 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
131 }
132}
133
134/**
135 * amdgpu_ih_process - interrupt handler
136 *
137 * @adev: amdgpu_device pointer
138 * @ih: ih ring to process
139 *
140 * Interrupt hander (VI), walk the IH ring.
141 * Returns irq process return code.
142 */
143int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
144{
145 u32 wptr;
146
147 if (!ih->enabled || adev->shutdown)
148 return IRQ_NONE;
149
150 wptr = amdgpu_ih_get_wptr(adev, ih);
151
152restart_ih:
153 /* is somebody else already processing irqs? */
154 if (atomic_xchg(&ih->lock, 1))
155 return IRQ_NONE;
156
157 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
158
159 /* Order reading of wptr vs. reading of IH ring data */
160 rmb();
161
162 while (ih->rptr != wptr) {
163 amdgpu_irq_dispatch(adev, ih);
164 ih->rptr &= ih->ptr_mask;
165 }
166
167 amdgpu_ih_set_rptr(adev, ih);
168 atomic_set(&ih->lock, 0);
169
170 /* make sure wptr hasn't changed while processing */
171 wptr = amdgpu_ih_get_wptr(adev, ih);
172 if (wptr != ih->rptr)
173 goto restart_ih;
174
175 return IRQ_HANDLED;
176}
177
178