1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_IRQ_H__
25#define __AMDGPU_IRQ_H__
26
27#include <linux/irqdomain.h>
28#include "soc15_ih_clientid.h"
29#include "amdgpu_ih.h"
30
31#define AMDGPU_MAX_IRQ_SRC_ID 0x100
32#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
33
34#define AMDGPU_IRQ_CLIENTID_LEGACY 0
35#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
36
37#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
38
39struct amdgpu_device;
40
41enum amdgpu_interrupt_state {
42 AMDGPU_IRQ_STATE_DISABLE,
43 AMDGPU_IRQ_STATE_ENABLE,
44};
45
46struct amdgpu_iv_entry {
47 unsigned client_id;
48 unsigned src_id;
49 unsigned ring_id;
50 unsigned vmid;
51 unsigned vmid_src;
52 uint64_t timestamp;
53 unsigned timestamp_src;
54 unsigned pasid;
55 unsigned pasid_src;
56 unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
57 const uint32_t *iv_entry;
58};
59
60struct amdgpu_irq_src {
61 unsigned num_types;
62 atomic_t *enabled_types;
63 const struct amdgpu_irq_src_funcs *funcs;
64 void *data;
65};
66
67struct amdgpu_irq_client {
68 struct amdgpu_irq_src **sources;
69};
70
71/* provided by interrupt generating IP blocks */
72struct amdgpu_irq_src_funcs {
73 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
74 unsigned type, enum amdgpu_interrupt_state state);
75
76 int (*process)(struct amdgpu_device *adev,
77 struct amdgpu_irq_src *source,
78 struct amdgpu_iv_entry *entry);
79};
80
81struct amdgpu_irq {
82 bool installed;
83 spinlock_t lock;
84 /* interrupt sources */
85 struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
86
87 /* status, etc. */
88 bool msi_enabled; /* msi enabled */
89
90 /* interrupt rings */
91 struct amdgpu_ih_ring ih, ih1, ih2;
92 const struct amdgpu_ih_funcs *ih_funcs;
93 struct work_struct ih1_work, ih2_work;
94 struct amdgpu_irq_src self_irq;
95
96 /* gen irq stuff */
97 struct irq_domain *domain; /* GPU irq controller domain */
98 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
99 uint32_t srbm_soft_reset;
100};
101
102void amdgpu_irq_disable_all(struct amdgpu_device *adev);
103irqreturn_t amdgpu_irq_handler(int irq, void *arg);
104
105int amdgpu_irq_init(struct amdgpu_device *adev);
106void amdgpu_irq_fini(struct amdgpu_device *adev);
107int amdgpu_irq_add_id(struct amdgpu_device *adev,
108 unsigned client_id, unsigned src_id,
109 struct amdgpu_irq_src *source);
110void amdgpu_irq_dispatch(struct amdgpu_device *adev,
111 struct amdgpu_ih_ring *ih);
112int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
113 unsigned type);
114int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
115 unsigned type);
116int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
117 unsigned type);
118bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
119 unsigned type);
120void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
121
122int amdgpu_irq_add_domain(struct amdgpu_device *adev);
123void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
124unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
125
126#endif
127