1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_JOB_H__
24#define __AMDGPU_JOB_H__
25
26/* bit set means command submit involves a preamble IB */
27#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0)
28/* bit set means preamble IB is first presented in belonging context */
29#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
30/* bit set means context switch occured */
31#define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
32
33#define to_amdgpu_job(sched_job) \
34 container_of((sched_job), struct amdgpu_job, base)
35
36#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
37
38struct amdgpu_fence;
39
40struct amdgpu_job {
41 struct drm_sched_job base;
42 struct amdgpu_vm *vm;
43 struct amdgpu_sync sync;
44 struct amdgpu_sync sched_sync;
45 struct amdgpu_ib *ibs;
46 struct dma_fence *fence; /* the hw fence */
47 uint32_t preamble_status;
48 uint32_t num_ibs;
49 void *owner;
50 bool vm_needs_flush;
51 uint64_t vm_pd_addr;
52 unsigned vmid;
53 unsigned pasid;
54 uint32_t gds_base, gds_size;
55 uint32_t gws_base, gws_size;
56 uint32_t oa_base, oa_size;
57 uint32_t vram_lost_counter;
58
59 /* user fence handling */
60 uint64_t uf_addr;
61 uint64_t uf_sequence;
62
63};
64
65int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
66 struct amdgpu_job **job, struct amdgpu_vm *vm);
67int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
68 struct amdgpu_job **job);
69
70void amdgpu_job_free_resources(struct amdgpu_job *job);
71void amdgpu_job_free(struct amdgpu_job *job);
72int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
73 void *owner, struct dma_fence **f);
74int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
75 struct dma_fence **fence);
76#endif
77