1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
3 | * VA Linux Systems Inc., Fremont, California. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Original Authors: |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
26 | * |
27 | * Kernel port Author: Dave Airlie |
28 | */ |
29 | |
30 | #ifndef AMDGPU_MODE_H |
31 | #define AMDGPU_MODE_H |
32 | |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> |
35 | #include <drm/drm_encoder.h> |
36 | #include <drm/drm_dp_helper.h> |
37 | #include <drm/drm_fixed.h> |
38 | #include <drm/drm_crtc_helper.h> |
39 | #include <drm/drm_fb_helper.h> |
40 | #include <drm/drm_plane_helper.h> |
41 | #include <drm/drm_probe_helper.h> |
42 | #include <linux/i2c.h> |
43 | #include <linux/i2c-algo-bit.h> |
44 | #include <linux/hrtimer.h> |
45 | #include "amdgpu_irq.h" |
46 | |
47 | #include <drm/drm_dp_mst_helper.h> |
48 | #include "modules/inc/mod_freesync.h" |
49 | |
50 | struct amdgpu_bo; |
51 | struct amdgpu_device; |
52 | struct amdgpu_encoder; |
53 | struct amdgpu_router; |
54 | struct amdgpu_hpd; |
55 | |
56 | #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) |
57 | #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) |
58 | #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) |
59 | #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) |
60 | |
61 | #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base); |
62 | |
63 | #define AMDGPU_MAX_HPD_PINS 6 |
64 | #define AMDGPU_MAX_CRTCS 6 |
65 | #define AMDGPU_MAX_PLANES 6 |
66 | #define AMDGPU_MAX_AFMT_BLOCKS 9 |
67 | |
68 | enum amdgpu_rmx_type { |
69 | RMX_OFF, |
70 | RMX_FULL, |
71 | RMX_CENTER, |
72 | RMX_ASPECT |
73 | }; |
74 | |
75 | enum amdgpu_underscan_type { |
76 | UNDERSCAN_OFF, |
77 | UNDERSCAN_ON, |
78 | UNDERSCAN_AUTO, |
79 | }; |
80 | |
81 | #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 |
82 | #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 |
83 | |
84 | enum amdgpu_hpd_id { |
85 | AMDGPU_HPD_1 = 0, |
86 | AMDGPU_HPD_2, |
87 | AMDGPU_HPD_3, |
88 | AMDGPU_HPD_4, |
89 | AMDGPU_HPD_5, |
90 | AMDGPU_HPD_6, |
91 | AMDGPU_HPD_NONE = 0xff, |
92 | }; |
93 | |
94 | enum amdgpu_crtc_irq { |
95 | AMDGPU_CRTC_IRQ_VBLANK1 = 0, |
96 | AMDGPU_CRTC_IRQ_VBLANK2, |
97 | AMDGPU_CRTC_IRQ_VBLANK3, |
98 | AMDGPU_CRTC_IRQ_VBLANK4, |
99 | AMDGPU_CRTC_IRQ_VBLANK5, |
100 | AMDGPU_CRTC_IRQ_VBLANK6, |
101 | AMDGPU_CRTC_IRQ_VLINE1, |
102 | AMDGPU_CRTC_IRQ_VLINE2, |
103 | AMDGPU_CRTC_IRQ_VLINE3, |
104 | AMDGPU_CRTC_IRQ_VLINE4, |
105 | AMDGPU_CRTC_IRQ_VLINE5, |
106 | AMDGPU_CRTC_IRQ_VLINE6, |
107 | AMDGPU_CRTC_IRQ_NONE = 0xff |
108 | }; |
109 | |
110 | enum amdgpu_pageflip_irq { |
111 | AMDGPU_PAGEFLIP_IRQ_D1 = 0, |
112 | AMDGPU_PAGEFLIP_IRQ_D2, |
113 | AMDGPU_PAGEFLIP_IRQ_D3, |
114 | AMDGPU_PAGEFLIP_IRQ_D4, |
115 | AMDGPU_PAGEFLIP_IRQ_D5, |
116 | AMDGPU_PAGEFLIP_IRQ_D6, |
117 | AMDGPU_PAGEFLIP_IRQ_NONE = 0xff |
118 | }; |
119 | |
120 | enum amdgpu_flip_status { |
121 | AMDGPU_FLIP_NONE, |
122 | AMDGPU_FLIP_PENDING, |
123 | AMDGPU_FLIP_SUBMITTED |
124 | }; |
125 | |
126 | #define AMDGPU_MAX_I2C_BUS 16 |
127 | |
128 | /* amdgpu gpio-based i2c |
129 | * 1. "mask" reg and bits |
130 | * grabs the gpio pins for software use |
131 | * 0=not held 1=held |
132 | * 2. "a" reg and bits |
133 | * output pin value |
134 | * 0=low 1=high |
135 | * 3. "en" reg and bits |
136 | * sets the pin direction |
137 | * 0=input 1=output |
138 | * 4. "y" reg and bits |
139 | * input pin value |
140 | * 0=low 1=high |
141 | */ |
142 | struct amdgpu_i2c_bus_rec { |
143 | bool valid; |
144 | /* id used by atom */ |
145 | uint8_t i2c_id; |
146 | /* id used by atom */ |
147 | enum amdgpu_hpd_id hpd; |
148 | /* can be used with hw i2c engine */ |
149 | bool hw_capable; |
150 | /* uses multi-media i2c engine */ |
151 | bool mm_i2c; |
152 | /* regs and bits */ |
153 | uint32_t mask_clk_reg; |
154 | uint32_t mask_data_reg; |
155 | uint32_t a_clk_reg; |
156 | uint32_t a_data_reg; |
157 | uint32_t en_clk_reg; |
158 | uint32_t en_data_reg; |
159 | uint32_t y_clk_reg; |
160 | uint32_t y_data_reg; |
161 | uint32_t mask_clk_mask; |
162 | uint32_t mask_data_mask; |
163 | uint32_t a_clk_mask; |
164 | uint32_t a_data_mask; |
165 | uint32_t en_clk_mask; |
166 | uint32_t en_data_mask; |
167 | uint32_t y_clk_mask; |
168 | uint32_t y_data_mask; |
169 | }; |
170 | |
171 | #define AMDGPU_MAX_BIOS_CONNECTOR 16 |
172 | |
173 | /* pll flags */ |
174 | #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) |
175 | #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) |
176 | #define AMDGPU_PLL_USE_REF_DIV (1 << 2) |
177 | #define AMDGPU_PLL_LEGACY (1 << 3) |
178 | #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) |
179 | #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
180 | #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) |
181 | #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
182 | #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) |
183 | #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
184 | #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) |
185 | #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
186 | #define AMDGPU_PLL_USE_POST_DIV (1 << 12) |
187 | #define AMDGPU_PLL_IS_LCD (1 << 13) |
188 | #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
189 | |
190 | struct amdgpu_pll { |
191 | /* reference frequency */ |
192 | uint32_t reference_freq; |
193 | |
194 | /* fixed dividers */ |
195 | uint32_t reference_div; |
196 | uint32_t post_div; |
197 | |
198 | /* pll in/out limits */ |
199 | uint32_t pll_in_min; |
200 | uint32_t pll_in_max; |
201 | uint32_t pll_out_min; |
202 | uint32_t pll_out_max; |
203 | uint32_t lcd_pll_out_min; |
204 | uint32_t lcd_pll_out_max; |
205 | uint32_t best_vco; |
206 | |
207 | /* divider limits */ |
208 | uint32_t min_ref_div; |
209 | uint32_t max_ref_div; |
210 | uint32_t min_post_div; |
211 | uint32_t max_post_div; |
212 | uint32_t min_feedback_div; |
213 | uint32_t max_feedback_div; |
214 | uint32_t min_frac_feedback_div; |
215 | uint32_t max_frac_feedback_div; |
216 | |
217 | /* flags for the current clock */ |
218 | uint32_t flags; |
219 | |
220 | /* pll id */ |
221 | uint32_t id; |
222 | }; |
223 | |
224 | struct amdgpu_i2c_chan { |
225 | struct i2c_adapter adapter; |
226 | struct drm_device *dev; |
227 | struct i2c_algo_bit_data bit; |
228 | struct amdgpu_i2c_bus_rec rec; |
229 | struct drm_dp_aux aux; |
230 | bool has_aux; |
231 | struct mutex mutex; |
232 | }; |
233 | |
234 | struct amdgpu_fbdev; |
235 | |
236 | struct amdgpu_afmt { |
237 | bool enabled; |
238 | int offset; |
239 | bool last_buffer_filled_status; |
240 | int id; |
241 | struct amdgpu_audio_pin *pin; |
242 | }; |
243 | |
244 | /* |
245 | * Audio |
246 | */ |
247 | struct amdgpu_audio_pin { |
248 | int channels; |
249 | int rate; |
250 | int bits_per_sample; |
251 | u8 status_bits; |
252 | u8 category_code; |
253 | u32 offset; |
254 | bool connected; |
255 | u32 id; |
256 | }; |
257 | |
258 | struct amdgpu_audio { |
259 | bool enabled; |
260 | struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; |
261 | int num_pins; |
262 | }; |
263 | |
264 | struct amdgpu_display_funcs { |
265 | /* display watermarks */ |
266 | void (*bandwidth_update)(struct amdgpu_device *adev); |
267 | /* get frame count */ |
268 | u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); |
269 | /* set backlight level */ |
270 | void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, |
271 | u8 level); |
272 | /* get backlight level */ |
273 | u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); |
274 | /* hotplug detect */ |
275 | bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); |
276 | void (*hpd_set_polarity)(struct amdgpu_device *adev, |
277 | enum amdgpu_hpd_id hpd); |
278 | u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); |
279 | /* pageflipping */ |
280 | void (*page_flip)(struct amdgpu_device *adev, |
281 | int crtc_id, u64 crtc_base, bool async); |
282 | int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, |
283 | u32 *vbl, u32 *position); |
284 | /* display topology setup */ |
285 | void (*add_encoder)(struct amdgpu_device *adev, |
286 | uint32_t encoder_enum, |
287 | uint32_t supported_device, |
288 | u16 caps); |
289 | void (*add_connector)(struct amdgpu_device *adev, |
290 | uint32_t connector_id, |
291 | uint32_t supported_device, |
292 | int connector_type, |
293 | struct amdgpu_i2c_bus_rec *i2c_bus, |
294 | uint16_t connector_object_id, |
295 | struct amdgpu_hpd *hpd, |
296 | struct amdgpu_router *router); |
297 | |
298 | |
299 | }; |
300 | |
301 | struct amdgpu_framebuffer { |
302 | struct drm_framebuffer base; |
303 | |
304 | /* caching for later use */ |
305 | uint64_t address; |
306 | }; |
307 | |
308 | struct amdgpu_fbdev { |
309 | struct drm_fb_helper helper; |
310 | struct amdgpu_framebuffer rfb; |
311 | struct list_head fbdev_list; |
312 | struct amdgpu_device *adev; |
313 | }; |
314 | |
315 | struct amdgpu_mode_info { |
316 | struct atom_context *atom_context; |
317 | struct card_info *atom_card_info; |
318 | bool mode_config_initialized; |
319 | struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; |
320 | struct drm_plane *planes[AMDGPU_MAX_PLANES]; |
321 | struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; |
322 | /* DVI-I properties */ |
323 | struct drm_property *coherent_mode_property; |
324 | /* DAC enable load detect */ |
325 | struct drm_property *load_detect_property; |
326 | /* underscan */ |
327 | struct drm_property *underscan_property; |
328 | struct drm_property *underscan_hborder_property; |
329 | struct drm_property *underscan_vborder_property; |
330 | /* audio */ |
331 | struct drm_property *audio_property; |
332 | /* FMT dithering */ |
333 | struct drm_property *dither_property; |
334 | /* maximum number of bits per channel for monitor color */ |
335 | struct drm_property *max_bpc_property; |
336 | /* Adaptive Backlight Modulation (power feature) */ |
337 | struct drm_property *abm_level_property; |
338 | /* hardcoded DFP edid from BIOS */ |
339 | struct edid *bios_hardcoded_edid; |
340 | int bios_hardcoded_edid_size; |
341 | |
342 | /* pointer to fbdev info structure */ |
343 | struct amdgpu_fbdev *rfbdev; |
344 | /* firmware flags */ |
345 | u16 firmware_flags; |
346 | /* pointer to backlight encoder */ |
347 | struct amdgpu_encoder *bl_encoder; |
348 | u8 bl_level; /* saved backlight level */ |
349 | struct amdgpu_audio audio; /* audio stuff */ |
350 | int num_crtc; /* number of crtcs */ |
351 | int num_hpd; /* number of hpd pins */ |
352 | int num_dig; /* number of dig blocks */ |
353 | int disp_priority; |
354 | const struct amdgpu_display_funcs *funcs; |
355 | const enum drm_plane_type *plane_type; |
356 | }; |
357 | |
358 | #define AMDGPU_MAX_BL_LEVEL 0xFF |
359 | |
360 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
361 | |
362 | struct amdgpu_backlight_privdata { |
363 | struct amdgpu_encoder *encoder; |
364 | uint8_t negative; |
365 | }; |
366 | |
367 | #endif |
368 | |
369 | struct amdgpu_atom_ss { |
370 | uint16_t percentage; |
371 | uint16_t percentage_divider; |
372 | uint8_t type; |
373 | uint16_t step; |
374 | uint8_t delay; |
375 | uint8_t range; |
376 | uint8_t refdiv; |
377 | /* asic_ss */ |
378 | uint16_t rate; |
379 | uint16_t amount; |
380 | }; |
381 | |
382 | struct amdgpu_crtc { |
383 | struct drm_crtc base; |
384 | int crtc_id; |
385 | bool enabled; |
386 | bool can_tile; |
387 | uint32_t crtc_offset; |
388 | struct drm_gem_object *cursor_bo; |
389 | uint64_t cursor_addr; |
390 | int cursor_x; |
391 | int cursor_y; |
392 | int cursor_hot_x; |
393 | int cursor_hot_y; |
394 | int cursor_width; |
395 | int cursor_height; |
396 | int max_cursor_width; |
397 | int max_cursor_height; |
398 | enum amdgpu_rmx_type rmx_type; |
399 | u8 h_border; |
400 | u8 v_border; |
401 | fixed20_12 vsc; |
402 | fixed20_12 hsc; |
403 | struct drm_display_mode native_mode; |
404 | u32 pll_id; |
405 | /* page flipping */ |
406 | struct amdgpu_flip_work *pflip_works; |
407 | enum amdgpu_flip_status pflip_status; |
408 | int deferred_flip_completion; |
409 | u64 last_flip_vblank; |
410 | /* pll sharing */ |
411 | struct amdgpu_atom_ss ss; |
412 | bool ss_enabled; |
413 | u32 adjusted_clock; |
414 | int bpc; |
415 | u32 pll_reference_div; |
416 | u32 pll_post_div; |
417 | u32 pll_flags; |
418 | struct drm_encoder *encoder; |
419 | struct drm_connector *connector; |
420 | /* for dpm */ |
421 | u32 line_time; |
422 | u32 wm_low; |
423 | u32 wm_high; |
424 | u32 lb_vblank_lead_lines; |
425 | struct drm_display_mode hw_mode; |
426 | /* for virtual dce */ |
427 | struct hrtimer vblank_timer; |
428 | enum amdgpu_interrupt_state vsync_timer_enabled; |
429 | |
430 | int otg_inst; |
431 | struct drm_pending_vblank_event *event; |
432 | }; |
433 | |
434 | struct amdgpu_encoder_atom_dig { |
435 | bool linkb; |
436 | /* atom dig */ |
437 | bool coherent_mode; |
438 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
439 | /* atom lvds/edp */ |
440 | uint32_t lcd_misc; |
441 | uint16_t panel_pwr_delay; |
442 | uint32_t lcd_ss_id; |
443 | /* panel mode */ |
444 | struct drm_display_mode native_mode; |
445 | struct backlight_device *bl_dev; |
446 | int dpms_mode; |
447 | uint8_t backlight_level; |
448 | int panel_mode; |
449 | struct amdgpu_afmt *afmt; |
450 | }; |
451 | |
452 | struct amdgpu_encoder { |
453 | struct drm_encoder base; |
454 | uint32_t encoder_enum; |
455 | uint32_t encoder_id; |
456 | uint32_t devices; |
457 | uint32_t active_device; |
458 | uint32_t flags; |
459 | uint32_t pixel_clock; |
460 | enum amdgpu_rmx_type rmx_type; |
461 | enum amdgpu_underscan_type underscan_type; |
462 | uint32_t underscan_hborder; |
463 | uint32_t underscan_vborder; |
464 | struct drm_display_mode native_mode; |
465 | void *enc_priv; |
466 | int audio_polling_active; |
467 | bool is_ext_encoder; |
468 | u16 caps; |
469 | }; |
470 | |
471 | struct amdgpu_connector_atom_dig { |
472 | /* displayport */ |
473 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
474 | u8 dp_sink_type; |
475 | int dp_clock; |
476 | int dp_lane_count; |
477 | bool edp_on; |
478 | }; |
479 | |
480 | struct amdgpu_gpio_rec { |
481 | bool valid; |
482 | u8 id; |
483 | u32 reg; |
484 | u32 mask; |
485 | u32 shift; |
486 | }; |
487 | |
488 | struct amdgpu_hpd { |
489 | enum amdgpu_hpd_id hpd; |
490 | u8 plugged_state; |
491 | struct amdgpu_gpio_rec gpio; |
492 | }; |
493 | |
494 | struct amdgpu_router { |
495 | u32 router_id; |
496 | struct amdgpu_i2c_bus_rec i2c_info; |
497 | u8 i2c_addr; |
498 | /* i2c mux */ |
499 | bool ddc_valid; |
500 | u8 ddc_mux_type; |
501 | u8 ddc_mux_control_pin; |
502 | u8 ddc_mux_state; |
503 | /* clock/data mux */ |
504 | bool cd_valid; |
505 | u8 cd_mux_type; |
506 | u8 cd_mux_control_pin; |
507 | u8 cd_mux_state; |
508 | }; |
509 | |
510 | enum amdgpu_connector_audio { |
511 | AMDGPU_AUDIO_DISABLE = 0, |
512 | AMDGPU_AUDIO_ENABLE = 1, |
513 | AMDGPU_AUDIO_AUTO = 2 |
514 | }; |
515 | |
516 | enum amdgpu_connector_dither { |
517 | AMDGPU_FMT_DITHER_DISABLE = 0, |
518 | AMDGPU_FMT_DITHER_ENABLE = 1, |
519 | }; |
520 | |
521 | struct amdgpu_dm_dp_aux { |
522 | struct drm_dp_aux aux; |
523 | struct ddc_service *ddc_service; |
524 | }; |
525 | |
526 | struct amdgpu_i2c_adapter { |
527 | struct i2c_adapter base; |
528 | |
529 | struct ddc_service *ddc_service; |
530 | }; |
531 | |
532 | #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) |
533 | |
534 | struct amdgpu_connector { |
535 | struct drm_connector base; |
536 | uint32_t connector_id; |
537 | uint32_t devices; |
538 | struct amdgpu_i2c_chan *ddc_bus; |
539 | /* some systems have an hdmi and vga port with a shared ddc line */ |
540 | bool shared_ddc; |
541 | bool use_digital; |
542 | /* we need to mind the EDID between detect |
543 | and get modes due to analog/digital/tvencoder */ |
544 | struct edid *edid; |
545 | void *con_priv; |
546 | bool dac_load_detect; |
547 | bool detected_by_load; /* if the connection status was determined by load */ |
548 | uint16_t connector_object_id; |
549 | struct amdgpu_hpd hpd; |
550 | struct amdgpu_router router; |
551 | struct amdgpu_i2c_chan *router_bus; |
552 | enum amdgpu_connector_audio audio; |
553 | enum amdgpu_connector_dither dither; |
554 | unsigned pixelclock_for_modeset; |
555 | }; |
556 | |
557 | /* TODO: start to use this struct and remove same field from base one */ |
558 | struct amdgpu_mst_connector { |
559 | struct amdgpu_connector base; |
560 | |
561 | struct drm_dp_mst_topology_mgr mst_mgr; |
562 | struct amdgpu_dm_dp_aux dm_dp_aux; |
563 | struct drm_dp_mst_port *port; |
564 | struct amdgpu_connector *mst_port; |
565 | bool is_mst_connector; |
566 | struct amdgpu_encoder *mst_encoder; |
567 | }; |
568 | |
569 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
570 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
571 | |
572 | /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ |
573 | #define DRM_SCANOUTPOS_VALID (1 << 0) |
574 | #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) |
575 | #define DRM_SCANOUTPOS_ACCURATE (1 << 2) |
576 | #define USE_REAL_VBLANKSTART (1 << 30) |
577 | #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) |
578 | |
579 | void amdgpu_link_encoder_connector(struct drm_device *dev); |
580 | |
581 | struct drm_connector * |
582 | amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); |
583 | struct drm_connector * |
584 | amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); |
585 | bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, |
586 | u32 pixel_clock); |
587 | |
588 | u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
589 | struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); |
590 | |
591 | bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, |
592 | bool use_aux); |
593 | |
594 | void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); |
595 | |
596 | int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, |
597 | unsigned int pipe, unsigned int flags, int *vpos, |
598 | int *hpos, ktime_t *stime, ktime_t *etime, |
599 | const struct drm_display_mode *mode); |
600 | |
601 | int amdgpu_display_framebuffer_init(struct drm_device *dev, |
602 | struct amdgpu_framebuffer *rfb, |
603 | const struct drm_mode_fb_cmd2 *mode_cmd, |
604 | struct drm_gem_object *obj); |
605 | |
606 | int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
607 | |
608 | void amdgpu_enc_destroy(struct drm_encoder *encoder); |
609 | void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
610 | bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
611 | const struct drm_display_mode *mode, |
612 | struct drm_display_mode *adjusted_mode); |
613 | void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, |
614 | struct drm_display_mode *adjusted_mode); |
615 | int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); |
616 | |
617 | /* fbdev layer */ |
618 | int amdgpu_fbdev_init(struct amdgpu_device *adev); |
619 | void amdgpu_fbdev_fini(struct amdgpu_device *adev); |
620 | void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); |
621 | int amdgpu_fbdev_total_size(struct amdgpu_device *adev); |
622 | bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); |
623 | |
624 | int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); |
625 | |
626 | /* amdgpu_display.c */ |
627 | void amdgpu_display_print_display_setup(struct drm_device *dev); |
628 | int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); |
629 | int amdgpu_display_crtc_set_config(struct drm_mode_set *set, |
630 | struct drm_modeset_acquire_ctx *ctx); |
631 | int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, |
632 | struct drm_framebuffer *fb, |
633 | struct drm_pending_vblank_event *event, |
634 | uint32_t page_flip_flags, uint32_t target, |
635 | struct drm_modeset_acquire_ctx *ctx); |
636 | extern const struct drm_mode_config_funcs amdgpu_mode_funcs; |
637 | |
638 | #endif |
639 | |