1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef AMDGPU_MODE_H
31#define AMDGPU_MODE_H
32
33#include <drm/display/drm_dp_helper.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_encoder.h>
37#include <drm/drm_fixed.h>
38#include <drm/drm_framebuffer.h>
39#include <drm/drm_probe_helper.h>
40#include <linux/i2c.h>
41#include <linux/i2c-algo-bit.h>
42#include <linux/hrtimer.h>
43#include "amdgpu_irq.h"
44
45#include <drm/display/drm_dp_mst_helper.h>
46#include "modules/inc/mod_freesync.h"
47#include "amdgpu_dm_irq_params.h"
48
49struct amdgpu_bo;
50struct amdgpu_device;
51struct amdgpu_encoder;
52struct amdgpu_router;
53struct amdgpu_hpd;
54
55#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
56#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
57#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
58#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
59
60#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
61
62#define AMDGPU_MAX_HPD_PINS 6
63#define AMDGPU_MAX_CRTCS 6
64#define AMDGPU_MAX_PLANES 6
65#define AMDGPU_MAX_AFMT_BLOCKS 9
66
67enum amdgpu_rmx_type {
68 RMX_OFF,
69 RMX_FULL,
70 RMX_CENTER,
71 RMX_ASPECT
72};
73
74enum amdgpu_underscan_type {
75 UNDERSCAN_OFF,
76 UNDERSCAN_ON,
77 UNDERSCAN_AUTO,
78};
79
80#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
81#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
82
83enum amdgpu_hpd_id {
84 AMDGPU_HPD_1 = 0,
85 AMDGPU_HPD_2,
86 AMDGPU_HPD_3,
87 AMDGPU_HPD_4,
88 AMDGPU_HPD_5,
89 AMDGPU_HPD_6,
90 AMDGPU_HPD_NONE = 0xff,
91};
92
93enum amdgpu_crtc_irq {
94 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
95 AMDGPU_CRTC_IRQ_VBLANK2,
96 AMDGPU_CRTC_IRQ_VBLANK3,
97 AMDGPU_CRTC_IRQ_VBLANK4,
98 AMDGPU_CRTC_IRQ_VBLANK5,
99 AMDGPU_CRTC_IRQ_VBLANK6,
100 AMDGPU_CRTC_IRQ_VLINE1,
101 AMDGPU_CRTC_IRQ_VLINE2,
102 AMDGPU_CRTC_IRQ_VLINE3,
103 AMDGPU_CRTC_IRQ_VLINE4,
104 AMDGPU_CRTC_IRQ_VLINE5,
105 AMDGPU_CRTC_IRQ_VLINE6,
106 AMDGPU_CRTC_IRQ_NONE = 0xff
107};
108
109enum amdgpu_pageflip_irq {
110 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
111 AMDGPU_PAGEFLIP_IRQ_D2,
112 AMDGPU_PAGEFLIP_IRQ_D3,
113 AMDGPU_PAGEFLIP_IRQ_D4,
114 AMDGPU_PAGEFLIP_IRQ_D5,
115 AMDGPU_PAGEFLIP_IRQ_D6,
116 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
117};
118
119enum amdgpu_flip_status {
120 AMDGPU_FLIP_NONE,
121 AMDGPU_FLIP_PENDING,
122 AMDGPU_FLIP_SUBMITTED
123};
124
125#define AMDGPU_MAX_I2C_BUS 16
126
127/* amdgpu gpio-based i2c
128 * 1. "mask" reg and bits
129 * grabs the gpio pins for software use
130 * 0=not held 1=held
131 * 2. "a" reg and bits
132 * output pin value
133 * 0=low 1=high
134 * 3. "en" reg and bits
135 * sets the pin direction
136 * 0=input 1=output
137 * 4. "y" reg and bits
138 * input pin value
139 * 0=low 1=high
140 */
141struct amdgpu_i2c_bus_rec {
142 bool valid;
143 /* id used by atom */
144 uint8_t i2c_id;
145 /* id used by atom */
146 enum amdgpu_hpd_id hpd;
147 /* can be used with hw i2c engine */
148 bool hw_capable;
149 /* uses multi-media i2c engine */
150 bool mm_i2c;
151 /* regs and bits */
152 uint32_t mask_clk_reg;
153 uint32_t mask_data_reg;
154 uint32_t a_clk_reg;
155 uint32_t a_data_reg;
156 uint32_t en_clk_reg;
157 uint32_t en_data_reg;
158 uint32_t y_clk_reg;
159 uint32_t y_data_reg;
160 uint32_t mask_clk_mask;
161 uint32_t mask_data_mask;
162 uint32_t a_clk_mask;
163 uint32_t a_data_mask;
164 uint32_t en_clk_mask;
165 uint32_t en_data_mask;
166 uint32_t y_clk_mask;
167 uint32_t y_data_mask;
168};
169
170#define AMDGPU_MAX_BIOS_CONNECTOR 16
171
172/* pll flags */
173#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
174#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
175#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
176#define AMDGPU_PLL_LEGACY (1 << 3)
177#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
178#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
179#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
180#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
181#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
182#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
183#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
184#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
185#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
186#define AMDGPU_PLL_IS_LCD (1 << 13)
187#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
188
189struct amdgpu_pll {
190 /* reference frequency */
191 uint32_t reference_freq;
192
193 /* fixed dividers */
194 uint32_t reference_div;
195 uint32_t post_div;
196
197 /* pll in/out limits */
198 uint32_t pll_in_min;
199 uint32_t pll_in_max;
200 uint32_t pll_out_min;
201 uint32_t pll_out_max;
202 uint32_t lcd_pll_out_min;
203 uint32_t lcd_pll_out_max;
204 uint32_t best_vco;
205
206 /* divider limits */
207 uint32_t min_ref_div;
208 uint32_t max_ref_div;
209 uint32_t min_post_div;
210 uint32_t max_post_div;
211 uint32_t min_feedback_div;
212 uint32_t max_feedback_div;
213 uint32_t min_frac_feedback_div;
214 uint32_t max_frac_feedback_div;
215
216 /* flags for the current clock */
217 uint32_t flags;
218
219 /* pll id */
220 uint32_t id;
221};
222
223struct amdgpu_i2c_chan {
224 struct i2c_adapter adapter;
225 struct drm_device *dev;
226 struct i2c_algo_bit_data bit;
227 struct amdgpu_i2c_bus_rec rec;
228 struct drm_dp_aux aux;
229 bool has_aux;
230 struct mutex mutex;
231};
232
233struct amdgpu_afmt {
234 bool enabled;
235 int offset;
236 bool last_buffer_filled_status;
237 int id;
238 struct amdgpu_audio_pin *pin;
239};
240
241/*
242 * Audio
243 */
244struct amdgpu_audio_pin {
245 int channels;
246 int rate;
247 int bits_per_sample;
248 u8 status_bits;
249 u8 category_code;
250 u32 offset;
251 bool connected;
252 u32 id;
253};
254
255struct amdgpu_audio {
256 bool enabled;
257 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
258 int num_pins;
259};
260
261struct amdgpu_display_funcs {
262 /* display watermarks */
263 void (*bandwidth_update)(struct amdgpu_device *adev);
264 /* get frame count */
265 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
266 /* set backlight level */
267 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
268 u8 level);
269 /* get backlight level */
270 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
271 /* hotplug detect */
272 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
273 void (*hpd_set_polarity)(struct amdgpu_device *adev,
274 enum amdgpu_hpd_id hpd);
275 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
276 /* pageflipping */
277 void (*page_flip)(struct amdgpu_device *adev,
278 int crtc_id, u64 crtc_base, bool async);
279 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
280 u32 *vbl, u32 *position);
281 /* display topology setup */
282 void (*add_encoder)(struct amdgpu_device *adev,
283 uint32_t encoder_enum,
284 uint32_t supported_device,
285 u16 caps);
286 void (*add_connector)(struct amdgpu_device *adev,
287 uint32_t connector_id,
288 uint32_t supported_device,
289 int connector_type,
290 struct amdgpu_i2c_bus_rec *i2c_bus,
291 uint16_t connector_object_id,
292 struct amdgpu_hpd *hpd,
293 struct amdgpu_router *router);
294
295
296};
297
298struct amdgpu_framebuffer {
299 struct drm_framebuffer base;
300
301 uint64_t tiling_flags;
302 bool tmz_surface;
303
304 /* caching for later use */
305 uint64_t address;
306};
307
308struct amdgpu_mode_info {
309 struct atom_context *atom_context;
310 struct card_info *atom_card_info;
311 bool mode_config_initialized;
312 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
313 struct drm_plane *planes[AMDGPU_MAX_PLANES];
314 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
315 /* DVI-I properties */
316 struct drm_property *coherent_mode_property;
317 /* DAC enable load detect */
318 struct drm_property *load_detect_property;
319 /* underscan */
320 struct drm_property *underscan_property;
321 struct drm_property *underscan_hborder_property;
322 struct drm_property *underscan_vborder_property;
323 /* audio */
324 struct drm_property *audio_property;
325 /* FMT dithering */
326 struct drm_property *dither_property;
327 /* Adaptive Backlight Modulation (power feature) */
328 struct drm_property *abm_level_property;
329 /* hardcoded DFP edid from BIOS */
330 struct edid *bios_hardcoded_edid;
331 int bios_hardcoded_edid_size;
332
333 /* firmware flags */
334 u32 firmware_flags;
335 /* pointer to backlight encoder */
336 struct amdgpu_encoder *bl_encoder;
337 u8 bl_level; /* saved backlight level */
338 struct amdgpu_audio audio; /* audio stuff */
339 int num_crtc; /* number of crtcs */
340 int num_hpd; /* number of hpd pins */
341 int num_dig; /* number of dig blocks */
342 bool gpu_vm_support; /* supports display from GTT */
343 int disp_priority;
344 const struct amdgpu_display_funcs *funcs;
345 const enum drm_plane_type *plane_type;
346};
347
348#define AMDGPU_MAX_BL_LEVEL 0xFF
349
350struct amdgpu_backlight_privdata {
351 struct amdgpu_encoder *encoder;
352 uint8_t negative;
353};
354
355struct amdgpu_atom_ss {
356 uint16_t percentage;
357 uint16_t percentage_divider;
358 uint8_t type;
359 uint16_t step;
360 uint8_t delay;
361 uint8_t range;
362 uint8_t refdiv;
363 /* asic_ss */
364 uint16_t rate;
365 uint16_t amount;
366};
367
368struct amdgpu_crtc {
369 struct drm_crtc base;
370 int crtc_id;
371 bool enabled;
372 bool can_tile;
373 uint32_t crtc_offset;
374 struct drm_gem_object *cursor_bo;
375 uint64_t cursor_addr;
376 int cursor_x;
377 int cursor_y;
378 int cursor_hot_x;
379 int cursor_hot_y;
380 int cursor_width;
381 int cursor_height;
382 int max_cursor_width;
383 int max_cursor_height;
384 enum amdgpu_rmx_type rmx_type;
385 u8 h_border;
386 u8 v_border;
387 fixed20_12 vsc;
388 fixed20_12 hsc;
389 struct drm_display_mode native_mode;
390 u32 pll_id;
391 /* page flipping */
392 struct amdgpu_flip_work *pflip_works;
393 enum amdgpu_flip_status pflip_status;
394 int deferred_flip_completion;
395 /* parameters access from DM IRQ handler */
396 struct dm_irq_params dm_irq_params;
397 /* pll sharing */
398 struct amdgpu_atom_ss ss;
399 bool ss_enabled;
400 u32 adjusted_clock;
401 int bpc;
402 u32 pll_reference_div;
403 u32 pll_post_div;
404 u32 pll_flags;
405 struct drm_encoder *encoder;
406 struct drm_connector *connector;
407 /* for dpm */
408 u32 line_time;
409 u32 wm_low;
410 u32 wm_high;
411 u32 lb_vblank_lead_lines;
412 struct drm_display_mode hw_mode;
413 /* for virtual dce */
414 struct hrtimer vblank_timer;
415 enum amdgpu_interrupt_state vsync_timer_enabled;
416
417 int otg_inst;
418 struct drm_pending_vblank_event *event;
419};
420
421struct amdgpu_encoder_atom_dig {
422 bool linkb;
423 /* atom dig */
424 bool coherent_mode;
425 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
426 /* atom lvds/edp */
427 uint32_t lcd_misc;
428 uint16_t panel_pwr_delay;
429 uint32_t lcd_ss_id;
430 /* panel mode */
431 struct drm_display_mode native_mode;
432 struct backlight_device *bl_dev;
433 int dpms_mode;
434 uint8_t backlight_level;
435 int panel_mode;
436 struct amdgpu_afmt *afmt;
437};
438
439struct amdgpu_encoder {
440 struct drm_encoder base;
441 uint32_t encoder_enum;
442 uint32_t encoder_id;
443 uint32_t devices;
444 uint32_t active_device;
445 uint32_t flags;
446 uint32_t pixel_clock;
447 enum amdgpu_rmx_type rmx_type;
448 enum amdgpu_underscan_type underscan_type;
449 uint32_t underscan_hborder;
450 uint32_t underscan_vborder;
451 struct drm_display_mode native_mode;
452 void *enc_priv;
453 int audio_polling_active;
454 bool is_ext_encoder;
455 u16 caps;
456};
457
458struct amdgpu_connector_atom_dig {
459 /* displayport */
460 u8 dpcd[DP_RECEIVER_CAP_SIZE];
461 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
462 u8 dp_sink_type;
463 int dp_clock;
464 int dp_lane_count;
465 bool edp_on;
466};
467
468struct amdgpu_gpio_rec {
469 bool valid;
470 u8 id;
471 u32 reg;
472 u32 mask;
473 u32 shift;
474};
475
476struct amdgpu_hpd {
477 enum amdgpu_hpd_id hpd;
478 u8 plugged_state;
479 struct amdgpu_gpio_rec gpio;
480};
481
482struct amdgpu_router {
483 u32 router_id;
484 struct amdgpu_i2c_bus_rec i2c_info;
485 u8 i2c_addr;
486 /* i2c mux */
487 bool ddc_valid;
488 u8 ddc_mux_type;
489 u8 ddc_mux_control_pin;
490 u8 ddc_mux_state;
491 /* clock/data mux */
492 bool cd_valid;
493 u8 cd_mux_type;
494 u8 cd_mux_control_pin;
495 u8 cd_mux_state;
496};
497
498enum amdgpu_connector_audio {
499 AMDGPU_AUDIO_DISABLE = 0,
500 AMDGPU_AUDIO_ENABLE = 1,
501 AMDGPU_AUDIO_AUTO = 2
502};
503
504enum amdgpu_connector_dither {
505 AMDGPU_FMT_DITHER_DISABLE = 0,
506 AMDGPU_FMT_DITHER_ENABLE = 1,
507};
508
509struct amdgpu_dm_dp_aux {
510 struct drm_dp_aux aux;
511 struct ddc_service *ddc_service;
512};
513
514struct amdgpu_i2c_adapter {
515 struct i2c_adapter base;
516
517 struct ddc_service *ddc_service;
518};
519
520#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
521
522struct amdgpu_connector {
523 struct drm_connector base;
524 uint32_t connector_id;
525 uint32_t devices;
526 struct amdgpu_i2c_chan *ddc_bus;
527 /* some systems have an hdmi and vga port with a shared ddc line */
528 bool shared_ddc;
529 bool use_digital;
530 /* we need to mind the EDID between detect
531 and get modes due to analog/digital/tvencoder */
532 struct edid *edid;
533 void *con_priv;
534 bool dac_load_detect;
535 bool detected_by_load; /* if the connection status was determined by load */
536 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
537 uint16_t connector_object_id;
538 struct amdgpu_hpd hpd;
539 struct amdgpu_router router;
540 struct amdgpu_i2c_chan *router_bus;
541 enum amdgpu_connector_audio audio;
542 enum amdgpu_connector_dither dither;
543 unsigned pixelclock_for_modeset;
544};
545
546/* TODO: start to use this struct and remove same field from base one */
547struct amdgpu_mst_connector {
548 struct amdgpu_connector base;
549
550 struct drm_dp_mst_topology_mgr mst_mgr;
551 struct amdgpu_dm_dp_aux dm_dp_aux;
552 struct drm_dp_mst_port *mst_output_port;
553 struct amdgpu_connector *mst_root;
554 bool is_mst_connector;
555 struct amdgpu_encoder *mst_encoder;
556};
557
558#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
559 ((em) == ATOM_ENCODER_MODE_DP_MST))
560
561/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
562#define DRM_SCANOUTPOS_VALID (1 << 0)
563#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
564#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
565#define USE_REAL_VBLANKSTART (1 << 30)
566#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
567
568void amdgpu_link_encoder_connector(struct drm_device *dev);
569
570struct drm_connector *
571amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
572struct drm_connector *
573amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
574bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
575 u32 pixel_clock);
576
577u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
578struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
579
580bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
581 bool use_aux);
582
583void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
584
585int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
586 unsigned int pipe, unsigned int flags, int *vpos,
587 int *hpos, ktime_t *stime, ktime_t *etime,
588 const struct drm_display_mode *mode);
589
590int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
591
592void amdgpu_enc_destroy(struct drm_encoder *encoder);
593void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
594bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
595 const struct drm_display_mode *mode,
596 struct drm_display_mode *adjusted_mode);
597void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
598 struct drm_display_mode *adjusted_mode);
599int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
600
601bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
602 bool in_vblank_irq, int *vpos,
603 int *hpos, ktime_t *stime, ktime_t *etime,
604 const struct drm_display_mode *mode);
605
606/* amdgpu_display.c */
607void amdgpu_display_print_display_setup(struct drm_device *dev);
608int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
609int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
610 struct drm_modeset_acquire_ctx *ctx);
611int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
612 struct drm_framebuffer *fb,
613 struct drm_pending_vblank_event *event,
614 uint32_t page_flip_flags, uint32_t target,
615 struct drm_modeset_acquire_ctx *ctx);
616extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
617
618#endif
619

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h