1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31
32#define PSP_FENCE_BUFFER_SIZE 0x1000
33#define PSP_CMD_BUFFER_SIZE 0x1000
34#define PSP_ASD_SHARED_MEM_SIZE 0x4000
35#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
36#define PSP_1_MEG 0x100000
37#define PSP_TMR_SIZE 0x400000
38
39struct psp_context;
40struct psp_xgmi_node_info;
41struct psp_xgmi_topology_info;
42
43enum psp_ring_type
44{
45 PSP_RING_TYPE__INVALID = 0,
46 /*
47 * These values map to the way the PSP kernel identifies the
48 * rings.
49 */
50 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
51 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
52};
53
54struct psp_ring
55{
56 enum psp_ring_type ring_type;
57 struct psp_gfx_rb_frame *ring_mem;
58 uint64_t ring_mem_mc_addr;
59 void *ring_mem_handle;
60 uint32_t ring_size;
61};
62
63struct psp_funcs
64{
65 int (*init_microcode)(struct psp_context *psp);
66 int (*bootloader_load_sysdrv)(struct psp_context *psp);
67 int (*bootloader_load_sos)(struct psp_context *psp);
68 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
69 int (*ring_create)(struct psp_context *psp,
70 enum psp_ring_type ring_type);
71 int (*ring_stop)(struct psp_context *psp,
72 enum psp_ring_type ring_type);
73 int (*ring_destroy)(struct psp_context *psp,
74 enum psp_ring_type ring_type);
75 int (*cmd_submit)(struct psp_context *psp,
76 struct amdgpu_firmware_info *ucode,
77 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
78 int index);
79 bool (*compare_sram_data)(struct psp_context *psp,
80 struct amdgpu_firmware_info *ucode,
81 enum AMDGPU_UCODE_ID ucode_type);
82 bool (*smu_reload_quirk)(struct psp_context *psp);
83 int (*mode1_reset)(struct psp_context *psp);
84 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
85 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
86 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
87 struct psp_xgmi_topology_info *topology);
88 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
89 struct psp_xgmi_topology_info *topology);
90 bool (*support_vmr_ring)(struct psp_context *psp);
91};
92
93struct psp_xgmi_context {
94 uint8_t initialized;
95 uint32_t session_id;
96 struct amdgpu_bo *xgmi_shared_bo;
97 uint64_t xgmi_shared_mc_addr;
98 void *xgmi_shared_buf;
99};
100
101struct psp_context
102{
103 struct amdgpu_device *adev;
104 struct psp_ring km_ring;
105 struct psp_gfx_cmd_resp *cmd;
106
107 const struct psp_funcs *funcs;
108
109 /* firmware buffer */
110 struct amdgpu_bo *fw_pri_bo;
111 uint64_t fw_pri_mc_addr;
112 void *fw_pri_buf;
113
114 /* sos firmware */
115 const struct firmware *sos_fw;
116 uint32_t sos_fw_version;
117 uint32_t sos_feature_version;
118 uint32_t sys_bin_size;
119 uint32_t sos_bin_size;
120 uint8_t *sys_start_addr;
121 uint8_t *sos_start_addr;
122
123 /* tmr buffer */
124 struct amdgpu_bo *tmr_bo;
125 uint64_t tmr_mc_addr;
126 void *tmr_buf;
127
128 /* asd firmware and buffer */
129 const struct firmware *asd_fw;
130 uint32_t asd_fw_version;
131 uint32_t asd_feature_version;
132 uint32_t asd_ucode_size;
133 uint8_t *asd_start_addr;
134 struct amdgpu_bo *asd_shared_bo;
135 uint64_t asd_shared_mc_addr;
136 void *asd_shared_buf;
137
138 /* fence buffer */
139 struct amdgpu_bo *fence_buf_bo;
140 uint64_t fence_buf_mc_addr;
141 void *fence_buf;
142
143 /* cmd buffer */
144 struct amdgpu_bo *cmd_buf_bo;
145 uint64_t cmd_buf_mc_addr;
146 struct psp_gfx_cmd_resp *cmd_buf_mem;
147
148 /* fence value associated with cmd buffer */
149 atomic_t fence_value;
150
151 /* xgmi ta firmware and buffer */
152 const struct firmware *ta_fw;
153 uint32_t ta_xgmi_ucode_version;
154 uint32_t ta_xgmi_ucode_size;
155 uint8_t *ta_xgmi_start_addr;
156 struct psp_xgmi_context xgmi_context;
157};
158
159struct amdgpu_psp_funcs {
160 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
161 enum AMDGPU_UCODE_ID);
162};
163
164#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
165struct psp_xgmi_node_info {
166 uint64_t node_id;
167 uint8_t num_hops;
168 uint8_t is_sharing_enabled;
169 enum ta_xgmi_assigned_sdma_engine sdma_engine;
170};
171
172struct psp_xgmi_topology_info {
173 uint32_t num_nodes;
174 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
175};
176
177#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
178#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
179#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
180#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
181#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
182 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
183#define psp_compare_sram_data(psp, ucode, type) \
184 (psp)->funcs->compare_sram_data((psp), (ucode), (type))
185#define psp_init_microcode(psp) \
186 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
187#define psp_bootloader_load_sysdrv(psp) \
188 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
189#define psp_bootloader_load_sos(psp) \
190 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
191#define psp_smu_reload_quirk(psp) \
192 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
193#define psp_support_vmr_ring(psp) \
194 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
195#define psp_mode1_reset(psp) \
196 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
197#define psp_xgmi_get_node_id(psp, node_id) \
198 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
199#define psp_xgmi_get_hive_id(psp, hive_id) \
200 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
201#define psp_xgmi_get_topology_info(psp, num_device, topology) \
202 ((psp)->funcs->xgmi_get_topology_info ? \
203 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
204#define psp_xgmi_set_topology_info(psp, num_device, topology) \
205 ((psp)->funcs->xgmi_set_topology_info ? \
206 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
207
208#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
209
210extern const struct amd_ip_funcs psp_ip_funcs;
211
212extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
213extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
214 uint32_t field_val, uint32_t mask, bool check_changed);
215
216extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
217
218int psp_gpu_reset(struct amdgpu_device *adev);
219int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
220extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
221
222#endif
223