1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian K├Ânig
23 */
24#ifndef __AMDGPU_VM_H__
25#define __AMDGPU_VM_H__
26
27#include <linux/idr.h>
28#include <linux/kfifo.h>
29#include <linux/rbtree.h>
30#include <drm/gpu_scheduler.h>
31#include <drm/drm_file.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <linux/chash.h>
34
35#include "amdgpu_sync.h"
36#include "amdgpu_ring.h"
37#include "amdgpu_ids.h"
38
39struct amdgpu_bo_va;
40struct amdgpu_job;
41struct amdgpu_bo_list_entry;
42
43/*
44 * GPUVM handling
45 */
46
47/* Maximum number of PTEs the hardware can write with one command */
48#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
49
50/* number of entries in page table */
51#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
52
53#define AMDGPU_PTE_VALID (1ULL << 0)
54#define AMDGPU_PTE_SYSTEM (1ULL << 1)
55#define AMDGPU_PTE_SNOOPED (1ULL << 2)
56
57/* VI only */
58#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
59
60#define AMDGPU_PTE_READABLE (1ULL << 5)
61#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
62
63#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
64
65/* TILED for VEGA10, reserved for older ASICs */
66#define AMDGPU_PTE_PRT (1ULL << 51)
67
68/* PDE is handled as PTE for VEGA10 */
69#define AMDGPU_PDE_PTE (1ULL << 54)
70
71/* PTE is handled as PDE for VEGA10 (Translate Further) */
72#define AMDGPU_PTE_TF (1ULL << 56)
73
74/* PDE Block Fragment Size for VEGA10 */
75#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
76
77
78/* For GFX9 */
79#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
80#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
81
82#define AMDGPU_MTYPE_NC 0
83#define AMDGPU_MTYPE_CC 2
84
85#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
86 | AMDGPU_PTE_SNOOPED \
87 | AMDGPU_PTE_EXECUTABLE \
88 | AMDGPU_PTE_READABLE \
89 | AMDGPU_PTE_WRITEABLE \
90 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
91
92/* How to programm VM fault handling */
93#define AMDGPU_VM_FAULT_STOP_NEVER 0
94#define AMDGPU_VM_FAULT_STOP_FIRST 1
95#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
96
97/* max number of VMHUB */
98#define AMDGPU_MAX_VMHUBS 2
99#define AMDGPU_GFXHUB 0
100#define AMDGPU_MMHUB 1
101
102/* hardcode that limit for now */
103#define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
104
105/* max vmids dedicated for process */
106#define AMDGPU_VM_MAX_RESERVED_VMID 1
107
108#define AMDGPU_VM_CONTEXT_GFX 0
109#define AMDGPU_VM_CONTEXT_COMPUTE 1
110
111/* See vm_update_mode */
112#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
113#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
114
115/* VMPT level enumerate, and the hiberachy is:
116 * PDB2->PDB1->PDB0->PTB
117 */
118enum amdgpu_vm_level {
119 AMDGPU_VM_PDB2,
120 AMDGPU_VM_PDB1,
121 AMDGPU_VM_PDB0,
122 AMDGPU_VM_PTB
123};
124
125/* base structure for tracking BO usage in a VM */
126struct amdgpu_vm_bo_base {
127 /* constant after initialization */
128 struct amdgpu_vm *vm;
129 struct amdgpu_bo *bo;
130
131 /* protected by bo being reserved */
132 struct amdgpu_vm_bo_base *next;
133
134 /* protected by spinlock */
135 struct list_head vm_status;
136
137 /* protected by the BO being reserved */
138 bool moved;
139};
140
141struct amdgpu_vm_pt {
142 struct amdgpu_vm_bo_base base;
143 bool huge;
144
145 /* array of page tables, one for each directory entry */
146 struct amdgpu_vm_pt *entries;
147};
148
149/* provided by hw blocks that can write ptes, e.g., sdma */
150struct amdgpu_vm_pte_funcs {
151 /* number of dw to reserve per operation */
152 unsigned copy_pte_num_dw;
153
154 /* copy pte entries from GART */
155 void (*copy_pte)(struct amdgpu_ib *ib,
156 uint64_t pe, uint64_t src,
157 unsigned count);
158
159 /* write pte one entry at a time with addr mapping */
160 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
161 uint64_t value, unsigned count,
162 uint32_t incr);
163 /* for linear pte/pde updates without addr mapping */
164 void (*set_pte_pde)(struct amdgpu_ib *ib,
165 uint64_t pe,
166 uint64_t addr, unsigned count,
167 uint32_t incr, uint64_t flags);
168};
169
170#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
171#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
172#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
173
174
175struct amdgpu_task_info {
176 char process_name[TASK_COMM_LEN];
177 char task_name[TASK_COMM_LEN];
178 pid_t pid;
179 pid_t tgid;
180};
181
182#define AMDGPU_PAGEFAULT_HASH_BITS 8
183struct amdgpu_retryfault_hashtable {
184 DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
185 spinlock_t lock;
186 int count;
187};
188
189struct amdgpu_vm {
190 /* tree of virtual addresses mapped */
191 struct rb_root_cached va;
192
193 /* BOs who needs a validation */
194 struct list_head evicted;
195
196 /* PT BOs which relocated and their parent need an update */
197 struct list_head relocated;
198
199 /* per VM BOs moved, but not yet updated in the PT */
200 struct list_head moved;
201
202 /* All BOs of this VM not currently in the state machine */
203 struct list_head idle;
204
205 /* regular invalidated BOs, but not yet updated in the PT */
206 struct list_head invalidated;
207 spinlock_t invalidated_lock;
208
209 /* BO mappings freed, but not yet updated in the PT */
210 struct list_head freed;
211
212 /* contains the page directory */
213 struct amdgpu_vm_pt root;
214 struct dma_fence *last_update;
215
216 /* Scheduler entity for page table updates */
217 struct drm_sched_entity entity;
218
219 unsigned int pasid;
220 /* dedicated to vm */
221 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
222
223 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
224 bool use_cpu_for_update;
225
226 /* Flag to indicate ATS support from PTE for GFX9 */
227 bool pte_support_ats;
228
229 /* Up to 128 pending retry page faults */
230 DECLARE_KFIFO(faults, u64, 128);
231
232 /* Points to the KFD process VM info */
233 struct amdkfd_process_info *process_info;
234
235 /* List node in amdkfd_process_info.vm_list_head */
236 struct list_head vm_list_node;
237
238 /* Valid while the PD is reserved or fenced */
239 uint64_t pd_phys_addr;
240
241 /* Some basic info about the task */
242 struct amdgpu_task_info task_info;
243
244 /* Store positions of group of BOs */
245 struct ttm_lru_bulk_move lru_bulk_move;
246 /* mark whether can do the bulk move */
247 bool bulk_moveable;
248 struct amdgpu_retryfault_hashtable *fault_hash;
249};
250
251struct amdgpu_vm_manager {
252 /* Handling of VMIDs */
253 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
254
255 /* Handling of VM fences */
256 u64 fence_context;
257 unsigned seqno[AMDGPU_MAX_RINGS];
258
259 uint64_t max_pfn;
260 uint32_t num_level;
261 uint32_t block_size;
262 uint32_t fragment_size;
263 enum amdgpu_vm_level root_level;
264 /* vram base address for page table entry */
265 u64 vram_base_offset;
266 /* vm pte handling */
267 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
268 struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
269 unsigned vm_pte_num_rqs;
270
271 /* partial resident texture handling */
272 spinlock_t prt_lock;
273 atomic_t num_prt_users;
274
275 /* controls how VM page tables are updated for Graphics and Compute.
276 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
277 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
278 */
279 int vm_update_mode;
280
281 /* PASID to VM mapping, will be used in interrupt context to
282 * look up VM of a page fault
283 */
284 struct idr pasid_idr;
285 spinlock_t pasid_lock;
286};
287
288#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
289#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
290#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
291
292void amdgpu_vm_manager_init(struct amdgpu_device *adev);
293void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
294int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
295 int vm_context, unsigned int pasid);
296int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
297void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
298void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
299void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
300 struct list_head *validated,
301 struct amdgpu_bo_list_entry *entry);
302bool amdgpu_vm_ready(struct amdgpu_vm *vm);
303int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
304 int (*callback)(void *p, struct amdgpu_bo *bo),
305 void *param);
306int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
307 struct amdgpu_vm *vm,
308 uint64_t saddr, uint64_t size);
309int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
310int amdgpu_vm_update_directories(struct amdgpu_device *adev,
311 struct amdgpu_vm *vm);
312int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
313 struct amdgpu_vm *vm,
314 struct dma_fence **fence);
315int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
316 struct amdgpu_vm *vm);
317int amdgpu_vm_bo_update(struct amdgpu_device *adev,
318 struct amdgpu_bo_va *bo_va,
319 bool clear);
320void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
321 struct amdgpu_bo *bo, bool evicted);
322struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
323 struct amdgpu_bo *bo);
324struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
325 struct amdgpu_vm *vm,
326 struct amdgpu_bo *bo);
327int amdgpu_vm_bo_map(struct amdgpu_device *adev,
328 struct amdgpu_bo_va *bo_va,
329 uint64_t addr, uint64_t offset,
330 uint64_t size, uint64_t flags);
331int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
332 struct amdgpu_bo_va *bo_va,
333 uint64_t addr, uint64_t offset,
334 uint64_t size, uint64_t flags);
335int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
336 struct amdgpu_bo_va *bo_va,
337 uint64_t addr);
338int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
339 struct amdgpu_vm *vm,
340 uint64_t saddr, uint64_t size);
341struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
342 uint64_t addr);
343void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
344void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
345 struct amdgpu_bo_va *bo_va);
346void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
347 uint32_t fragment_size_default, unsigned max_level,
348 unsigned max_bits);
349int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
350bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
351 struct amdgpu_job *job);
352void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
353
354void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
355 struct amdgpu_task_info *task_info);
356
357void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
358
359void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
360 struct amdgpu_vm *vm);
361
362int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
363
364void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
365
366void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
367
368#endif
369