1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "cikd.h"
27
28#include "bif/bif_4_1_d.h"
29#include "bif/bif_4_1_sh_mask.h"
30
31#include "oss/oss_2_0_d.h"
32#include "oss/oss_2_0_sh_mask.h"
33
34/*
35 * Interrupts
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
47 */
48
49static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
50
51/**
52 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
53 *
54 * @adev: amdgpu_device pointer
55 *
56 * Enable the interrupt ring buffer (CIK).
57 */
58static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
59{
60 u32 ih_cntl = RREG32(mmIH_CNTL);
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
62
63 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
64 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
65 WREG32(mmIH_CNTL, ih_cntl);
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67 adev->irq.ih.enabled = true;
68}
69
70/**
71 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
72 *
73 * @adev: amdgpu_device pointer
74 *
75 * Disable the interrupt ring buffer (CIK).
76 */
77static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
78{
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80 u32 ih_cntl = RREG32(mmIH_CNTL);
81
82 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
83 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
84 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85 WREG32(mmIH_CNTL, ih_cntl);
86 /* set rptr, wptr to 0 */
87 WREG32(mmIH_RB_RPTR, 0);
88 WREG32(mmIH_RB_WPTR, 0);
89 adev->irq.ih.enabled = false;
90 adev->irq.ih.rptr = 0;
91}
92
93/**
94 * cik_ih_irq_init - init and enable the interrupt ring
95 *
96 * @adev: amdgpu_device pointer
97 *
98 * Allocate a ring buffer for the interrupt controller,
99 * enable the RLC, disable interrupts, enable the IH
100 * ring buffer and enable it (CIK).
101 * Called at device load and reume.
102 * Returns 0 for success, errors for failure.
103 */
104static int cik_ih_irq_init(struct amdgpu_device *adev)
105{
106 struct amdgpu_ih_ring *ih = &adev->irq.ih;
107 int rb_bufsz;
108 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
109
110 /* disable irqs */
111 cik_ih_disable_interrupts(adev);
112
113 /* setup interrupt control */
114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
118 */
119 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
121 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
122 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
123
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
126
127 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
128 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
129 (rb_bufsz << 1));
130
131 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
132
133 /* set the writeback address whether it's enabled or not */
134 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
135 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
136
137 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
138
139 /* set rptr, wptr to 0 */
140 WREG32(mmIH_RB_RPTR, 0);
141 WREG32(mmIH_RB_WPTR, 0);
142
143 /* Default settings for IH_CNTL (disabled at first) */
144 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
145 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
146 (0 << IH_CNTL__MC_VMID__SHIFT);
147 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
148 if (adev->irq.msi_enabled)
149 ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
150 WREG32(mmIH_CNTL, ih_cntl);
151
152 pci_set_master(adev->pdev);
153
154 /* enable irqs */
155 cik_ih_enable_interrupts(adev);
156
157 return 0;
158}
159
160/**
161 * cik_ih_irq_disable - disable interrupts
162 *
163 * @adev: amdgpu_device pointer
164 *
165 * Disable interrupts on the hw (CIK).
166 */
167static void cik_ih_irq_disable(struct amdgpu_device *adev)
168{
169 cik_ih_disable_interrupts(adev);
170 /* Wait and acknowledge irq */
171 mdelay(1);
172}
173
174/**
175 * cik_ih_get_wptr - get the IH ring buffer wptr
176 *
177 * @adev: amdgpu_device pointer
178 *
179 * Get the IH ring buffer wptr from either the register
180 * or the writeback memory buffer (CIK). Also check for
181 * ring buffer overflow and deal with it.
182 * Used by cik_irq_process().
183 * Returns the value of the wptr.
184 */
185static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
186 struct amdgpu_ih_ring *ih)
187{
188 u32 wptr, tmp;
189
190 wptr = le32_to_cpu(*ih->wptr_cpu);
191
192 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
193 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
194 /* When a ring buffer overflow happen start parsing interrupt
195 * from the last not overwritten vector (wptr + 16). Hopefully
196 * this should allow us to catchup.
197 */
198 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
199 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
200 ih->rptr = (wptr + 16) & ih->ptr_mask;
201 tmp = RREG32(mmIH_RB_CNTL);
202 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
203 WREG32(mmIH_RB_CNTL, tmp);
204 }
205 return (wptr & ih->ptr_mask);
206}
207
208/* CIK IV Ring
209 * Each IV ring entry is 128 bits:
210 * [7:0] - interrupt source id
211 * [31:8] - reserved
212 * [59:32] - interrupt source data
213 * [63:60] - reserved
214 * [71:64] - RINGID
215 * CP:
216 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
217 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
218 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
219 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
220 * PIPE_ID - ME0 0=3D
221 * - ME1&2 compute dispatcher (4 pipes each)
222 * SDMA:
223 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
224 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
225 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
226 * [79:72] - VMID
227 * [95:80] - PASID
228 * [127:96] - reserved
229 */
230
231 /**
232 * cik_ih_decode_iv - decode an interrupt vector
233 *
234 * @adev: amdgpu_device pointer
235 *
236 * Decodes the interrupt vector at the current rptr
237 * position and also advance the position.
238 */
239static void cik_ih_decode_iv(struct amdgpu_device *adev,
240 struct amdgpu_ih_ring *ih,
241 struct amdgpu_iv_entry *entry)
242{
243 /* wptr/rptr are in bytes! */
244 u32 ring_index = ih->rptr >> 2;
245 uint32_t dw[4];
246
247 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
248 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
249 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
250 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
251
252 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
253 entry->src_id = dw[0] & 0xff;
254 entry->src_data[0] = dw[1] & 0xfffffff;
255 entry->ring_id = dw[2] & 0xff;
256 entry->vmid = (dw[2] >> 8) & 0xff;
257 entry->pasid = (dw[2] >> 16) & 0xffff;
258
259 /* wptr/rptr are in bytes! */
260 ih->rptr += 16;
261}
262
263/**
264 * cik_ih_set_rptr - set the IH ring buffer rptr
265 *
266 * @adev: amdgpu_device pointer
267 *
268 * Set the IH ring buffer rptr.
269 */
270static void cik_ih_set_rptr(struct amdgpu_device *adev,
271 struct amdgpu_ih_ring *ih)
272{
273 WREG32(mmIH_RB_RPTR, ih->rptr);
274}
275
276static int cik_ih_early_init(void *handle)
277{
278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
279 int ret;
280
281 ret = amdgpu_irq_add_domain(adev);
282 if (ret)
283 return ret;
284
285 cik_ih_set_interrupt_funcs(adev);
286
287 return 0;
288}
289
290static int cik_ih_sw_init(void *handle)
291{
292 int r;
293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
294
295 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
296 if (r)
297 return r;
298
299 r = amdgpu_irq_init(adev);
300
301 return r;
302}
303
304static int cik_ih_sw_fini(void *handle)
305{
306 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
307
308 amdgpu_irq_fini(adev);
309 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
310 amdgpu_irq_remove_domain(adev);
311
312 return 0;
313}
314
315static int cik_ih_hw_init(void *handle)
316{
317 int r;
318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
319
320 r = cik_ih_irq_init(adev);
321 if (r)
322 return r;
323
324 return 0;
325}
326
327static int cik_ih_hw_fini(void *handle)
328{
329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
330
331 cik_ih_irq_disable(adev);
332
333 return 0;
334}
335
336static int cik_ih_suspend(void *handle)
337{
338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
339
340 return cik_ih_hw_fini(adev);
341}
342
343static int cik_ih_resume(void *handle)
344{
345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
346
347 return cik_ih_hw_init(adev);
348}
349
350static bool cik_ih_is_idle(void *handle)
351{
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353 u32 tmp = RREG32(mmSRBM_STATUS);
354
355 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
356 return false;
357
358 return true;
359}
360
361static int cik_ih_wait_for_idle(void *handle)
362{
363 unsigned i;
364 u32 tmp;
365 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
366
367 for (i = 0; i < adev->usec_timeout; i++) {
368 /* read MC_STATUS */
369 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
370 if (!tmp)
371 return 0;
372 udelay(1);
373 }
374 return -ETIMEDOUT;
375}
376
377static int cik_ih_soft_reset(void *handle)
378{
379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
380
381 u32 srbm_soft_reset = 0;
382 u32 tmp = RREG32(mmSRBM_STATUS);
383
384 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
385 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
386
387 if (srbm_soft_reset) {
388 tmp = RREG32(mmSRBM_SOFT_RESET);
389 tmp |= srbm_soft_reset;
390 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
391 WREG32(mmSRBM_SOFT_RESET, tmp);
392 tmp = RREG32(mmSRBM_SOFT_RESET);
393
394 udelay(50);
395
396 tmp &= ~srbm_soft_reset;
397 WREG32(mmSRBM_SOFT_RESET, tmp);
398 tmp = RREG32(mmSRBM_SOFT_RESET);
399
400 /* Wait a little for things to settle down */
401 udelay(50);
402 }
403
404 return 0;
405}
406
407static int cik_ih_set_clockgating_state(void *handle,
408 enum amd_clockgating_state state)
409{
410 return 0;
411}
412
413static int cik_ih_set_powergating_state(void *handle,
414 enum amd_powergating_state state)
415{
416 return 0;
417}
418
419static const struct amd_ip_funcs cik_ih_ip_funcs = {
420 .name = "cik_ih",
421 .early_init = cik_ih_early_init,
422 .late_init = NULL,
423 .sw_init = cik_ih_sw_init,
424 .sw_fini = cik_ih_sw_fini,
425 .hw_init = cik_ih_hw_init,
426 .hw_fini = cik_ih_hw_fini,
427 .suspend = cik_ih_suspend,
428 .resume = cik_ih_resume,
429 .is_idle = cik_ih_is_idle,
430 .wait_for_idle = cik_ih_wait_for_idle,
431 .soft_reset = cik_ih_soft_reset,
432 .set_clockgating_state = cik_ih_set_clockgating_state,
433 .set_powergating_state = cik_ih_set_powergating_state,
434};
435
436static const struct amdgpu_ih_funcs cik_ih_funcs = {
437 .get_wptr = cik_ih_get_wptr,
438 .decode_iv = cik_ih_decode_iv,
439 .set_rptr = cik_ih_set_rptr
440};
441
442static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
443{
444 adev->irq.ih_funcs = &cik_ih_funcs;
445}
446
447const struct amdgpu_ip_block_version cik_ih_ip_block =
448{
449 .type = AMD_IP_BLOCK_TYPE_IH,
450 .major = 2,
451 .minor = 0,
452 .rev = 0,
453 .funcs = &cik_ih_ip_funcs,
454};
455