1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/firmware.h> |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> |
27 | |
28 | #include <drm/drm_cache.h> |
29 | #include "amdgpu.h" |
30 | #include "gmc_v6_0.h" |
31 | #include "amdgpu_ucode.h" |
32 | #include "amdgpu_gem.h" |
33 | |
34 | #include "bif/bif_3_0_d.h" |
35 | #include "bif/bif_3_0_sh_mask.h" |
36 | #include "oss/oss_1_0_d.h" |
37 | #include "oss/oss_1_0_sh_mask.h" |
38 | #include "gmc/gmc_6_0_d.h" |
39 | #include "gmc/gmc_6_0_sh_mask.h" |
40 | #include "dce/dce_6_0_d.h" |
41 | #include "dce/dce_6_0_sh_mask.h" |
42 | #include "si_enums.h" |
43 | |
44 | static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); |
45 | static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); |
46 | static int gmc_v6_0_wait_for_idle(void *handle); |
47 | |
48 | MODULE_FIRMWARE("amdgpu/tahiti_mc.bin" ); |
49 | MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin" ); |
50 | MODULE_FIRMWARE("amdgpu/verde_mc.bin" ); |
51 | MODULE_FIRMWARE("amdgpu/oland_mc.bin" ); |
52 | MODULE_FIRMWARE("amdgpu/hainan_mc.bin" ); |
53 | MODULE_FIRMWARE("amdgpu/si58_mc.bin" ); |
54 | |
55 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000 |
56 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 |
57 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000 |
58 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 |
59 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 |
60 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 |
61 | #define MC_SEQ_MISC0__MT__HBM 0x60000000 |
62 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 |
63 | |
64 | static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) |
65 | { |
66 | u32 blackout; |
67 | |
68 | gmc_v6_0_wait_for_idle(handle: (void *)adev); |
69 | |
70 | blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
71 | if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { |
72 | /* Block CPU access */ |
73 | WREG32(mmBIF_FB_EN, 0); |
74 | /* blackout the MC */ |
75 | blackout = REG_SET_FIELD(blackout, |
76 | MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); |
77 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); |
78 | } |
79 | /* wait for the MC to settle */ |
80 | udelay(100); |
81 | |
82 | } |
83 | |
84 | static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) |
85 | { |
86 | u32 tmp; |
87 | |
88 | /* unblackout the MC */ |
89 | tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
90 | tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); |
91 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); |
92 | /* allow CPU access */ |
93 | tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); |
94 | tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); |
95 | WREG32(mmBIF_FB_EN, tmp); |
96 | } |
97 | |
98 | static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) |
99 | { |
100 | const char *chip_name; |
101 | char fw_name[30]; |
102 | int err; |
103 | bool is_58_fw = false; |
104 | |
105 | DRM_DEBUG("\n" ); |
106 | |
107 | switch (adev->asic_type) { |
108 | case CHIP_TAHITI: |
109 | chip_name = "tahiti" ; |
110 | break; |
111 | case CHIP_PITCAIRN: |
112 | chip_name = "pitcairn" ; |
113 | break; |
114 | case CHIP_VERDE: |
115 | chip_name = "verde" ; |
116 | break; |
117 | case CHIP_OLAND: |
118 | chip_name = "oland" ; |
119 | break; |
120 | case CHIP_HAINAN: |
121 | chip_name = "hainan" ; |
122 | break; |
123 | default: |
124 | BUG(); |
125 | } |
126 | |
127 | /* this memory configuration requires special firmware */ |
128 | if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) |
129 | is_58_fw = true; |
130 | |
131 | if (is_58_fw) |
132 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/si58_mc.bin" ); |
133 | else |
134 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_mc.bin" , chip_name); |
135 | err = amdgpu_ucode_request(adev, fw: &adev->gmc.fw, fw_name); |
136 | if (err) { |
137 | dev_err(adev->dev, |
138 | "si_mc: Failed to load firmware \"%s\"\n" , |
139 | fw_name); |
140 | amdgpu_ucode_release(fw: &adev->gmc.fw); |
141 | } |
142 | return err; |
143 | } |
144 | |
145 | static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) |
146 | { |
147 | const __le32 *new_fw_data = NULL; |
148 | u32 running; |
149 | const __le32 *new_io_mc_regs = NULL; |
150 | int i, regs_size, ucode_size; |
151 | const struct mc_firmware_header_v1_0 *hdr; |
152 | |
153 | if (!adev->gmc.fw) |
154 | return -EINVAL; |
155 | |
156 | hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; |
157 | |
158 | amdgpu_ucode_print_mc_hdr(hdr: &hdr->header); |
159 | |
160 | adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); |
161 | regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); |
162 | new_io_mc_regs = (const __le32 *) |
163 | (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); |
164 | ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
165 | new_fw_data = (const __le32 *) |
166 | (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
167 | |
168 | running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; |
169 | |
170 | if (running == 0) { |
171 | |
172 | /* reset the engine and set to writable */ |
173 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
174 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); |
175 | |
176 | /* load mc io regs */ |
177 | for (i = 0; i < regs_size; i++) { |
178 | WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); |
179 | WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); |
180 | } |
181 | /* load the MC ucode */ |
182 | for (i = 0; i < ucode_size; i++) |
183 | WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); |
184 | |
185 | /* put the engine back into the active state */ |
186 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
187 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); |
188 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); |
189 | |
190 | /* wait for training to complete */ |
191 | for (i = 0; i < adev->usec_timeout; i++) { |
192 | if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) |
193 | break; |
194 | udelay(1); |
195 | } |
196 | for (i = 0; i < adev->usec_timeout; i++) { |
197 | if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) |
198 | break; |
199 | udelay(1); |
200 | } |
201 | |
202 | } |
203 | |
204 | return 0; |
205 | } |
206 | |
207 | static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, |
208 | struct amdgpu_gmc *mc) |
209 | { |
210 | u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; |
211 | |
212 | base <<= 24; |
213 | |
214 | amdgpu_gmc_vram_location(adev, mc, base); |
215 | amdgpu_gmc_gart_location(adev, mc, gart_placement: AMDGPU_GART_PLACEMENT_BEST_FIT); |
216 | } |
217 | |
218 | static void gmc_v6_0_mc_program(struct amdgpu_device *adev) |
219 | { |
220 | int i, j; |
221 | |
222 | /* Initialize HDP */ |
223 | for (i = 0, j = 0; i < 32; i++, j += 0x6) { |
224 | WREG32((0xb05 + j), 0x00000000); |
225 | WREG32((0xb06 + j), 0x00000000); |
226 | WREG32((0xb07 + j), 0x00000000); |
227 | WREG32((0xb08 + j), 0x00000000); |
228 | WREG32((0xb09 + j), 0x00000000); |
229 | } |
230 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); |
231 | |
232 | if (gmc_v6_0_wait_for_idle(handle: (void *)adev)) |
233 | dev_warn(adev->dev, "Wait for MC idle timedout !\n" ); |
234 | |
235 | if (adev->mode_info.num_crtc) { |
236 | u32 tmp; |
237 | |
238 | /* Lockout access through VGA aperture*/ |
239 | tmp = RREG32(mmVGA_HDP_CONTROL); |
240 | tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; |
241 | WREG32(mmVGA_HDP_CONTROL, tmp); |
242 | |
243 | /* disable VGA render */ |
244 | tmp = RREG32(mmVGA_RENDER_CONTROL); |
245 | tmp &= ~VGA_VSTATUS_CNTL; |
246 | WREG32(mmVGA_RENDER_CONTROL, tmp); |
247 | } |
248 | /* Update configuration */ |
249 | WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
250 | adev->gmc.vram_start >> 12); |
251 | WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
252 | adev->gmc.vram_end >> 12); |
253 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, |
254 | adev->mem_scratch.gpu_addr >> 12); |
255 | WREG32(mmMC_VM_AGP_BASE, 0); |
256 | WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); |
257 | WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); |
258 | |
259 | if (gmc_v6_0_wait_for_idle(handle: (void *)adev)) |
260 | dev_warn(adev->dev, "Wait for MC idle timedout !\n" ); |
261 | } |
262 | |
263 | static int gmc_v6_0_mc_init(struct amdgpu_device *adev) |
264 | { |
265 | |
266 | u32 tmp; |
267 | int chansize, numchan; |
268 | int r; |
269 | |
270 | tmp = RREG32(mmMC_ARB_RAMCFG); |
271 | if (tmp & (1 << 11)) |
272 | chansize = 16; |
273 | else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) |
274 | chansize = 64; |
275 | else |
276 | chansize = 32; |
277 | |
278 | tmp = RREG32(mmMC_SHARED_CHMAP); |
279 | switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { |
280 | case 0: |
281 | default: |
282 | numchan = 1; |
283 | break; |
284 | case 1: |
285 | numchan = 2; |
286 | break; |
287 | case 2: |
288 | numchan = 4; |
289 | break; |
290 | case 3: |
291 | numchan = 8; |
292 | break; |
293 | case 4: |
294 | numchan = 3; |
295 | break; |
296 | case 5: |
297 | numchan = 6; |
298 | break; |
299 | case 6: |
300 | numchan = 10; |
301 | break; |
302 | case 7: |
303 | numchan = 12; |
304 | break; |
305 | case 8: |
306 | numchan = 16; |
307 | break; |
308 | } |
309 | adev->gmc.vram_width = numchan * chansize; |
310 | /* size in MB on si */ |
311 | adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
312 | adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
313 | |
314 | if (!(adev->flags & AMD_IS_APU)) { |
315 | r = amdgpu_device_resize_fb_bar(adev); |
316 | if (r) |
317 | return r; |
318 | } |
319 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
320 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); |
321 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
322 | |
323 | /* set the gart size */ |
324 | if (amdgpu_gart_size == -1) { |
325 | switch (adev->asic_type) { |
326 | case CHIP_HAINAN: /* no MM engines */ |
327 | default: |
328 | adev->gmc.gart_size = 256ULL << 20; |
329 | break; |
330 | case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ |
331 | case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ |
332 | case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ |
333 | case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ |
334 | adev->gmc.gart_size = 1024ULL << 20; |
335 | break; |
336 | } |
337 | } else { |
338 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
339 | } |
340 | |
341 | adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; |
342 | gmc_v6_0_vram_gtt_location(adev, mc: &adev->gmc); |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
348 | uint32_t vmhub, uint32_t flush_type) |
349 | { |
350 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); |
351 | } |
352 | |
353 | static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
354 | unsigned int vmid, uint64_t pd_addr) |
355 | { |
356 | uint32_t reg; |
357 | |
358 | /* write new base address */ |
359 | if (vmid < 8) |
360 | reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; |
361 | else |
362 | reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); |
363 | amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); |
364 | |
365 | /* bits 0-15 are the VM contexts0-15 */ |
366 | amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); |
367 | |
368 | return pd_addr; |
369 | } |
370 | |
371 | static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, |
372 | uint64_t *addr, uint64_t *flags) |
373 | { |
374 | BUG_ON(*addr & 0xFFFFFF0000000FFFULL); |
375 | } |
376 | |
377 | static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev, |
378 | struct amdgpu_bo_va_mapping *mapping, |
379 | uint64_t *flags) |
380 | { |
381 | *flags &= ~AMDGPU_PTE_EXECUTABLE; |
382 | *flags &= ~AMDGPU_PTE_PRT; |
383 | } |
384 | |
385 | static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, |
386 | bool value) |
387 | { |
388 | u32 tmp; |
389 | |
390 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
391 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
392 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
393 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
394 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
395 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
396 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
397 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
398 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
399 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
400 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
401 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
402 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
403 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
404 | } |
405 | |
406 | /** |
407 | * gmc_v8_0_set_prt() - set PRT VM fault |
408 | * |
409 | * @adev: amdgpu_device pointer |
410 | * @enable: enable/disable VM fault handling for PRT |
411 | */ |
412 | static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) |
413 | { |
414 | u32 tmp; |
415 | |
416 | if (enable && !adev->gmc.prt_warning) { |
417 | dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n" ); |
418 | adev->gmc.prt_warning = true; |
419 | } |
420 | |
421 | tmp = RREG32(mmVM_PRT_CNTL); |
422 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, |
423 | CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, |
424 | enable); |
425 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, |
426 | TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, |
427 | enable); |
428 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, |
429 | L2_CACHE_STORE_INVALID_ENTRIES, |
430 | enable); |
431 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, |
432 | L1_TLB_STORE_INVALID_ENTRIES, |
433 | enable); |
434 | WREG32(mmVM_PRT_CNTL, tmp); |
435 | |
436 | if (enable) { |
437 | uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; |
438 | uint32_t high = adev->vm_manager.max_pfn - |
439 | (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); |
440 | |
441 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); |
442 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); |
443 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); |
444 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); |
445 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); |
446 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); |
447 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); |
448 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); |
449 | } else { |
450 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); |
451 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); |
452 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); |
453 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); |
454 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); |
455 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); |
456 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); |
457 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); |
458 | } |
459 | } |
460 | |
461 | static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) |
462 | { |
463 | uint64_t table_addr; |
464 | u32 field; |
465 | int i; |
466 | |
467 | if (adev->gart.bo == NULL) { |
468 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n" ); |
469 | return -EINVAL; |
470 | } |
471 | amdgpu_gtt_mgr_recover(mgr: &adev->mman.gtt_mgr); |
472 | |
473 | table_addr = amdgpu_bo_gpu_offset(bo: adev->gart.bo); |
474 | |
475 | /* Setup TLB control */ |
476 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, |
477 | (0xA << 7) | |
478 | MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | |
479 | MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | |
480 | MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | |
481 | MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | |
482 | (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); |
483 | /* Setup L2 cache */ |
484 | WREG32(mmVM_L2_CNTL, |
485 | VM_L2_CNTL__ENABLE_L2_CACHE_MASK | |
486 | VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | |
487 | VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | |
488 | VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | |
489 | (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | |
490 | (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); |
491 | WREG32(mmVM_L2_CNTL2, |
492 | VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | |
493 | VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); |
494 | |
495 | field = adev->vm_manager.fragment_size; |
496 | WREG32(mmVM_L2_CNTL3, |
497 | VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | |
498 | (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | |
499 | (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); |
500 | /* setup context0 */ |
501 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); |
502 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); |
503 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); |
504 | WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
505 | (u32)(adev->dummy_page_addr >> 12)); |
506 | WREG32(mmVM_CONTEXT0_CNTL2, 0); |
507 | WREG32(mmVM_CONTEXT0_CNTL, |
508 | VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | |
509 | (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | |
510 | VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); |
511 | |
512 | WREG32(0x575, 0); |
513 | WREG32(0x576, 0); |
514 | WREG32(0x577, 0); |
515 | |
516 | /* empty context1-15 */ |
517 | /* set vm size, must be a multiple of 4 */ |
518 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
519 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); |
520 | /* Assign the pt base to something valid for now; the pts used for |
521 | * the VMs are determined by the application and setup and assigned |
522 | * on the fly in the vm part of radeon_gart.c |
523 | */ |
524 | for (i = 1; i < AMDGPU_NUM_VMID; i++) { |
525 | if (i < 8) |
526 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, |
527 | table_addr >> 12); |
528 | else |
529 | WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, |
530 | table_addr >> 12); |
531 | } |
532 | |
533 | /* enable context1-15 */ |
534 | WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
535 | (u32)(adev->dummy_page_addr >> 12)); |
536 | WREG32(mmVM_CONTEXT1_CNTL2, 4); |
537 | WREG32(mmVM_CONTEXT1_CNTL, |
538 | VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | |
539 | (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | |
540 | ((adev->vm_manager.block_size - 9) |
541 | << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); |
542 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
543 | gmc_v6_0_set_fault_enable_default(adev, value: false); |
544 | else |
545 | gmc_v6_0_set_fault_enable_default(adev, value: true); |
546 | |
547 | gmc_v6_0_flush_gpu_tlb(adev, vmid: 0, vmhub: 0, flush_type: 0); |
548 | dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n" , |
549 | (unsigned int)(adev->gmc.gart_size >> 20), |
550 | (unsigned long long)table_addr); |
551 | return 0; |
552 | } |
553 | |
554 | static int gmc_v6_0_gart_init(struct amdgpu_device *adev) |
555 | { |
556 | int r; |
557 | |
558 | if (adev->gart.bo) { |
559 | dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n" ); |
560 | return 0; |
561 | } |
562 | r = amdgpu_gart_init(adev); |
563 | if (r) |
564 | return r; |
565 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; |
566 | adev->gart.gart_pte_flags = 0; |
567 | return amdgpu_gart_table_vram_alloc(adev); |
568 | } |
569 | |
570 | static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) |
571 | { |
572 | /*unsigned i; |
573 | |
574 | for (i = 1; i < 16; ++i) { |
575 | uint32_t reg; |
576 | if (i < 8) |
577 | reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; |
578 | else |
579 | reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); |
580 | adev->vm_manager.saved_table_addr[i] = RREG32(reg); |
581 | }*/ |
582 | |
583 | /* Disable all tables */ |
584 | WREG32(mmVM_CONTEXT0_CNTL, 0); |
585 | WREG32(mmVM_CONTEXT1_CNTL, 0); |
586 | /* Setup TLB control */ |
587 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, |
588 | MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | |
589 | (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); |
590 | /* Setup L2 cache */ |
591 | WREG32(mmVM_L2_CNTL, |
592 | VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | |
593 | VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | |
594 | (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | |
595 | (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); |
596 | WREG32(mmVM_L2_CNTL2, 0); |
597 | WREG32(mmVM_L2_CNTL3, |
598 | VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | |
599 | (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); |
600 | } |
601 | |
602 | static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, |
603 | u32 status, u32 addr, u32 mc_client) |
604 | { |
605 | u32 mc_id; |
606 | u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); |
607 | u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
608 | PROTECTIONS); |
609 | char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, |
610 | (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; |
611 | |
612 | mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
613 | MEMORY_CLIENT_ID); |
614 | |
615 | dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , |
616 | protections, vmid, addr, |
617 | REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
618 | MEMORY_CLIENT_RW) ? |
619 | "write" : "read" , block, mc_client, mc_id); |
620 | } |
621 | |
622 | /* |
623 | static const u32 mc_cg_registers[] = { |
624 | MC_HUB_MISC_HUB_CG, |
625 | MC_HUB_MISC_SIP_CG, |
626 | MC_HUB_MISC_VM_CG, |
627 | MC_XPB_CLK_GAT, |
628 | ATC_MISC_CG, |
629 | MC_CITF_MISC_WR_CG, |
630 | MC_CITF_MISC_RD_CG, |
631 | MC_CITF_MISC_VM_CG, |
632 | VM_L2_CG, |
633 | }; |
634 | |
635 | static const u32 mc_cg_ls_en[] = { |
636 | MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, |
637 | MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, |
638 | MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, |
639 | MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, |
640 | ATC_MISC_CG__MEM_LS_ENABLE_MASK, |
641 | MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, |
642 | MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, |
643 | MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, |
644 | VM_L2_CG__MEM_LS_ENABLE_MASK, |
645 | }; |
646 | |
647 | static const u32 mc_cg_en[] = { |
648 | MC_HUB_MISC_HUB_CG__ENABLE_MASK, |
649 | MC_HUB_MISC_SIP_CG__ENABLE_MASK, |
650 | MC_HUB_MISC_VM_CG__ENABLE_MASK, |
651 | MC_XPB_CLK_GAT__ENABLE_MASK, |
652 | ATC_MISC_CG__ENABLE_MASK, |
653 | MC_CITF_MISC_WR_CG__ENABLE_MASK, |
654 | MC_CITF_MISC_RD_CG__ENABLE_MASK, |
655 | MC_CITF_MISC_VM_CG__ENABLE_MASK, |
656 | VM_L2_CG__ENABLE_MASK, |
657 | }; |
658 | |
659 | static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, |
660 | bool enable) |
661 | { |
662 | int i; |
663 | u32 orig, data; |
664 | |
665 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { |
666 | orig = data = RREG32(mc_cg_registers[i]); |
667 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) |
668 | data |= mc_cg_ls_en[i]; |
669 | else |
670 | data &= ~mc_cg_ls_en[i]; |
671 | if (data != orig) |
672 | WREG32(mc_cg_registers[i], data); |
673 | } |
674 | } |
675 | |
676 | static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, |
677 | bool enable) |
678 | { |
679 | int i; |
680 | u32 orig, data; |
681 | |
682 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { |
683 | orig = data = RREG32(mc_cg_registers[i]); |
684 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) |
685 | data |= mc_cg_en[i]; |
686 | else |
687 | data &= ~mc_cg_en[i]; |
688 | if (data != orig) |
689 | WREG32(mc_cg_registers[i], data); |
690 | } |
691 | } |
692 | |
693 | static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, |
694 | bool enable) |
695 | { |
696 | u32 orig, data; |
697 | |
698 | orig = data = RREG32_PCIE(ixPCIE_CNTL2); |
699 | |
700 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { |
701 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); |
702 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); |
703 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); |
704 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); |
705 | } else { |
706 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); |
707 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); |
708 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); |
709 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); |
710 | } |
711 | |
712 | if (orig != data) |
713 | WREG32_PCIE(ixPCIE_CNTL2, data); |
714 | } |
715 | |
716 | static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, |
717 | bool enable) |
718 | { |
719 | u32 orig, data; |
720 | |
721 | orig = data = RREG32(mmHDP_HOST_PATH_CNTL); |
722 | |
723 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) |
724 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); |
725 | else |
726 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); |
727 | |
728 | if (orig != data) |
729 | WREG32(mmHDP_HOST_PATH_CNTL, data); |
730 | } |
731 | |
732 | static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, |
733 | bool enable) |
734 | { |
735 | u32 orig, data; |
736 | |
737 | orig = data = RREG32(mmHDP_MEM_POWER_LS); |
738 | |
739 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) |
740 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); |
741 | else |
742 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); |
743 | |
744 | if (orig != data) |
745 | WREG32(mmHDP_MEM_POWER_LS, data); |
746 | } |
747 | */ |
748 | |
749 | static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) |
750 | { |
751 | switch (mc_seq_vram_type) { |
752 | case MC_SEQ_MISC0__MT__GDDR1: |
753 | return AMDGPU_VRAM_TYPE_GDDR1; |
754 | case MC_SEQ_MISC0__MT__DDR2: |
755 | return AMDGPU_VRAM_TYPE_DDR2; |
756 | case MC_SEQ_MISC0__MT__GDDR3: |
757 | return AMDGPU_VRAM_TYPE_GDDR3; |
758 | case MC_SEQ_MISC0__MT__GDDR4: |
759 | return AMDGPU_VRAM_TYPE_GDDR4; |
760 | case MC_SEQ_MISC0__MT__GDDR5: |
761 | return AMDGPU_VRAM_TYPE_GDDR5; |
762 | case MC_SEQ_MISC0__MT__DDR3: |
763 | return AMDGPU_VRAM_TYPE_DDR3; |
764 | default: |
765 | return AMDGPU_VRAM_TYPE_UNKNOWN; |
766 | } |
767 | } |
768 | |
769 | static int gmc_v6_0_early_init(void *handle) |
770 | { |
771 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
772 | |
773 | gmc_v6_0_set_gmc_funcs(adev); |
774 | gmc_v6_0_set_irq_funcs(adev); |
775 | |
776 | return 0; |
777 | } |
778 | |
779 | static int gmc_v6_0_late_init(void *handle) |
780 | { |
781 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
782 | |
783 | if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) |
784 | return amdgpu_irq_get(adev, src: &adev->gmc.vm_fault, type: 0); |
785 | else |
786 | return 0; |
787 | } |
788 | |
789 | static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) |
790 | { |
791 | u32 d1vga_control = RREG32(mmD1VGA_CONTROL); |
792 | unsigned int size; |
793 | |
794 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { |
795 | size = AMDGPU_VBIOS_VGA_ALLOCATION; |
796 | } else { |
797 | u32 viewport = RREG32(mmVIEWPORT_SIZE); |
798 | |
799 | size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * |
800 | REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * |
801 | 4); |
802 | } |
803 | return size; |
804 | } |
805 | |
806 | static int gmc_v6_0_sw_init(void *handle) |
807 | { |
808 | int r; |
809 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
810 | |
811 | set_bit(AMDGPU_GFXHUB(0), addr: adev->vmhubs_mask); |
812 | |
813 | if (adev->flags & AMD_IS_APU) { |
814 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; |
815 | } else { |
816 | u32 tmp = RREG32(mmMC_SEQ_MISC0); |
817 | |
818 | tmp &= MC_SEQ_MISC0__MT__MASK; |
819 | adev->gmc.vram_type = gmc_v6_0_convert_vram_type(mc_seq_vram_type: tmp); |
820 | } |
821 | |
822 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: 146, source: &adev->gmc.vm_fault); |
823 | if (r) |
824 | return r; |
825 | |
826 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: 147, source: &adev->gmc.vm_fault); |
827 | if (r) |
828 | return r; |
829 | |
830 | amdgpu_vm_adjust_size(adev, min_vm_size: 64, fragment_size_default: 9, max_level: 1, max_bits: 40); |
831 | |
832 | adev->gmc.mc_mask = 0xffffffffffULL; |
833 | |
834 | r = dma_set_mask_and_coherent(dev: adev->dev, DMA_BIT_MASK(40)); |
835 | if (r) { |
836 | dev_warn(adev->dev, "No suitable DMA available.\n" ); |
837 | return r; |
838 | } |
839 | adev->need_swiotlb = drm_need_swiotlb(dma_bits: 40); |
840 | |
841 | r = gmc_v6_0_init_microcode(adev); |
842 | if (r) { |
843 | dev_err(adev->dev, "Failed to load mc firmware!\n" ); |
844 | return r; |
845 | } |
846 | |
847 | r = gmc_v6_0_mc_init(adev); |
848 | if (r) |
849 | return r; |
850 | |
851 | amdgpu_gmc_get_vbios_allocations(adev); |
852 | |
853 | r = amdgpu_bo_init(adev); |
854 | if (r) |
855 | return r; |
856 | |
857 | r = gmc_v6_0_gart_init(adev); |
858 | if (r) |
859 | return r; |
860 | |
861 | /* |
862 | * number of VMs |
863 | * VMID 0 is reserved for System |
864 | * amdgpu graphics/compute will use VMIDs 1-7 |
865 | * amdkfd will use VMIDs 8-15 |
866 | */ |
867 | adev->vm_manager.first_kfd_vmid = 8; |
868 | amdgpu_vm_manager_init(adev); |
869 | |
870 | /* base offset of vram pages */ |
871 | if (adev->flags & AMD_IS_APU) { |
872 | u64 tmp = RREG32(mmMC_VM_FB_OFFSET); |
873 | |
874 | tmp <<= 22; |
875 | adev->vm_manager.vram_base_offset = tmp; |
876 | } else { |
877 | adev->vm_manager.vram_base_offset = 0; |
878 | } |
879 | |
880 | return 0; |
881 | } |
882 | |
883 | static int gmc_v6_0_sw_fini(void *handle) |
884 | { |
885 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
886 | |
887 | amdgpu_gem_force_release(adev); |
888 | amdgpu_vm_manager_fini(adev); |
889 | amdgpu_gart_table_vram_free(adev); |
890 | amdgpu_bo_fini(adev); |
891 | amdgpu_ucode_release(fw: &adev->gmc.fw); |
892 | |
893 | return 0; |
894 | } |
895 | |
896 | static int gmc_v6_0_hw_init(void *handle) |
897 | { |
898 | int r; |
899 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
900 | |
901 | gmc_v6_0_mc_program(adev); |
902 | |
903 | if (!(adev->flags & AMD_IS_APU)) { |
904 | r = gmc_v6_0_mc_load_microcode(adev); |
905 | if (r) { |
906 | dev_err(adev->dev, "Failed to load MC firmware!\n" ); |
907 | return r; |
908 | } |
909 | } |
910 | |
911 | r = gmc_v6_0_gart_enable(adev); |
912 | if (r) |
913 | return r; |
914 | |
915 | if (amdgpu_emu_mode == 1) |
916 | return amdgpu_gmc_vram_checking(adev); |
917 | else |
918 | return r; |
919 | } |
920 | |
921 | static int gmc_v6_0_hw_fini(void *handle) |
922 | { |
923 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
924 | |
925 | amdgpu_irq_put(adev, src: &adev->gmc.vm_fault, type: 0); |
926 | gmc_v6_0_gart_disable(adev); |
927 | |
928 | return 0; |
929 | } |
930 | |
931 | static int gmc_v6_0_suspend(void *handle) |
932 | { |
933 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
934 | |
935 | gmc_v6_0_hw_fini(handle: adev); |
936 | |
937 | return 0; |
938 | } |
939 | |
940 | static int gmc_v6_0_resume(void *handle) |
941 | { |
942 | int r; |
943 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
944 | |
945 | r = gmc_v6_0_hw_init(handle: adev); |
946 | if (r) |
947 | return r; |
948 | |
949 | amdgpu_vmid_reset_all(adev); |
950 | |
951 | return 0; |
952 | } |
953 | |
954 | static bool gmc_v6_0_is_idle(void *handle) |
955 | { |
956 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
957 | u32 tmp = RREG32(mmSRBM_STATUS); |
958 | |
959 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | |
960 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) |
961 | return false; |
962 | |
963 | return true; |
964 | } |
965 | |
966 | static int gmc_v6_0_wait_for_idle(void *handle) |
967 | { |
968 | unsigned int i; |
969 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
970 | |
971 | for (i = 0; i < adev->usec_timeout; i++) { |
972 | if (gmc_v6_0_is_idle(handle)) |
973 | return 0; |
974 | udelay(1); |
975 | } |
976 | return -ETIMEDOUT; |
977 | |
978 | } |
979 | |
980 | static int gmc_v6_0_soft_reset(void *handle) |
981 | { |
982 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
983 | u32 srbm_soft_reset = 0; |
984 | u32 tmp = RREG32(mmSRBM_STATUS); |
985 | |
986 | if (tmp & SRBM_STATUS__VMC_BUSY_MASK) |
987 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
988 | SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); |
989 | |
990 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | |
991 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { |
992 | if (!(adev->flags & AMD_IS_APU)) |
993 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
994 | SRBM_SOFT_RESET, SOFT_RESET_MC, 1); |
995 | } |
996 | |
997 | if (srbm_soft_reset) { |
998 | gmc_v6_0_mc_stop(adev); |
999 | if (gmc_v6_0_wait_for_idle(handle: adev)) |
1000 | dev_warn(adev->dev, "Wait for GMC idle timed out !\n" ); |
1001 | |
1002 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1003 | tmp |= srbm_soft_reset; |
1004 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n" , tmp); |
1005 | WREG32(mmSRBM_SOFT_RESET, tmp); |
1006 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1007 | |
1008 | udelay(50); |
1009 | |
1010 | tmp &= ~srbm_soft_reset; |
1011 | WREG32(mmSRBM_SOFT_RESET, tmp); |
1012 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1013 | |
1014 | udelay(50); |
1015 | |
1016 | gmc_v6_0_mc_resume(adev); |
1017 | udelay(50); |
1018 | } |
1019 | |
1020 | return 0; |
1021 | } |
1022 | |
1023 | static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
1024 | struct amdgpu_irq_src *src, |
1025 | unsigned int type, |
1026 | enum amdgpu_interrupt_state state) |
1027 | { |
1028 | u32 tmp; |
1029 | u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
1030 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
1031 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
1032 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
1033 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
1034 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); |
1035 | |
1036 | switch (state) { |
1037 | case AMDGPU_IRQ_STATE_DISABLE: |
1038 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
1039 | tmp &= ~bits; |
1040 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
1041 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
1042 | tmp &= ~bits; |
1043 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
1044 | break; |
1045 | case AMDGPU_IRQ_STATE_ENABLE: |
1046 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
1047 | tmp |= bits; |
1048 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
1049 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
1050 | tmp |= bits; |
1051 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
1052 | break; |
1053 | default: |
1054 | break; |
1055 | } |
1056 | |
1057 | return 0; |
1058 | } |
1059 | |
1060 | static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, |
1061 | struct amdgpu_irq_src *source, |
1062 | struct amdgpu_iv_entry *entry) |
1063 | { |
1064 | u32 addr, status; |
1065 | |
1066 | addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); |
1067 | status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); |
1068 | WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); |
1069 | |
1070 | if (!addr && !status) |
1071 | return 0; |
1072 | |
1073 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) |
1074 | gmc_v6_0_set_fault_enable_default(adev, value: false); |
1075 | |
1076 | if (printk_ratelimit()) { |
1077 | dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n" , |
1078 | entry->src_id, entry->src_data[0]); |
1079 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n" , |
1080 | addr); |
1081 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n" , |
1082 | status); |
1083 | gmc_v6_0_vm_decode_fault(adev, status, addr, mc_client: 0); |
1084 | } |
1085 | |
1086 | return 0; |
1087 | } |
1088 | |
1089 | static int gmc_v6_0_set_clockgating_state(void *handle, |
1090 | enum amd_clockgating_state state) |
1091 | { |
1092 | return 0; |
1093 | } |
1094 | |
1095 | static int gmc_v6_0_set_powergating_state(void *handle, |
1096 | enum amd_powergating_state state) |
1097 | { |
1098 | return 0; |
1099 | } |
1100 | |
1101 | static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { |
1102 | .name = "gmc_v6_0" , |
1103 | .early_init = gmc_v6_0_early_init, |
1104 | .late_init = gmc_v6_0_late_init, |
1105 | .sw_init = gmc_v6_0_sw_init, |
1106 | .sw_fini = gmc_v6_0_sw_fini, |
1107 | .hw_init = gmc_v6_0_hw_init, |
1108 | .hw_fini = gmc_v6_0_hw_fini, |
1109 | .suspend = gmc_v6_0_suspend, |
1110 | .resume = gmc_v6_0_resume, |
1111 | .is_idle = gmc_v6_0_is_idle, |
1112 | .wait_for_idle = gmc_v6_0_wait_for_idle, |
1113 | .soft_reset = gmc_v6_0_soft_reset, |
1114 | .set_clockgating_state = gmc_v6_0_set_clockgating_state, |
1115 | .set_powergating_state = gmc_v6_0_set_powergating_state, |
1116 | }; |
1117 | |
1118 | static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { |
1119 | .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, |
1120 | .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, |
1121 | .set_prt = gmc_v6_0_set_prt, |
1122 | .get_vm_pde = gmc_v6_0_get_vm_pde, |
1123 | .get_vm_pte = gmc_v6_0_get_vm_pte, |
1124 | .get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size, |
1125 | }; |
1126 | |
1127 | static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { |
1128 | .set = gmc_v6_0_vm_fault_interrupt_state, |
1129 | .process = gmc_v6_0_process_interrupt, |
1130 | }; |
1131 | |
1132 | static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) |
1133 | { |
1134 | adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; |
1135 | } |
1136 | |
1137 | static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) |
1138 | { |
1139 | adev->gmc.vm_fault.num_types = 1; |
1140 | adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; |
1141 | } |
1142 | |
1143 | const struct amdgpu_ip_block_version gmc_v6_0_ip_block = { |
1144 | .type = AMD_IP_BLOCK_TYPE_GMC, |
1145 | .major = 6, |
1146 | .minor = 0, |
1147 | .rev = 0, |
1148 | .funcs = &gmc_v6_0_ip_funcs, |
1149 | }; |
1150 | |