1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "cikd.h"
31#include "cik.h"
32#include "gmc_v7_0.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_amdkfd.h"
35#include "amdgpu_gem.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46#include "dce/dce_8_0_d.h"
47#include "dce/dce_8_0_sh_mask.h"
48
49#include "amdgpu_atombios.h"
50
51#include "ivsrcid/ivsrcid_vislands30.h"
52
53static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
54static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static int gmc_v7_0_wait_for_idle(void *handle);
56
57MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
58MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
59MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
60
61static const u32 golden_settings_iceland_a11[] = {
62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
66};
67
68static const u32 iceland_mgcg_cgcg_init[] = {
69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
70};
71
72static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
73{
74 switch (adev->asic_type) {
75 case CHIP_TOPAZ:
76 amdgpu_device_program_register_sequence(adev,
77 registers: iceland_mgcg_cgcg_init,
78 ARRAY_SIZE(iceland_mgcg_cgcg_init));
79 amdgpu_device_program_register_sequence(adev,
80 registers: golden_settings_iceland_a11,
81 ARRAY_SIZE(golden_settings_iceland_a11));
82 break;
83 default:
84 break;
85 }
86}
87
88static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
89{
90 u32 blackout;
91
92 gmc_v7_0_wait_for_idle(handle: (void *)adev);
93
94 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
95 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
96 /* Block CPU access */
97 WREG32(mmBIF_FB_EN, 0);
98 /* blackout the MC */
99 blackout = REG_SET_FIELD(blackout,
100 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
102 }
103 /* wait for the MC to settle */
104 udelay(100);
105}
106
107static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
108{
109 u32 tmp;
110
111 /* unblackout the MC */
112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
113 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
114 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
115 /* allow CPU access */
116 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
117 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
118 WREG32(mmBIF_FB_EN, tmp);
119}
120
121/**
122 * gmc_v7_0_init_microcode - load ucode images from disk
123 *
124 * @adev: amdgpu_device pointer
125 *
126 * Use the firmware interface to load the ucode images into
127 * the driver (not loaded into hw).
128 * Returns 0 on success, error on failure.
129 */
130static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
131{
132 const char *chip_name;
133 char fw_name[30];
134 int err;
135
136 DRM_DEBUG("\n");
137
138 switch (adev->asic_type) {
139 case CHIP_BONAIRE:
140 chip_name = "bonaire";
141 break;
142 case CHIP_HAWAII:
143 chip_name = "hawaii";
144 break;
145 case CHIP_TOPAZ:
146 chip_name = "topaz";
147 break;
148 case CHIP_KAVERI:
149 case CHIP_KABINI:
150 case CHIP_MULLINS:
151 return 0;
152 default:
153 return -EINVAL;
154 }
155
156 snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_mc.bin", chip_name);
157
158 err = amdgpu_ucode_request(adev, fw: &adev->gmc.fw, fw_name);
159 if (err) {
160 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
161 amdgpu_ucode_release(fw: &adev->gmc.fw);
162 }
163 return err;
164}
165
166/**
167 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
168 *
169 * @adev: amdgpu_device pointer
170 *
171 * Load the GDDR MC ucode into the hw (CIK).
172 * Returns 0 on success, error on failure.
173 */
174static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
175{
176 const struct mc_firmware_header_v1_0 *hdr;
177 const __le32 *fw_data = NULL;
178 const __le32 *io_mc_regs = NULL;
179 u32 running;
180 int i, ucode_size, regs_size;
181
182 if (!adev->gmc.fw)
183 return -EINVAL;
184
185 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
186 amdgpu_ucode_print_mc_hdr(hdr: &hdr->header);
187
188 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
189 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
190 io_mc_regs = (const __le32 *)
191 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
192 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
193 fw_data = (const __le32 *)
194 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
195
196 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
197
198 if (running == 0) {
199 /* reset the engine and set to writable */
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
202
203 /* load mc io regs */
204 for (i = 0; i < regs_size; i++) {
205 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
206 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
207 }
208 /* load the MC ucode */
209 for (i = 0; i < ucode_size; i++)
210 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
211
212 /* put the engine back into the active state */
213 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
214 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
215 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
216
217 /* wait for training to complete */
218 for (i = 0; i < adev->usec_timeout; i++) {
219 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
220 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
221 break;
222 udelay(1);
223 }
224 for (i = 0; i < adev->usec_timeout; i++) {
225 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
226 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
227 break;
228 udelay(1);
229 }
230 }
231
232 return 0;
233}
234
235static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
236 struct amdgpu_gmc *mc)
237{
238 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
239
240 base <<= 24;
241
242 amdgpu_gmc_vram_location(adev, mc, base);
243 amdgpu_gmc_gart_location(adev, mc, gart_placement: AMDGPU_GART_PLACEMENT_BEST_FIT);
244}
245
246/**
247 * gmc_v7_0_mc_program - program the GPU memory controller
248 *
249 * @adev: amdgpu_device pointer
250 *
251 * Set the location of vram, gart, and AGP in the GPU's
252 * physical address space (CIK).
253 */
254static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
255{
256 u32 tmp;
257 int i, j;
258
259 /* Initialize HDP */
260 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
261 WREG32((0xb05 + j), 0x00000000);
262 WREG32((0xb06 + j), 0x00000000);
263 WREG32((0xb07 + j), 0x00000000);
264 WREG32((0xb08 + j), 0x00000000);
265 WREG32((0xb09 + j), 0x00000000);
266 }
267 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
268
269 if (gmc_v7_0_wait_for_idle(handle: (void *)adev))
270 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
271
272 if (adev->mode_info.num_crtc) {
273 /* Lockout access through VGA aperture*/
274 tmp = RREG32(mmVGA_HDP_CONTROL);
275 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
276 WREG32(mmVGA_HDP_CONTROL, tmp);
277
278 /* disable VGA render */
279 tmp = RREG32(mmVGA_RENDER_CONTROL);
280 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
281 WREG32(mmVGA_RENDER_CONTROL, tmp);
282 }
283 /* Update configuration */
284 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
285 adev->gmc.vram_start >> 12);
286 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
287 adev->gmc.vram_end >> 12);
288 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
289 adev->mem_scratch.gpu_addr >> 12);
290 WREG32(mmMC_VM_AGP_BASE, 0);
291 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
292 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
293 if (gmc_v7_0_wait_for_idle(handle: (void *)adev))
294 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
295
296 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
297
298 tmp = RREG32(mmHDP_MISC_CNTL);
299 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
300 WREG32(mmHDP_MISC_CNTL, tmp);
301
302 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
303 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
304}
305
306/**
307 * gmc_v7_0_mc_init - initialize the memory controller driver params
308 *
309 * @adev: amdgpu_device pointer
310 *
311 * Look up the amount of vram, vram width, and decide how to place
312 * vram and gart within the GPU's physical address space (CIK).
313 * Returns 0 for success.
314 */
315static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
316{
317 int r;
318
319 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
320 if (!adev->gmc.vram_width) {
321 u32 tmp;
322 int chansize, numchan;
323
324 /* Get VRAM informations */
325 tmp = RREG32(mmMC_ARB_RAMCFG);
326 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
327 chansize = 64;
328 else
329 chansize = 32;
330
331 tmp = RREG32(mmMC_SHARED_CHMAP);
332 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
333 case 0:
334 default:
335 numchan = 1;
336 break;
337 case 1:
338 numchan = 2;
339 break;
340 case 2:
341 numchan = 4;
342 break;
343 case 3:
344 numchan = 8;
345 break;
346 case 4:
347 numchan = 3;
348 break;
349 case 5:
350 numchan = 6;
351 break;
352 case 6:
353 numchan = 10;
354 break;
355 case 7:
356 numchan = 12;
357 break;
358 case 8:
359 numchan = 16;
360 break;
361 }
362 adev->gmc.vram_width = numchan * chansize;
363 }
364 /* size in MB on si */
365 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
366 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
367
368 if (!(adev->flags & AMD_IS_APU)) {
369 r = amdgpu_device_resize_fb_bar(adev);
370 if (r)
371 return r;
372 }
373 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
374 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
375
376#ifdef CONFIG_X86_64
377 if ((adev->flags & AMD_IS_APU) &&
378 adev->gmc.real_vram_size > adev->gmc.aper_size &&
379 !amdgpu_passthrough(adev)) {
380 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
381 adev->gmc.aper_size = adev->gmc.real_vram_size;
382 }
383#endif
384
385 adev->gmc.visible_vram_size = adev->gmc.aper_size;
386
387 /* set the gart size */
388 if (amdgpu_gart_size == -1) {
389 switch (adev->asic_type) {
390 case CHIP_TOPAZ: /* no MM engines */
391 default:
392 adev->gmc.gart_size = 256ULL << 20;
393 break;
394#ifdef CONFIG_DRM_AMDGPU_CIK
395 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
396 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
397 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
398 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
399 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
400 adev->gmc.gart_size = 1024ULL << 20;
401 break;
402#endif
403 }
404 } else {
405 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
406 }
407
408 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
409 gmc_v7_0_vram_gtt_location(adev, mc: &adev->gmc);
410
411 return 0;
412}
413
414/**
415 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
416 *
417 * @adev: amdgpu_device pointer
418 * @pasid: pasid to be flush
419 * @flush_type: type of flush
420 * @all_hub: flush all hubs
421 * @inst: is used to select which instance of KIQ to use for the invalidation
422 *
423 * Flush the TLB for the requested pasid.
424 */
425static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
426 uint16_t pasid, uint32_t flush_type,
427 bool all_hub, uint32_t inst)
428{
429 u32 mask = 0x0;
430 int vmid;
431
432 for (vmid = 1; vmid < 16; vmid++) {
433 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
434
435 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
436 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
437 mask |= 1 << vmid;
438 }
439
440 WREG32(mmVM_INVALIDATE_REQUEST, mask);
441 RREG32(mmVM_INVALIDATE_RESPONSE);
442}
443
444/*
445 * GART
446 * VMID 0 is the physical GPU addresses as used by the kernel.
447 * VMIDs 1-15 are used for userspace clients and are handled
448 * by the amdgpu vm/hsa code.
449 */
450
451/**
452 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
453 *
454 * @adev: amdgpu_device pointer
455 * @vmid: vm instance to flush
456 * @vmhub: which hub to flush
457 * @flush_type: type of flush
458 * *
459 * Flush the TLB for the requested page table (CIK).
460 */
461static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
462 uint32_t vmhub, uint32_t flush_type)
463{
464 /* bits 0-15 are the VM contexts0-15 */
465 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
466}
467
468static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
469 unsigned int vmid, uint64_t pd_addr)
470{
471 uint32_t reg;
472
473 if (vmid < 8)
474 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
475 else
476 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
477 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
478
479 /* bits 0-15 are the VM contexts0-15 */
480 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
481
482 return pd_addr;
483}
484
485static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
486 unsigned int pasid)
487{
488 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
489}
490
491static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
492 uint64_t *addr, uint64_t *flags)
493{
494 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
495}
496
497static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
498 struct amdgpu_bo_va_mapping *mapping,
499 uint64_t *flags)
500{
501 *flags &= ~AMDGPU_PTE_EXECUTABLE;
502 *flags &= ~AMDGPU_PTE_PRT;
503}
504
505/**
506 * gmc_v7_0_set_fault_enable_default - update VM fault handling
507 *
508 * @adev: amdgpu_device pointer
509 * @value: true redirects VM faults to the default page
510 */
511static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
512 bool value)
513{
514 u32 tmp;
515
516 tmp = RREG32(mmVM_CONTEXT1_CNTL);
517 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
518 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
519 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
520 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
522 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
524 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
526 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
528 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
529 WREG32(mmVM_CONTEXT1_CNTL, tmp);
530}
531
532/**
533 * gmc_v7_0_set_prt - set PRT VM fault
534 *
535 * @adev: amdgpu_device pointer
536 * @enable: enable/disable VM fault handling for PRT
537 */
538static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
539{
540 uint32_t tmp;
541
542 if (enable && !adev->gmc.prt_warning) {
543 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
544 adev->gmc.prt_warning = true;
545 }
546
547 tmp = RREG32(mmVM_PRT_CNTL);
548 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
549 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
550 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
551 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
552 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
553 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
554 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
555 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
557 L2_CACHE_STORE_INVALID_ENTRIES, enable);
558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
559 L1_TLB_STORE_INVALID_ENTRIES, enable);
560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
561 MASK_PDE0_FAULT, enable);
562 WREG32(mmVM_PRT_CNTL, tmp);
563
564 if (enable) {
565 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
566 uint32_t high = adev->vm_manager.max_pfn -
567 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
568
569 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
570 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
571 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
572 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
573 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
574 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
575 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
576 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
577 } else {
578 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
579 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
580 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
581 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
582 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
583 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
584 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
585 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
586 }
587}
588
589/**
590 * gmc_v7_0_gart_enable - gart enable
591 *
592 * @adev: amdgpu_device pointer
593 *
594 * This sets up the TLBs, programs the page tables for VMID0,
595 * sets up the hw for VMIDs 1-15 which are allocated on
596 * demand, and sets up the global locations for the LDS, GDS,
597 * and GPUVM for FSA64 clients (CIK).
598 * Returns 0 for success, errors for failure.
599 */
600static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
601{
602 uint64_t table_addr;
603 u32 tmp, field;
604 int i;
605
606 if (adev->gart.bo == NULL) {
607 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
608 return -EINVAL;
609 }
610 amdgpu_gtt_mgr_recover(mgr: &adev->mman.gtt_mgr);
611 table_addr = amdgpu_bo_gpu_offset(bo: adev->gart.bo);
612
613 /* Setup TLB control */
614 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
620 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
621 /* Setup L2 cache */
622 tmp = RREG32(mmVM_L2_CNTL);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
630 WREG32(mmVM_L2_CNTL, tmp);
631 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
633 WREG32(mmVM_L2_CNTL2, tmp);
634
635 field = adev->vm_manager.fragment_size;
636 tmp = RREG32(mmVM_L2_CNTL3);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
640 WREG32(mmVM_L2_CNTL3, tmp);
641 /* setup context0 */
642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
644 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
645 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
646 (u32)(adev->dummy_page_addr >> 12));
647 WREG32(mmVM_CONTEXT0_CNTL2, 0);
648 tmp = RREG32(mmVM_CONTEXT0_CNTL);
649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
651 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
652 WREG32(mmVM_CONTEXT0_CNTL, tmp);
653
654 WREG32(0x575, 0);
655 WREG32(0x576, 0);
656 WREG32(0x577, 0);
657
658 /* empty context1-15 */
659 /* FIXME start with 4G, once using 2 level pt switch to full
660 * vm size space
661 */
662 /* set vm size, must be a multiple of 4 */
663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
664 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
665 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
666 if (i < 8)
667 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
668 table_addr >> 12);
669 else
670 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
671 table_addr >> 12);
672 }
673
674 /* enable context1-15 */
675 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
676 (u32)(adev->dummy_page_addr >> 12));
677 WREG32(mmVM_CONTEXT1_CNTL2, 4);
678 tmp = RREG32(mmVM_CONTEXT1_CNTL);
679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
682 adev->vm_manager.block_size - 9);
683 WREG32(mmVM_CONTEXT1_CNTL, tmp);
684 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
685 gmc_v7_0_set_fault_enable_default(adev, value: false);
686 else
687 gmc_v7_0_set_fault_enable_default(adev, value: true);
688
689 if (adev->asic_type == CHIP_KAVERI) {
690 tmp = RREG32(mmCHUB_CONTROL);
691 tmp &= ~BYPASS_VM;
692 WREG32(mmCHUB_CONTROL, tmp);
693 }
694
695 gmc_v7_0_flush_gpu_tlb(adev, vmid: 0, vmhub: 0, flush_type: 0);
696 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
697 (unsigned int)(adev->gmc.gart_size >> 20),
698 (unsigned long long)table_addr);
699 return 0;
700}
701
702static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
703{
704 int r;
705
706 if (adev->gart.bo) {
707 WARN(1, "R600 PCIE GART already initialized\n");
708 return 0;
709 }
710 /* Initialize common gart structure */
711 r = amdgpu_gart_init(adev);
712 if (r)
713 return r;
714 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
715 adev->gart.gart_pte_flags = 0;
716 return amdgpu_gart_table_vram_alloc(adev);
717}
718
719/**
720 * gmc_v7_0_gart_disable - gart disable
721 *
722 * @adev: amdgpu_device pointer
723 *
724 * This disables all VM page table (CIK).
725 */
726static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
727{
728 u32 tmp;
729
730 /* Disable all tables */
731 WREG32(mmVM_CONTEXT0_CNTL, 0);
732 WREG32(mmVM_CONTEXT1_CNTL, 0);
733 /* Setup TLB control */
734 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
735 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
737 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
738 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
739 /* Setup L2 cache */
740 tmp = RREG32(mmVM_L2_CNTL);
741 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
742 WREG32(mmVM_L2_CNTL, tmp);
743 WREG32(mmVM_L2_CNTL2, 0);
744}
745
746/**
747 * gmc_v7_0_vm_decode_fault - print human readable fault info
748 *
749 * @adev: amdgpu_device pointer
750 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
751 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
752 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
753 * @pasid: debug logging only - no functional use
754 *
755 * Print human readable fault information (CIK).
756 */
757static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
758 u32 addr, u32 mc_client, unsigned int pasid)
759{
760 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
761 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
762 PROTECTIONS);
763 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
764 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
765 u32 mc_id;
766
767 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
768 MEMORY_CLIENT_ID);
769
770 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
771 protections, vmid, pasid, addr,
772 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
773 MEMORY_CLIENT_RW) ?
774 "write" : "read", block, mc_client, mc_id);
775}
776
777
778static const u32 mc_cg_registers[] = {
779 mmMC_HUB_MISC_HUB_CG,
780 mmMC_HUB_MISC_SIP_CG,
781 mmMC_HUB_MISC_VM_CG,
782 mmMC_XPB_CLK_GAT,
783 mmATC_MISC_CG,
784 mmMC_CITF_MISC_WR_CG,
785 mmMC_CITF_MISC_RD_CG,
786 mmMC_CITF_MISC_VM_CG,
787 mmVM_L2_CG,
788};
789
790static const u32 mc_cg_ls_en[] = {
791 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
792 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
793 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
794 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
795 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
796 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
797 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
798 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
799 VM_L2_CG__MEM_LS_ENABLE_MASK,
800};
801
802static const u32 mc_cg_en[] = {
803 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
804 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
805 MC_HUB_MISC_VM_CG__ENABLE_MASK,
806 MC_XPB_CLK_GAT__ENABLE_MASK,
807 ATC_MISC_CG__ENABLE_MASK,
808 MC_CITF_MISC_WR_CG__ENABLE_MASK,
809 MC_CITF_MISC_RD_CG__ENABLE_MASK,
810 MC_CITF_MISC_VM_CG__ENABLE_MASK,
811 VM_L2_CG__ENABLE_MASK,
812};
813
814static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
815 bool enable)
816{
817 int i;
818 u32 orig, data;
819
820 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
821 orig = data = RREG32(mc_cg_registers[i]);
822 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
823 data |= mc_cg_ls_en[i];
824 else
825 data &= ~mc_cg_ls_en[i];
826 if (data != orig)
827 WREG32(mc_cg_registers[i], data);
828 }
829}
830
831static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
832 bool enable)
833{
834 int i;
835 u32 orig, data;
836
837 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
838 orig = data = RREG32(mc_cg_registers[i]);
839 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
840 data |= mc_cg_en[i];
841 else
842 data &= ~mc_cg_en[i];
843 if (data != orig)
844 WREG32(mc_cg_registers[i], data);
845 }
846}
847
848static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
849 bool enable)
850{
851 u32 orig, data;
852
853 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
854
855 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
856 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
857 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
858 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
859 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
860 } else {
861 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
862 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
863 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
864 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
865 }
866
867 if (orig != data)
868 WREG32_PCIE(ixPCIE_CNTL2, data);
869}
870
871static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
872 bool enable)
873{
874 u32 orig, data;
875
876 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
877
878 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
879 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
880 else
881 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
882
883 if (orig != data)
884 WREG32(mmHDP_HOST_PATH_CNTL, data);
885}
886
887static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
888 bool enable)
889{
890 u32 orig, data;
891
892 orig = data = RREG32(mmHDP_MEM_POWER_LS);
893
894 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
895 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
896 else
897 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
898
899 if (orig != data)
900 WREG32(mmHDP_MEM_POWER_LS, data);
901}
902
903static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
904{
905 switch (mc_seq_vram_type) {
906 case MC_SEQ_MISC0__MT__GDDR1:
907 return AMDGPU_VRAM_TYPE_GDDR1;
908 case MC_SEQ_MISC0__MT__DDR2:
909 return AMDGPU_VRAM_TYPE_DDR2;
910 case MC_SEQ_MISC0__MT__GDDR3:
911 return AMDGPU_VRAM_TYPE_GDDR3;
912 case MC_SEQ_MISC0__MT__GDDR4:
913 return AMDGPU_VRAM_TYPE_GDDR4;
914 case MC_SEQ_MISC0__MT__GDDR5:
915 return AMDGPU_VRAM_TYPE_GDDR5;
916 case MC_SEQ_MISC0__MT__HBM:
917 return AMDGPU_VRAM_TYPE_HBM;
918 case MC_SEQ_MISC0__MT__DDR3:
919 return AMDGPU_VRAM_TYPE_DDR3;
920 default:
921 return AMDGPU_VRAM_TYPE_UNKNOWN;
922 }
923}
924
925static int gmc_v7_0_early_init(void *handle)
926{
927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
928
929 gmc_v7_0_set_gmc_funcs(adev);
930 gmc_v7_0_set_irq_funcs(adev);
931
932 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
933 adev->gmc.shared_aperture_end =
934 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
935 adev->gmc.private_aperture_start =
936 adev->gmc.shared_aperture_end + 1;
937 adev->gmc.private_aperture_end =
938 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
939 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
940
941 return 0;
942}
943
944static int gmc_v7_0_late_init(void *handle)
945{
946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
947
948 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
949 return amdgpu_irq_get(adev, src: &adev->gmc.vm_fault, type: 0);
950 else
951 return 0;
952}
953
954static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
955{
956 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
957 unsigned int size;
958
959 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
960 size = AMDGPU_VBIOS_VGA_ALLOCATION;
961 } else {
962 u32 viewport = RREG32(mmVIEWPORT_SIZE);
963
964 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
965 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
966 4);
967 }
968
969 return size;
970}
971
972static int gmc_v7_0_sw_init(void *handle)
973{
974 int r;
975 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
976
977 set_bit(AMDGPU_GFXHUB(0), addr: adev->vmhubs_mask);
978
979 if (adev->flags & AMD_IS_APU) {
980 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
981 } else {
982 u32 tmp = RREG32(mmMC_SEQ_MISC0);
983
984 tmp &= MC_SEQ_MISC0__MT__MASK;
985 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(mc_seq_vram_type: tmp);
986 }
987
988 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, source: &adev->gmc.vm_fault);
989 if (r)
990 return r;
991
992 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, source: &adev->gmc.vm_fault);
993 if (r)
994 return r;
995
996 /* Adjust VM size here.
997 * Currently set to 4GB ((1 << 20) 4k pages).
998 * Max GPUVM size for cayman and SI is 40 bits.
999 */
1000 amdgpu_vm_adjust_size(adev, min_vm_size: 64, fragment_size_default: 9, max_level: 1, max_bits: 40);
1001
1002 /* Set the internal MC address mask
1003 * This is the max address of the GPU's
1004 * internal address space.
1005 */
1006 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1007
1008 r = dma_set_mask_and_coherent(dev: adev->dev, DMA_BIT_MASK(40));
1009 if (r) {
1010 pr_warn("No suitable DMA available\n");
1011 return r;
1012 }
1013 adev->need_swiotlb = drm_need_swiotlb(dma_bits: 40);
1014
1015 r = gmc_v7_0_init_microcode(adev);
1016 if (r) {
1017 DRM_ERROR("Failed to load mc firmware!\n");
1018 return r;
1019 }
1020
1021 r = gmc_v7_0_mc_init(adev);
1022 if (r)
1023 return r;
1024
1025 amdgpu_gmc_get_vbios_allocations(adev);
1026
1027 /* Memory manager */
1028 r = amdgpu_bo_init(adev);
1029 if (r)
1030 return r;
1031
1032 r = gmc_v7_0_gart_init(adev);
1033 if (r)
1034 return r;
1035
1036 /*
1037 * number of VMs
1038 * VMID 0 is reserved for System
1039 * amdgpu graphics/compute will use VMIDs 1-7
1040 * amdkfd will use VMIDs 8-15
1041 */
1042 adev->vm_manager.first_kfd_vmid = 8;
1043 amdgpu_vm_manager_init(adev);
1044
1045 /* base offset of vram pages */
1046 if (adev->flags & AMD_IS_APU) {
1047 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1048
1049 tmp <<= 22;
1050 adev->vm_manager.vram_base_offset = tmp;
1051 } else {
1052 adev->vm_manager.vram_base_offset = 0;
1053 }
1054
1055 adev->gmc.vm_fault_info = kmalloc(size: sizeof(struct kfd_vm_fault_info),
1056 GFP_KERNEL);
1057 if (!adev->gmc.vm_fault_info)
1058 return -ENOMEM;
1059 atomic_set(v: &adev->gmc.vm_fault_info_updated, i: 0);
1060
1061 return 0;
1062}
1063
1064static int gmc_v7_0_sw_fini(void *handle)
1065{
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067
1068 amdgpu_gem_force_release(adev);
1069 amdgpu_vm_manager_fini(adev);
1070 kfree(objp: adev->gmc.vm_fault_info);
1071 amdgpu_gart_table_vram_free(adev);
1072 amdgpu_bo_fini(adev);
1073 amdgpu_ucode_release(fw: &adev->gmc.fw);
1074
1075 return 0;
1076}
1077
1078static int gmc_v7_0_hw_init(void *handle)
1079{
1080 int r;
1081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082
1083 gmc_v7_0_init_golden_registers(adev);
1084
1085 gmc_v7_0_mc_program(adev);
1086
1087 if (!(adev->flags & AMD_IS_APU)) {
1088 r = gmc_v7_0_mc_load_microcode(adev);
1089 if (r) {
1090 DRM_ERROR("Failed to load MC firmware!\n");
1091 return r;
1092 }
1093 }
1094
1095 r = gmc_v7_0_gart_enable(adev);
1096 if (r)
1097 return r;
1098
1099 if (amdgpu_emu_mode == 1)
1100 return amdgpu_gmc_vram_checking(adev);
1101 else
1102 return r;
1103}
1104
1105static int gmc_v7_0_hw_fini(void *handle)
1106{
1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1108
1109 amdgpu_irq_put(adev, src: &adev->gmc.vm_fault, type: 0);
1110 gmc_v7_0_gart_disable(adev);
1111
1112 return 0;
1113}
1114
1115static int gmc_v7_0_suspend(void *handle)
1116{
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1119 gmc_v7_0_hw_fini(handle: adev);
1120
1121 return 0;
1122}
1123
1124static int gmc_v7_0_resume(void *handle)
1125{
1126 int r;
1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1128
1129 r = gmc_v7_0_hw_init(handle: adev);
1130 if (r)
1131 return r;
1132
1133 amdgpu_vmid_reset_all(adev);
1134
1135 return 0;
1136}
1137
1138static bool gmc_v7_0_is_idle(void *handle)
1139{
1140 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141 u32 tmp = RREG32(mmSRBM_STATUS);
1142
1143 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1144 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1145 return false;
1146
1147 return true;
1148}
1149
1150static int gmc_v7_0_wait_for_idle(void *handle)
1151{
1152 unsigned int i;
1153 u32 tmp;
1154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1155
1156 for (i = 0; i < adev->usec_timeout; i++) {
1157 /* read MC_STATUS */
1158 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1159 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1160 SRBM_STATUS__MCC_BUSY_MASK |
1161 SRBM_STATUS__MCD_BUSY_MASK |
1162 SRBM_STATUS__VMC_BUSY_MASK);
1163 if (!tmp)
1164 return 0;
1165 udelay(1);
1166 }
1167 return -ETIMEDOUT;
1168
1169}
1170
1171static int gmc_v7_0_soft_reset(void *handle)
1172{
1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1174 u32 srbm_soft_reset = 0;
1175 u32 tmp = RREG32(mmSRBM_STATUS);
1176
1177 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1178 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1179 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1180
1181 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1182 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1183 if (!(adev->flags & AMD_IS_APU))
1184 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1185 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1186 }
1187
1188 if (srbm_soft_reset) {
1189 gmc_v7_0_mc_stop(adev);
1190 if (gmc_v7_0_wait_for_idle(handle: (void *)adev))
1191 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1192
1193 tmp = RREG32(mmSRBM_SOFT_RESET);
1194 tmp |= srbm_soft_reset;
1195 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1196 WREG32(mmSRBM_SOFT_RESET, tmp);
1197 tmp = RREG32(mmSRBM_SOFT_RESET);
1198
1199 udelay(50);
1200
1201 tmp &= ~srbm_soft_reset;
1202 WREG32(mmSRBM_SOFT_RESET, tmp);
1203 tmp = RREG32(mmSRBM_SOFT_RESET);
1204
1205 /* Wait a little for things to settle down */
1206 udelay(50);
1207
1208 gmc_v7_0_mc_resume(adev);
1209 udelay(50);
1210 }
1211
1212 return 0;
1213}
1214
1215static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1216 struct amdgpu_irq_src *src,
1217 unsigned int type,
1218 enum amdgpu_interrupt_state state)
1219{
1220 u32 tmp;
1221 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1222 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1223 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1224 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1225 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1227
1228 switch (state) {
1229 case AMDGPU_IRQ_STATE_DISABLE:
1230 /* system context */
1231 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1232 tmp &= ~bits;
1233 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1234 /* VMs */
1235 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1236 tmp &= ~bits;
1237 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1238 break;
1239 case AMDGPU_IRQ_STATE_ENABLE:
1240 /* system context */
1241 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1242 tmp |= bits;
1243 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1244 /* VMs */
1245 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1246 tmp |= bits;
1247 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1248 break;
1249 default:
1250 break;
1251 }
1252
1253 return 0;
1254}
1255
1256static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1257 struct amdgpu_irq_src *source,
1258 struct amdgpu_iv_entry *entry)
1259{
1260 u32 addr, status, mc_client, vmid;
1261
1262 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1263 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1264 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1265 /* reset addr and status */
1266 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1267
1268 if (!addr && !status)
1269 return 0;
1270
1271 amdgpu_vm_update_fault_cache(adev, pasid: entry->pasid,
1272 addr: ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1273
1274 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1275 gmc_v7_0_set_fault_enable_default(adev, value: false);
1276
1277 if (printk_ratelimit()) {
1278 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1279 entry->src_id, entry->src_data[0]);
1280 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1281 addr);
1282 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1283 status);
1284 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1285 pasid: entry->pasid);
1286 }
1287
1288 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1289 VMID);
1290 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1291 && !atomic_read(v: &adev->gmc.vm_fault_info_updated)) {
1292 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1293 u32 protections = REG_GET_FIELD(status,
1294 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1295 PROTECTIONS);
1296
1297 info->vmid = vmid;
1298 info->mc_id = REG_GET_FIELD(status,
1299 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1300 MEMORY_CLIENT_ID);
1301 info->status = status;
1302 info->page_addr = addr;
1303 info->prot_valid = protections & 0x7 ? true : false;
1304 info->prot_read = protections & 0x8 ? true : false;
1305 info->prot_write = protections & 0x10 ? true : false;
1306 info->prot_exec = protections & 0x20 ? true : false;
1307 mb();
1308 atomic_set(v: &adev->gmc.vm_fault_info_updated, i: 1);
1309 }
1310
1311 return 0;
1312}
1313
1314static int gmc_v7_0_set_clockgating_state(void *handle,
1315 enum amd_clockgating_state state)
1316{
1317 bool gate = false;
1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1319
1320 if (state == AMD_CG_STATE_GATE)
1321 gate = true;
1322
1323 if (!(adev->flags & AMD_IS_APU)) {
1324 gmc_v7_0_enable_mc_mgcg(adev, enable: gate);
1325 gmc_v7_0_enable_mc_ls(adev, enable: gate);
1326 }
1327 gmc_v7_0_enable_bif_mgls(adev, enable: gate);
1328 gmc_v7_0_enable_hdp_mgcg(adev, enable: gate);
1329 gmc_v7_0_enable_hdp_ls(adev, enable: gate);
1330
1331 return 0;
1332}
1333
1334static int gmc_v7_0_set_powergating_state(void *handle,
1335 enum amd_powergating_state state)
1336{
1337 return 0;
1338}
1339
1340static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1341 .name = "gmc_v7_0",
1342 .early_init = gmc_v7_0_early_init,
1343 .late_init = gmc_v7_0_late_init,
1344 .sw_init = gmc_v7_0_sw_init,
1345 .sw_fini = gmc_v7_0_sw_fini,
1346 .hw_init = gmc_v7_0_hw_init,
1347 .hw_fini = gmc_v7_0_hw_fini,
1348 .suspend = gmc_v7_0_suspend,
1349 .resume = gmc_v7_0_resume,
1350 .is_idle = gmc_v7_0_is_idle,
1351 .wait_for_idle = gmc_v7_0_wait_for_idle,
1352 .soft_reset = gmc_v7_0_soft_reset,
1353 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1354 .set_powergating_state = gmc_v7_0_set_powergating_state,
1355};
1356
1357static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1358 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1359 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1360 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1361 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1362 .set_prt = gmc_v7_0_set_prt,
1363 .get_vm_pde = gmc_v7_0_get_vm_pde,
1364 .get_vm_pte = gmc_v7_0_get_vm_pte,
1365 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1366};
1367
1368static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1369 .set = gmc_v7_0_vm_fault_interrupt_state,
1370 .process = gmc_v7_0_process_interrupt,
1371};
1372
1373static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1374{
1375 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1376}
1377
1378static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1379{
1380 adev->gmc.vm_fault.num_types = 1;
1381 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1382}
1383
1384const struct amdgpu_ip_block_version gmc_v7_0_ip_block = {
1385 .type = AMD_IP_BLOCK_TYPE_GMC,
1386 .major = 7,
1387 .minor = 0,
1388 .rev = 0,
1389 .funcs = &gmc_v7_0_ip_funcs,
1390};
1391
1392const struct amdgpu_ip_block_version gmc_v7_4_ip_block = {
1393 .type = AMD_IP_BLOCK_TYPE_GMC,
1394 .major = 7,
1395 .minor = 4,
1396 .rev = 0,
1397 .funcs = &gmc_v7_0_ip_funcs,
1398};
1399

source code of linux/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c