1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/pci.h> |
25 | |
26 | #include "amdgpu.h" |
27 | #include "amdgpu_ih.h" |
28 | #include "vid.h" |
29 | |
30 | #include "oss/oss_2_4_d.h" |
31 | #include "oss/oss_2_4_sh_mask.h" |
32 | |
33 | #include "bif/bif_5_1_d.h" |
34 | #include "bif/bif_5_1_sh_mask.h" |
35 | |
36 | /* |
37 | * Interrupts |
38 | * Starting with r6xx, interrupts are handled via a ring buffer. |
39 | * Ring buffers are areas of GPU accessible memory that the GPU |
40 | * writes interrupt vectors into and the host reads vectors out of. |
41 | * There is a rptr (read pointer) that determines where the |
42 | * host is currently reading, and a wptr (write pointer) |
43 | * which determines where the GPU has written. When the |
44 | * pointers are equal, the ring is idle. When the GPU |
45 | * writes vectors to the ring buffer, it increments the |
46 | * wptr. When there is an interrupt, the host then starts |
47 | * fetching commands and processing them until the pointers are |
48 | * equal again at which point it updates the rptr. |
49 | */ |
50 | |
51 | static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev); |
52 | |
53 | /** |
54 | * iceland_ih_enable_interrupts - Enable the interrupt ring buffer |
55 | * |
56 | * @adev: amdgpu_device pointer |
57 | * |
58 | * Enable the interrupt ring buffer (VI). |
59 | */ |
60 | static void iceland_ih_enable_interrupts(struct amdgpu_device *adev) |
61 | { |
62 | u32 ih_cntl = RREG32(mmIH_CNTL); |
63 | u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); |
64 | |
65 | ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); |
66 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); |
67 | WREG32(mmIH_CNTL, ih_cntl); |
68 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
69 | adev->irq.ih.enabled = true; |
70 | } |
71 | |
72 | /** |
73 | * iceland_ih_disable_interrupts - Disable the interrupt ring buffer |
74 | * |
75 | * @adev: amdgpu_device pointer |
76 | * |
77 | * Disable the interrupt ring buffer (VI). |
78 | */ |
79 | static void iceland_ih_disable_interrupts(struct amdgpu_device *adev) |
80 | { |
81 | u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); |
82 | u32 ih_cntl = RREG32(mmIH_CNTL); |
83 | |
84 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); |
85 | ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); |
86 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
87 | WREG32(mmIH_CNTL, ih_cntl); |
88 | /* set rptr, wptr to 0 */ |
89 | WREG32(mmIH_RB_RPTR, 0); |
90 | WREG32(mmIH_RB_WPTR, 0); |
91 | adev->irq.ih.enabled = false; |
92 | adev->irq.ih.rptr = 0; |
93 | } |
94 | |
95 | /** |
96 | * iceland_ih_irq_init - init and enable the interrupt ring |
97 | * |
98 | * @adev: amdgpu_device pointer |
99 | * |
100 | * Allocate a ring buffer for the interrupt controller, |
101 | * enable the RLC, disable interrupts, enable the IH |
102 | * ring buffer and enable it (VI). |
103 | * Called at device load and reume. |
104 | * Returns 0 for success, errors for failure. |
105 | */ |
106 | static int iceland_ih_irq_init(struct amdgpu_device *adev) |
107 | { |
108 | struct amdgpu_ih_ring *ih = &adev->irq.ih; |
109 | int rb_bufsz; |
110 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; |
111 | |
112 | /* disable irqs */ |
113 | iceland_ih_disable_interrupts(adev); |
114 | |
115 | /* setup interrupt control */ |
116 | WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); |
117 | interrupt_cntl = RREG32(mmINTERRUPT_CNTL); |
118 | /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi |
119 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN |
120 | */ |
121 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); |
122 | /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ |
123 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); |
124 | WREG32(mmINTERRUPT_CNTL, interrupt_cntl); |
125 | |
126 | /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ |
127 | WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); |
128 | |
129 | rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); |
130 | ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); |
131 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
132 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); |
133 | |
134 | /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ |
135 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); |
136 | |
137 | /* set the writeback address whether it's enabled or not */ |
138 | WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); |
139 | WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); |
140 | |
141 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
142 | |
143 | /* set rptr, wptr to 0 */ |
144 | WREG32(mmIH_RB_RPTR, 0); |
145 | WREG32(mmIH_RB_WPTR, 0); |
146 | |
147 | /* Default settings for IH_CNTL (disabled at first) */ |
148 | ih_cntl = RREG32(mmIH_CNTL); |
149 | ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); |
150 | |
151 | if (adev->irq.msi_enabled) |
152 | ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); |
153 | WREG32(mmIH_CNTL, ih_cntl); |
154 | |
155 | pci_set_master(dev: adev->pdev); |
156 | |
157 | /* enable interrupts */ |
158 | iceland_ih_enable_interrupts(adev); |
159 | |
160 | return 0; |
161 | } |
162 | |
163 | /** |
164 | * iceland_ih_irq_disable - disable interrupts |
165 | * |
166 | * @adev: amdgpu_device pointer |
167 | * |
168 | * Disable interrupts on the hw (VI). |
169 | */ |
170 | static void iceland_ih_irq_disable(struct amdgpu_device *adev) |
171 | { |
172 | iceland_ih_disable_interrupts(adev); |
173 | |
174 | /* Wait and acknowledge irq */ |
175 | mdelay(1); |
176 | } |
177 | |
178 | /** |
179 | * iceland_ih_get_wptr - get the IH ring buffer wptr |
180 | * |
181 | * @adev: amdgpu_device pointer |
182 | * @ih: IH ring buffer to fetch wptr |
183 | * |
184 | * Get the IH ring buffer wptr from either the register |
185 | * or the writeback memory buffer (VI). Also check for |
186 | * ring buffer overflow and deal with it. |
187 | * Used by cz_irq_process(VI). |
188 | * Returns the value of the wptr. |
189 | */ |
190 | static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, |
191 | struct amdgpu_ih_ring *ih) |
192 | { |
193 | u32 wptr, tmp; |
194 | |
195 | wptr = le32_to_cpu(*ih->wptr_cpu); |
196 | |
197 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) |
198 | goto out; |
199 | |
200 | /* Double check that the overflow wasn't already cleared. */ |
201 | wptr = RREG32(mmIH_RB_WPTR); |
202 | |
203 | if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) |
204 | goto out; |
205 | |
206 | wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); |
207 | /* When a ring buffer overflow happen start parsing interrupt |
208 | * from the last not overwritten vector (wptr + 16). Hopefully |
209 | * this should allow us to catchup. |
210 | */ |
211 | dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n" , |
212 | wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); |
213 | ih->rptr = (wptr + 16) & ih->ptr_mask; |
214 | tmp = RREG32(mmIH_RB_CNTL); |
215 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
216 | WREG32(mmIH_RB_CNTL, tmp); |
217 | |
218 | |
219 | out: |
220 | return (wptr & ih->ptr_mask); |
221 | } |
222 | |
223 | /** |
224 | * iceland_ih_decode_iv - decode an interrupt vector |
225 | * |
226 | * @adev: amdgpu_device pointer |
227 | * @ih: IH ring buffer to decode |
228 | * @entry: IV entry to place decoded information into |
229 | * |
230 | * Decodes the interrupt vector at the current rptr |
231 | * position and also advance the position. |
232 | */ |
233 | static void iceland_ih_decode_iv(struct amdgpu_device *adev, |
234 | struct amdgpu_ih_ring *ih, |
235 | struct amdgpu_iv_entry *entry) |
236 | { |
237 | /* wptr/rptr are in bytes! */ |
238 | u32 ring_index = ih->rptr >> 2; |
239 | uint32_t dw[4]; |
240 | |
241 | dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); |
242 | dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); |
243 | dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); |
244 | dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); |
245 | |
246 | entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
247 | entry->src_id = dw[0] & 0xff; |
248 | entry->src_data[0] = dw[1] & 0xfffffff; |
249 | entry->ring_id = dw[2] & 0xff; |
250 | entry->vmid = (dw[2] >> 8) & 0xff; |
251 | entry->pasid = (dw[2] >> 16) & 0xffff; |
252 | |
253 | /* wptr/rptr are in bytes! */ |
254 | ih->rptr += 16; |
255 | } |
256 | |
257 | /** |
258 | * iceland_ih_set_rptr - set the IH ring buffer rptr |
259 | * |
260 | * @adev: amdgpu_device pointer |
261 | * @ih: IH ring buffer to set rptr |
262 | * |
263 | * Set the IH ring buffer rptr. |
264 | */ |
265 | static void iceland_ih_set_rptr(struct amdgpu_device *adev, |
266 | struct amdgpu_ih_ring *ih) |
267 | { |
268 | WREG32(mmIH_RB_RPTR, ih->rptr); |
269 | } |
270 | |
271 | static int iceland_ih_early_init(void *handle) |
272 | { |
273 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
274 | int ret; |
275 | |
276 | ret = amdgpu_irq_add_domain(adev); |
277 | if (ret) |
278 | return ret; |
279 | |
280 | iceland_ih_set_interrupt_funcs(adev); |
281 | |
282 | return 0; |
283 | } |
284 | |
285 | static int iceland_ih_sw_init(void *handle) |
286 | { |
287 | int r; |
288 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
289 | |
290 | r = amdgpu_ih_ring_init(adev, ih: &adev->irq.ih, ring_size: 64 * 1024, use_bus_addr: false); |
291 | if (r) |
292 | return r; |
293 | |
294 | r = amdgpu_irq_init(adev); |
295 | |
296 | return r; |
297 | } |
298 | |
299 | static int iceland_ih_sw_fini(void *handle) |
300 | { |
301 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
302 | |
303 | amdgpu_irq_fini_sw(adev); |
304 | amdgpu_irq_remove_domain(adev); |
305 | |
306 | return 0; |
307 | } |
308 | |
309 | static int iceland_ih_hw_init(void *handle) |
310 | { |
311 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
312 | |
313 | return iceland_ih_irq_init(adev); |
314 | } |
315 | |
316 | static int iceland_ih_hw_fini(void *handle) |
317 | { |
318 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
319 | |
320 | iceland_ih_irq_disable(adev); |
321 | |
322 | return 0; |
323 | } |
324 | |
325 | static int iceland_ih_suspend(void *handle) |
326 | { |
327 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
328 | |
329 | return iceland_ih_hw_fini(handle: adev); |
330 | } |
331 | |
332 | static int iceland_ih_resume(void *handle) |
333 | { |
334 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
335 | |
336 | return iceland_ih_hw_init(handle: adev); |
337 | } |
338 | |
339 | static bool iceland_ih_is_idle(void *handle) |
340 | { |
341 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
342 | u32 tmp = RREG32(mmSRBM_STATUS); |
343 | |
344 | if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) |
345 | return false; |
346 | |
347 | return true; |
348 | } |
349 | |
350 | static int iceland_ih_wait_for_idle(void *handle) |
351 | { |
352 | unsigned i; |
353 | u32 tmp; |
354 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
355 | |
356 | for (i = 0; i < adev->usec_timeout; i++) { |
357 | /* read MC_STATUS */ |
358 | tmp = RREG32(mmSRBM_STATUS); |
359 | if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) |
360 | return 0; |
361 | udelay(1); |
362 | } |
363 | return -ETIMEDOUT; |
364 | } |
365 | |
366 | static int iceland_ih_soft_reset(void *handle) |
367 | { |
368 | u32 srbm_soft_reset = 0; |
369 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
370 | u32 tmp = RREG32(mmSRBM_STATUS); |
371 | |
372 | if (tmp & SRBM_STATUS__IH_BUSY_MASK) |
373 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, |
374 | SOFT_RESET_IH, 1); |
375 | |
376 | if (srbm_soft_reset) { |
377 | tmp = RREG32(mmSRBM_SOFT_RESET); |
378 | tmp |= srbm_soft_reset; |
379 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n" , tmp); |
380 | WREG32(mmSRBM_SOFT_RESET, tmp); |
381 | tmp = RREG32(mmSRBM_SOFT_RESET); |
382 | |
383 | udelay(50); |
384 | |
385 | tmp &= ~srbm_soft_reset; |
386 | WREG32(mmSRBM_SOFT_RESET, tmp); |
387 | tmp = RREG32(mmSRBM_SOFT_RESET); |
388 | |
389 | /* Wait a little for things to settle down */ |
390 | udelay(50); |
391 | } |
392 | |
393 | return 0; |
394 | } |
395 | |
396 | static int iceland_ih_set_clockgating_state(void *handle, |
397 | enum amd_clockgating_state state) |
398 | { |
399 | return 0; |
400 | } |
401 | |
402 | static int iceland_ih_set_powergating_state(void *handle, |
403 | enum amd_powergating_state state) |
404 | { |
405 | return 0; |
406 | } |
407 | |
408 | static const struct amd_ip_funcs iceland_ih_ip_funcs = { |
409 | .name = "iceland_ih" , |
410 | .early_init = iceland_ih_early_init, |
411 | .late_init = NULL, |
412 | .sw_init = iceland_ih_sw_init, |
413 | .sw_fini = iceland_ih_sw_fini, |
414 | .hw_init = iceland_ih_hw_init, |
415 | .hw_fini = iceland_ih_hw_fini, |
416 | .suspend = iceland_ih_suspend, |
417 | .resume = iceland_ih_resume, |
418 | .is_idle = iceland_ih_is_idle, |
419 | .wait_for_idle = iceland_ih_wait_for_idle, |
420 | .soft_reset = iceland_ih_soft_reset, |
421 | .set_clockgating_state = iceland_ih_set_clockgating_state, |
422 | .set_powergating_state = iceland_ih_set_powergating_state, |
423 | }; |
424 | |
425 | static const struct amdgpu_ih_funcs iceland_ih_funcs = { |
426 | .get_wptr = iceland_ih_get_wptr, |
427 | .decode_iv = iceland_ih_decode_iv, |
428 | .set_rptr = iceland_ih_set_rptr |
429 | }; |
430 | |
431 | static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev) |
432 | { |
433 | adev->irq.ih_funcs = &iceland_ih_funcs; |
434 | } |
435 | |
436 | const struct amdgpu_ip_block_version iceland_ih_ip_block = |
437 | { |
438 | .type = AMD_IP_BLOCK_TYPE_IH, |
439 | .major = 2, |
440 | .minor = 4, |
441 | .rev = 0, |
442 | .funcs = &iceland_ih_ip_funcs, |
443 | }; |
444 | |