1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "amdgpu.h" |
24 | #include "amdgpu_atombios.h" |
25 | #include "nbio_v7_0.h" |
26 | |
27 | #include "nbio/nbio_7_0_default.h" |
28 | #include "nbio/nbio_7_0_offset.h" |
29 | #include "nbio/nbio_7_0_sh_mask.h" |
30 | #include "nbio/nbio_7_0_smn.h" |
31 | #include "vega10_enum.h" |
32 | #include <uapi/linux/kfd_ioctl.h> |
33 | |
34 | #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c |
35 | |
36 | static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev) |
37 | { |
38 | WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, |
39 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); |
40 | WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, |
41 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); |
42 | } |
43 | |
44 | static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) |
45 | { |
46 | u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); |
47 | |
48 | tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; |
49 | tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; |
50 | |
51 | return tmp; |
52 | } |
53 | |
54 | static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) |
55 | { |
56 | if (enable) |
57 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, |
58 | BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); |
59 | else |
60 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); |
61 | } |
62 | |
63 | static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) |
64 | { |
65 | return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); |
66 | } |
67 | |
68 | static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, |
69 | bool use_doorbell, int doorbell_index, int doorbell_size) |
70 | { |
71 | u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : |
72 | SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); |
73 | |
74 | u32 doorbell_range = RREG32(reg); |
75 | |
76 | if (use_doorbell) { |
77 | doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); |
78 | doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); |
79 | } else |
80 | doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); |
81 | |
82 | WREG32(reg, doorbell_range); |
83 | } |
84 | |
85 | static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, |
86 | int doorbell_index, int instance) |
87 | { |
88 | u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); |
89 | |
90 | u32 doorbell_range = RREG32(reg); |
91 | |
92 | if (use_doorbell) { |
93 | doorbell_range = REG_SET_FIELD(doorbell_range, |
94 | BIF_MMSCH0_DOORBELL_RANGE, OFFSET, |
95 | doorbell_index); |
96 | doorbell_range = REG_SET_FIELD(doorbell_range, |
97 | BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); |
98 | } else |
99 | doorbell_range = REG_SET_FIELD(doorbell_range, |
100 | BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); |
101 | |
102 | WREG32(reg, doorbell_range); |
103 | } |
104 | |
105 | static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, |
106 | bool enable) |
107 | { |
108 | WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); |
109 | } |
110 | |
111 | static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, |
112 | bool enable) |
113 | { |
114 | |
115 | } |
116 | |
117 | static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, |
118 | bool use_doorbell, int doorbell_index) |
119 | { |
120 | u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); |
121 | |
122 | if (use_doorbell) { |
123 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); |
124 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); |
125 | } else |
126 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); |
127 | |
128 | WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); |
129 | } |
130 | |
131 | static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset) |
132 | { |
133 | uint32_t data; |
134 | |
135 | WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); |
136 | data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); |
137 | |
138 | return data; |
139 | } |
140 | |
141 | static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset, |
142 | uint32_t data) |
143 | { |
144 | WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); |
145 | WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); |
146 | } |
147 | |
148 | static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
149 | bool enable) |
150 | { |
151 | uint32_t def, data; |
152 | |
153 | /* NBIF_MGCG_CTRL_LCLK */ |
154 | def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); |
155 | |
156 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) |
157 | data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; |
158 | else |
159 | data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; |
160 | |
161 | if (def != data) |
162 | WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); |
163 | |
164 | /* SYSHUB_MGCG_CTRL_SOCCLK */ |
165 | def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK); |
166 | |
167 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) |
168 | data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; |
169 | else |
170 | data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; |
171 | |
172 | if (def != data) |
173 | nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data); |
174 | |
175 | /* SYSHUB_MGCG_CTRL_SHUBCLK */ |
176 | def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK); |
177 | |
178 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) |
179 | data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; |
180 | else |
181 | data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; |
182 | |
183 | if (def != data) |
184 | nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data); |
185 | } |
186 | |
187 | static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
188 | bool enable) |
189 | { |
190 | uint32_t def, data; |
191 | |
192 | def = data = RREG32_PCIE(smnPCIE_CNTL2); |
193 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { |
194 | data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | |
195 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | |
196 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); |
197 | } else { |
198 | data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | |
199 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | |
200 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); |
201 | } |
202 | |
203 | if (def != data) |
204 | WREG32_PCIE(smnPCIE_CNTL2, data); |
205 | } |
206 | |
207 | static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev, |
208 | u64 *flags) |
209 | { |
210 | int data; |
211 | |
212 | /* AMD_CG_SUPPORT_BIF_MGCG */ |
213 | data = RREG32_PCIE(smnCPM_CONTROL); |
214 | if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) |
215 | *flags |= AMD_CG_SUPPORT_BIF_MGCG; |
216 | |
217 | /* AMD_CG_SUPPORT_BIF_LS */ |
218 | data = RREG32_PCIE(smnPCIE_CNTL2); |
219 | if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) |
220 | *flags |= AMD_CG_SUPPORT_BIF_LS; |
221 | } |
222 | |
223 | static void nbio_v7_0_ih_control(struct amdgpu_device *adev) |
224 | { |
225 | u32 interrupt_cntl; |
226 | |
227 | /* setup interrupt control */ |
228 | WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); |
229 | interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); |
230 | /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi |
231 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN |
232 | */ |
233 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); |
234 | /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ |
235 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); |
236 | WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); |
237 | } |
238 | |
239 | static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) |
240 | { |
241 | return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); |
242 | } |
243 | |
244 | static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) |
245 | { |
246 | return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); |
247 | } |
248 | |
249 | static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) |
250 | { |
251 | return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); |
252 | } |
253 | |
254 | static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) |
255 | { |
256 | return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); |
257 | } |
258 | |
259 | const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { |
260 | .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, |
261 | .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, |
262 | .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, |
263 | .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, |
264 | .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, |
265 | .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, |
266 | .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, |
267 | .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, |
268 | .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, |
269 | .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, |
270 | .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, |
271 | .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, |
272 | }; |
273 | |
274 | static void nbio_v7_0_init_registers(struct amdgpu_device *adev) |
275 | { |
276 | if (amdgpu_sriov_vf(adev)) |
277 | adev->rmmio_remap.reg_offset = |
278 | SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2; |
279 | } |
280 | |
281 | const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { |
282 | .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, |
283 | .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, |
284 | .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, |
285 | .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, |
286 | .get_rev_id = nbio_v7_0_get_rev_id, |
287 | .mc_access_enable = nbio_v7_0_mc_access_enable, |
288 | .get_memsize = nbio_v7_0_get_memsize, |
289 | .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range, |
290 | .vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range, |
291 | .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture, |
292 | .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture, |
293 | .ih_doorbell_range = nbio_v7_0_ih_doorbell_range, |
294 | .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating, |
295 | .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep, |
296 | .get_clockgating_state = nbio_v7_0_get_clockgating_state, |
297 | .ih_control = nbio_v7_0_ih_control, |
298 | .init_registers = nbio_v7_0_init_registers, |
299 | .remap_hdp_registers = nbio_v7_0_remap_hdp_registers, |
300 | }; |
301 | |