1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: Alex Deucher |
23 | */ |
24 | |
25 | #include <linux/delay.h> |
26 | #include <linux/firmware.h> |
27 | #include <linux/module.h> |
28 | |
29 | #include "amdgpu.h" |
30 | #include "amdgpu_ucode.h" |
31 | #include "amdgpu_trace.h" |
32 | #include "vi.h" |
33 | #include "vid.h" |
34 | |
35 | #include "oss/oss_2_4_d.h" |
36 | #include "oss/oss_2_4_sh_mask.h" |
37 | |
38 | #include "gmc/gmc_7_1_d.h" |
39 | #include "gmc/gmc_7_1_sh_mask.h" |
40 | |
41 | #include "gca/gfx_8_0_d.h" |
42 | #include "gca/gfx_8_0_enum.h" |
43 | #include "gca/gfx_8_0_sh_mask.h" |
44 | |
45 | #include "bif/bif_5_0_d.h" |
46 | #include "bif/bif_5_0_sh_mask.h" |
47 | |
48 | #include "iceland_sdma_pkt_open.h" |
49 | |
50 | #include "ivsrcid/ivsrcid_vislands30.h" |
51 | |
52 | static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); |
53 | static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); |
54 | static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); |
55 | static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); |
56 | |
57 | MODULE_FIRMWARE("amdgpu/topaz_sdma.bin" ); |
58 | MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin" ); |
59 | |
60 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = |
61 | { |
62 | SDMA0_REGISTER_OFFSET, |
63 | SDMA1_REGISTER_OFFSET |
64 | }; |
65 | |
66 | static const u32 golden_settings_iceland_a11[] = |
67 | { |
68 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, |
69 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, |
70 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, |
71 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, |
72 | }; |
73 | |
74 | static const u32 iceland_mgcg_cgcg_init[] = |
75 | { |
76 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, |
77 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 |
78 | }; |
79 | |
80 | /* |
81 | * sDMA - System DMA |
82 | * Starting with CIK, the GPU has new asynchronous |
83 | * DMA engines. These engines are used for compute |
84 | * and gfx. There are two DMA engines (SDMA0, SDMA1) |
85 | * and each one supports 1 ring buffer used for gfx |
86 | * and 2 queues used for compute. |
87 | * |
88 | * The programming model is very similar to the CP |
89 | * (ring buffer, IBs, etc.), but sDMA has it's own |
90 | * packet format that is different from the PM4 format |
91 | * used by the CP. sDMA supports copying data, writing |
92 | * embedded data, solid fills, and a number of other |
93 | * things. It also has support for tiling/detiling of |
94 | * buffers. |
95 | */ |
96 | |
97 | static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) |
98 | { |
99 | switch (adev->asic_type) { |
100 | case CHIP_TOPAZ: |
101 | amdgpu_device_program_register_sequence(adev, |
102 | registers: iceland_mgcg_cgcg_init, |
103 | ARRAY_SIZE(iceland_mgcg_cgcg_init)); |
104 | amdgpu_device_program_register_sequence(adev, |
105 | registers: golden_settings_iceland_a11, |
106 | ARRAY_SIZE(golden_settings_iceland_a11)); |
107 | break; |
108 | default: |
109 | break; |
110 | } |
111 | } |
112 | |
113 | static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) |
114 | { |
115 | int i; |
116 | |
117 | for (i = 0; i < adev->sdma.num_instances; i++) |
118 | amdgpu_ucode_release(fw: &adev->sdma.instance[i].fw); |
119 | } |
120 | |
121 | /** |
122 | * sdma_v2_4_init_microcode - load ucode images from disk |
123 | * |
124 | * @adev: amdgpu_device pointer |
125 | * |
126 | * Use the firmware interface to load the ucode images into |
127 | * the driver (not loaded into hw). |
128 | * Returns 0 on success, error on failure. |
129 | */ |
130 | static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) |
131 | { |
132 | const char *chip_name; |
133 | char fw_name[30]; |
134 | int err = 0, i; |
135 | struct amdgpu_firmware_info *info = NULL; |
136 | const struct common_firmware_header * = NULL; |
137 | const struct sdma_firmware_header_v1_0 *hdr; |
138 | |
139 | DRM_DEBUG("\n" ); |
140 | |
141 | switch (adev->asic_type) { |
142 | case CHIP_TOPAZ: |
143 | chip_name = "topaz" ; |
144 | break; |
145 | default: BUG(); |
146 | } |
147 | |
148 | for (i = 0; i < adev->sdma.num_instances; i++) { |
149 | if (i == 0) |
150 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_sdma.bin" , chip_name); |
151 | else |
152 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_sdma1.bin" , chip_name); |
153 | err = amdgpu_ucode_request(adev, fw: &adev->sdma.instance[i].fw, fw_name); |
154 | if (err) |
155 | goto out; |
156 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
157 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); |
158 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); |
159 | if (adev->sdma.instance[i].feature_version >= 20) |
160 | adev->sdma.instance[i].burst_nop = true; |
161 | |
162 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { |
163 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; |
164 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; |
165 | info->fw = adev->sdma.instance[i].fw; |
166 | header = (const struct common_firmware_header *)info->fw->data; |
167 | adev->firmware.fw_size += |
168 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
169 | } |
170 | } |
171 | |
172 | out: |
173 | if (err) { |
174 | pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n" , fw_name); |
175 | for (i = 0; i < adev->sdma.num_instances; i++) |
176 | amdgpu_ucode_release(fw: &adev->sdma.instance[i].fw); |
177 | } |
178 | return err; |
179 | } |
180 | |
181 | /** |
182 | * sdma_v2_4_ring_get_rptr - get the current read pointer |
183 | * |
184 | * @ring: amdgpu ring pointer |
185 | * |
186 | * Get the current rptr from the hardware (VI+). |
187 | */ |
188 | static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) |
189 | { |
190 | /* XXX check if swapping is necessary on BE */ |
191 | return *ring->rptr_cpu_addr >> 2; |
192 | } |
193 | |
194 | /** |
195 | * sdma_v2_4_ring_get_wptr - get the current write pointer |
196 | * |
197 | * @ring: amdgpu ring pointer |
198 | * |
199 | * Get the current wptr from the hardware (VI+). |
200 | */ |
201 | static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) |
202 | { |
203 | struct amdgpu_device *adev = ring->adev; |
204 | u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; |
205 | |
206 | return wptr; |
207 | } |
208 | |
209 | /** |
210 | * sdma_v2_4_ring_set_wptr - commit the write pointer |
211 | * |
212 | * @ring: amdgpu ring pointer |
213 | * |
214 | * Write the wptr back to the hardware (VI+). |
215 | */ |
216 | static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) |
217 | { |
218 | struct amdgpu_device *adev = ring->adev; |
219 | |
220 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); |
221 | } |
222 | |
223 | static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
224 | { |
225 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
226 | int i; |
227 | |
228 | for (i = 0; i < count; i++) |
229 | if (sdma && sdma->burst_nop && (i == 0)) |
230 | amdgpu_ring_write(ring, v: ring->funcs->nop | |
231 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); |
232 | else |
233 | amdgpu_ring_write(ring, v: ring->funcs->nop); |
234 | } |
235 | |
236 | /** |
237 | * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine |
238 | * |
239 | * @ring: amdgpu ring pointer |
240 | * @job: job to retrieve vmid from |
241 | * @ib: IB object to schedule |
242 | * @flags: unused |
243 | * |
244 | * Schedule an IB in the DMA ring (VI). |
245 | */ |
246 | static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, |
247 | struct amdgpu_job *job, |
248 | struct amdgpu_ib *ib, |
249 | uint32_t flags) |
250 | { |
251 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
252 | |
253 | /* IB packet must end on a 8 DW boundary */ |
254 | sdma_v2_4_ring_insert_nop(ring, count: (2 - lower_32_bits(ring->wptr)) & 7); |
255 | |
256 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | |
257 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); |
258 | /* base must be 32 byte aligned */ |
259 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); |
260 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
261 | amdgpu_ring_write(ring, v: ib->length_dw); |
262 | amdgpu_ring_write(ring, v: 0); |
263 | amdgpu_ring_write(ring, v: 0); |
264 | |
265 | } |
266 | |
267 | /** |
268 | * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
269 | * |
270 | * @ring: amdgpu ring pointer |
271 | * |
272 | * Emit an hdp flush packet on the requested DMA ring. |
273 | */ |
274 | static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
275 | { |
276 | u32 ref_and_mask = 0; |
277 | |
278 | if (ring->me == 0) |
279 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); |
280 | else |
281 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); |
282 | |
283 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | |
284 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | |
285 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ |
286 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); |
287 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); |
288 | amdgpu_ring_write(ring, v: ref_and_mask); /* reference */ |
289 | amdgpu_ring_write(ring, v: ref_and_mask); /* mask */ |
290 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | |
291 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ |
292 | } |
293 | |
294 | /** |
295 | * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring |
296 | * |
297 | * @ring: amdgpu ring pointer |
298 | * @addr: address |
299 | * @seq: sequence number |
300 | * @flags: fence related flags |
301 | * |
302 | * Add a DMA fence packet to the ring to write |
303 | * the fence seq number and DMA trap packet to generate |
304 | * an interrupt if needed (VI). |
305 | */ |
306 | static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
307 | unsigned flags) |
308 | { |
309 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
310 | /* write the fence */ |
311 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); |
312 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
313 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
314 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
315 | |
316 | /* optionally write high bits as well */ |
317 | if (write64bit) { |
318 | addr += 4; |
319 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); |
320 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
321 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
322 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
323 | } |
324 | |
325 | /* generate an interrupt */ |
326 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); |
327 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); |
328 | } |
329 | |
330 | /** |
331 | * sdma_v2_4_gfx_stop - stop the gfx async dma engines |
332 | * |
333 | * @adev: amdgpu_device pointer |
334 | * |
335 | * Stop the gfx async dma ring buffers (VI). |
336 | */ |
337 | static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) |
338 | { |
339 | u32 rb_cntl, ib_cntl; |
340 | int i; |
341 | |
342 | for (i = 0; i < adev->sdma.num_instances; i++) { |
343 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
344 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); |
345 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); |
346 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); |
347 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); |
348 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); |
349 | } |
350 | } |
351 | |
352 | /** |
353 | * sdma_v2_4_rlc_stop - stop the compute async dma engines |
354 | * |
355 | * @adev: amdgpu_device pointer |
356 | * |
357 | * Stop the compute async dma queues (VI). |
358 | */ |
359 | static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) |
360 | { |
361 | /* XXX todo */ |
362 | } |
363 | |
364 | /** |
365 | * sdma_v2_4_enable - stop the async dma engines |
366 | * |
367 | * @adev: amdgpu_device pointer |
368 | * @enable: enable/disable the DMA MEs. |
369 | * |
370 | * Halt or unhalt the async dma engines (VI). |
371 | */ |
372 | static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) |
373 | { |
374 | u32 f32_cntl; |
375 | int i; |
376 | |
377 | if (!enable) { |
378 | sdma_v2_4_gfx_stop(adev); |
379 | sdma_v2_4_rlc_stop(adev); |
380 | } |
381 | |
382 | for (i = 0; i < adev->sdma.num_instances; i++) { |
383 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
384 | if (enable) |
385 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); |
386 | else |
387 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); |
388 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); |
389 | } |
390 | } |
391 | |
392 | /** |
393 | * sdma_v2_4_gfx_resume - setup and start the async dma engines |
394 | * |
395 | * @adev: amdgpu_device pointer |
396 | * |
397 | * Set up the gfx DMA ring buffers and enable them (VI). |
398 | * Returns 0 for success, error for failure. |
399 | */ |
400 | static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) |
401 | { |
402 | struct amdgpu_ring *ring; |
403 | u32 rb_cntl, ib_cntl; |
404 | u32 rb_bufsz; |
405 | int i, j, r; |
406 | |
407 | for (i = 0; i < adev->sdma.num_instances; i++) { |
408 | ring = &adev->sdma.instance[i].ring; |
409 | |
410 | mutex_lock(&adev->srbm_mutex); |
411 | for (j = 0; j < 16; j++) { |
412 | vi_srbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: j); |
413 | /* SDMA GFX */ |
414 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); |
415 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); |
416 | } |
417 | vi_srbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
418 | mutex_unlock(lock: &adev->srbm_mutex); |
419 | |
420 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
421 | adev->gfx.config.gb_addr_config & 0x70); |
422 | |
423 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
424 | |
425 | /* Set ring buffer size in dwords */ |
426 | rb_bufsz = order_base_2(ring->ring_size / 4); |
427 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
428 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); |
429 | #ifdef __BIG_ENDIAN |
430 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); |
431 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, |
432 | RPTR_WRITEBACK_SWAP_ENABLE, 1); |
433 | #endif |
434 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); |
435 | |
436 | /* Initialize the ring buffer's read and write pointers */ |
437 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); |
438 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); |
439 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
440 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); |
441 | |
442 | /* set the wb address whether it's enabled or not */ |
443 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], |
444 | upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); |
445 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], |
446 | lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); |
447 | |
448 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); |
449 | |
450 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); |
451 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); |
452 | |
453 | ring->wptr = 0; |
454 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); |
455 | |
456 | /* enable DMA RB */ |
457 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); |
458 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); |
459 | |
460 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); |
461 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); |
462 | #ifdef __BIG_ENDIAN |
463 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); |
464 | #endif |
465 | /* enable DMA IBs */ |
466 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); |
467 | } |
468 | |
469 | sdma_v2_4_enable(adev, enable: true); |
470 | for (i = 0; i < adev->sdma.num_instances; i++) { |
471 | ring = &adev->sdma.instance[i].ring; |
472 | r = amdgpu_ring_test_helper(ring); |
473 | if (r) |
474 | return r; |
475 | } |
476 | |
477 | return 0; |
478 | } |
479 | |
480 | /** |
481 | * sdma_v2_4_rlc_resume - setup and start the async dma engines |
482 | * |
483 | * @adev: amdgpu_device pointer |
484 | * |
485 | * Set up the compute DMA queues and enable them (VI). |
486 | * Returns 0 for success, error for failure. |
487 | */ |
488 | static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) |
489 | { |
490 | /* XXX todo */ |
491 | return 0; |
492 | } |
493 | |
494 | |
495 | /** |
496 | * sdma_v2_4_start - setup and start the async dma engines |
497 | * |
498 | * @adev: amdgpu_device pointer |
499 | * |
500 | * Set up the DMA engines and enable them (VI). |
501 | * Returns 0 for success, error for failure. |
502 | */ |
503 | static int sdma_v2_4_start(struct amdgpu_device *adev) |
504 | { |
505 | int r; |
506 | |
507 | /* halt the engine before programing */ |
508 | sdma_v2_4_enable(adev, enable: false); |
509 | |
510 | /* start the gfx rings and rlc compute queues */ |
511 | r = sdma_v2_4_gfx_resume(adev); |
512 | if (r) |
513 | return r; |
514 | r = sdma_v2_4_rlc_resume(adev); |
515 | if (r) |
516 | return r; |
517 | |
518 | return 0; |
519 | } |
520 | |
521 | /** |
522 | * sdma_v2_4_ring_test_ring - simple async dma engine test |
523 | * |
524 | * @ring: amdgpu_ring structure holding ring information |
525 | * |
526 | * Test the DMA engine by writing using it to write an |
527 | * value to memory. (VI). |
528 | * Returns 0 for success, error for failure. |
529 | */ |
530 | static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) |
531 | { |
532 | struct amdgpu_device *adev = ring->adev; |
533 | unsigned i; |
534 | unsigned index; |
535 | int r; |
536 | u32 tmp; |
537 | u64 gpu_addr; |
538 | |
539 | r = amdgpu_device_wb_get(adev, wb: &index); |
540 | if (r) |
541 | return r; |
542 | |
543 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
544 | tmp = 0xCAFEDEAD; |
545 | adev->wb.wb[index] = cpu_to_le32(tmp); |
546 | |
547 | r = amdgpu_ring_alloc(ring, ndw: 5); |
548 | if (r) |
549 | goto error_free_wb; |
550 | |
551 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | |
552 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); |
553 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); |
554 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); |
555 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); |
556 | amdgpu_ring_write(ring, v: 0xDEADBEEF); |
557 | amdgpu_ring_commit(ring); |
558 | |
559 | for (i = 0; i < adev->usec_timeout; i++) { |
560 | tmp = le32_to_cpu(adev->wb.wb[index]); |
561 | if (tmp == 0xDEADBEEF) |
562 | break; |
563 | udelay(1); |
564 | } |
565 | |
566 | if (i >= adev->usec_timeout) |
567 | r = -ETIMEDOUT; |
568 | |
569 | error_free_wb: |
570 | amdgpu_device_wb_free(adev, wb: index); |
571 | return r; |
572 | } |
573 | |
574 | /** |
575 | * sdma_v2_4_ring_test_ib - test an IB on the DMA engine |
576 | * |
577 | * @ring: amdgpu_ring structure holding ring information |
578 | * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT |
579 | * |
580 | * Test a simple IB in the DMA ring (VI). |
581 | * Returns 0 on success, error on failure. |
582 | */ |
583 | static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
584 | { |
585 | struct amdgpu_device *adev = ring->adev; |
586 | struct amdgpu_ib ib; |
587 | struct dma_fence *f = NULL; |
588 | unsigned index; |
589 | u32 tmp = 0; |
590 | u64 gpu_addr; |
591 | long r; |
592 | |
593 | r = amdgpu_device_wb_get(adev, wb: &index); |
594 | if (r) |
595 | return r; |
596 | |
597 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
598 | tmp = 0xCAFEDEAD; |
599 | adev->wb.wb[index] = cpu_to_le32(tmp); |
600 | memset(&ib, 0, sizeof(ib)); |
601 | r = amdgpu_ib_get(adev, NULL, size: 256, |
602 | pool: AMDGPU_IB_POOL_DIRECT, ib: &ib); |
603 | if (r) |
604 | goto err0; |
605 | |
606 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | |
607 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); |
608 | ib.ptr[1] = lower_32_bits(gpu_addr); |
609 | ib.ptr[2] = upper_32_bits(gpu_addr); |
610 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); |
611 | ib.ptr[4] = 0xDEADBEEF; |
612 | ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); |
613 | ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); |
614 | ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); |
615 | ib.length_dw = 8; |
616 | |
617 | r = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: &ib, NULL, f: &f); |
618 | if (r) |
619 | goto err1; |
620 | |
621 | r = dma_fence_wait_timeout(f, intr: false, timeout); |
622 | if (r == 0) { |
623 | r = -ETIMEDOUT; |
624 | goto err1; |
625 | } else if (r < 0) { |
626 | goto err1; |
627 | } |
628 | tmp = le32_to_cpu(adev->wb.wb[index]); |
629 | if (tmp == 0xDEADBEEF) |
630 | r = 0; |
631 | else |
632 | r = -EINVAL; |
633 | |
634 | err1: |
635 | amdgpu_ib_free(adev, ib: &ib, NULL); |
636 | dma_fence_put(fence: f); |
637 | err0: |
638 | amdgpu_device_wb_free(adev, wb: index); |
639 | return r; |
640 | } |
641 | |
642 | /** |
643 | * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART |
644 | * |
645 | * @ib: indirect buffer to fill with commands |
646 | * @pe: addr of the page entry |
647 | * @src: src addr to copy from |
648 | * @count: number of page entries to update |
649 | * |
650 | * Update PTEs by copying them from the GART using sDMA (CIK). |
651 | */ |
652 | static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, |
653 | uint64_t pe, uint64_t src, |
654 | unsigned count) |
655 | { |
656 | unsigned bytes = count * 8; |
657 | |
658 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
659 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); |
660 | ib->ptr[ib->length_dw++] = bytes; |
661 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
662 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
663 | ib->ptr[ib->length_dw++] = upper_32_bits(src); |
664 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
665 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
666 | } |
667 | |
668 | /** |
669 | * sdma_v2_4_vm_write_pte - update PTEs by writing them manually |
670 | * |
671 | * @ib: indirect buffer to fill with commands |
672 | * @pe: addr of the page entry |
673 | * @value: dst addr to write into pe |
674 | * @count: number of page entries to update |
675 | * @incr: increase next addr by incr bytes |
676 | * |
677 | * Update PTEs by writing them manually using sDMA (CIK). |
678 | */ |
679 | static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
680 | uint64_t value, unsigned count, |
681 | uint32_t incr) |
682 | { |
683 | unsigned ndw = count * 2; |
684 | |
685 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | |
686 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); |
687 | ib->ptr[ib->length_dw++] = pe; |
688 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
689 | ib->ptr[ib->length_dw++] = ndw; |
690 | for (; ndw > 0; ndw -= 2) { |
691 | ib->ptr[ib->length_dw++] = lower_32_bits(value); |
692 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
693 | value += incr; |
694 | } |
695 | } |
696 | |
697 | /** |
698 | * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA |
699 | * |
700 | * @ib: indirect buffer to fill with commands |
701 | * @pe: addr of the page entry |
702 | * @addr: dst addr to write into pe |
703 | * @count: number of page entries to update |
704 | * @incr: increase next addr by incr bytes |
705 | * @flags: access flags |
706 | * |
707 | * Update the page tables using sDMA (CIK). |
708 | */ |
709 | static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
710 | uint64_t addr, unsigned count, |
711 | uint32_t incr, uint64_t flags) |
712 | { |
713 | /* for physically contiguous pages (vram) */ |
714 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); |
715 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ |
716 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
717 | ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ |
718 | ib->ptr[ib->length_dw++] = upper_32_bits(flags); |
719 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ |
720 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); |
721 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
722 | ib->ptr[ib->length_dw++] = 0; |
723 | ib->ptr[ib->length_dw++] = count; /* number of entries */ |
724 | } |
725 | |
726 | /** |
727 | * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw |
728 | * |
729 | * @ring: amdgpu_ring structure holding ring information |
730 | * @ib: indirect buffer to fill with padding |
731 | * |
732 | */ |
733 | static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
734 | { |
735 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
736 | u32 pad_count; |
737 | int i; |
738 | |
739 | pad_count = (-ib->length_dw) & 7; |
740 | for (i = 0; i < pad_count; i++) |
741 | if (sdma && sdma->burst_nop && (i == 0)) |
742 | ib->ptr[ib->length_dw++] = |
743 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | |
744 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); |
745 | else |
746 | ib->ptr[ib->length_dw++] = |
747 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP); |
748 | } |
749 | |
750 | /** |
751 | * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline |
752 | * |
753 | * @ring: amdgpu_ring pointer |
754 | * |
755 | * Make sure all previous operations are completed (CIK). |
756 | */ |
757 | static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
758 | { |
759 | uint32_t seq = ring->fence_drv.sync_seq; |
760 | uint64_t addr = ring->fence_drv.gpu_addr; |
761 | |
762 | /* wait for idle */ |
763 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | |
764 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | |
765 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ |
766 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); |
767 | amdgpu_ring_write(ring, v: addr & 0xfffffffc); |
768 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); |
769 | amdgpu_ring_write(ring, v: seq); /* reference */ |
770 | amdgpu_ring_write(ring, v: 0xffffffff); /* mask */ |
771 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | |
772 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ |
773 | } |
774 | |
775 | /** |
776 | * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA |
777 | * |
778 | * @ring: amdgpu_ring pointer |
779 | * @vmid: vmid number to use |
780 | * @pd_addr: address |
781 | * |
782 | * Update the page table base and flush the VM TLB |
783 | * using sDMA (VI). |
784 | */ |
785 | static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, |
786 | unsigned vmid, uint64_t pd_addr) |
787 | { |
788 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
789 | |
790 | /* wait for flush */ |
791 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | |
792 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | |
793 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ |
794 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); |
795 | amdgpu_ring_write(ring, v: 0); |
796 | amdgpu_ring_write(ring, v: 0); /* reference */ |
797 | amdgpu_ring_write(ring, v: 0); /* mask */ |
798 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | |
799 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ |
800 | } |
801 | |
802 | static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, |
803 | uint32_t reg, uint32_t val) |
804 | { |
805 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | |
806 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); |
807 | amdgpu_ring_write(ring, v: reg); |
808 | amdgpu_ring_write(ring, v: val); |
809 | } |
810 | |
811 | static int sdma_v2_4_early_init(void *handle) |
812 | { |
813 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
814 | int r; |
815 | |
816 | r = sdma_v2_4_init_microcode(adev); |
817 | if (r) |
818 | return r; |
819 | |
820 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
821 | |
822 | sdma_v2_4_set_ring_funcs(adev); |
823 | sdma_v2_4_set_buffer_funcs(adev); |
824 | sdma_v2_4_set_vm_pte_funcs(adev); |
825 | sdma_v2_4_set_irq_funcs(adev); |
826 | |
827 | return 0; |
828 | } |
829 | |
830 | static int sdma_v2_4_sw_init(void *handle) |
831 | { |
832 | struct amdgpu_ring *ring; |
833 | int r, i; |
834 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
835 | |
836 | /* SDMA trap event */ |
837 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, |
838 | source: &adev->sdma.trap_irq); |
839 | if (r) |
840 | return r; |
841 | |
842 | /* SDMA Privileged inst */ |
843 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: 241, |
844 | source: &adev->sdma.illegal_inst_irq); |
845 | if (r) |
846 | return r; |
847 | |
848 | /* SDMA Privileged inst */ |
849 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, |
850 | source: &adev->sdma.illegal_inst_irq); |
851 | if (r) |
852 | return r; |
853 | |
854 | for (i = 0; i < adev->sdma.num_instances; i++) { |
855 | ring = &adev->sdma.instance[i].ring; |
856 | ring->ring_obj = NULL; |
857 | ring->use_doorbell = false; |
858 | sprintf(buf: ring->name, fmt: "sdma%d" , i); |
859 | r = amdgpu_ring_init(adev, ring, max_dw: 1024, irq_src: &adev->sdma.trap_irq, |
860 | irq_type: (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : |
861 | AMDGPU_SDMA_IRQ_INSTANCE1, |
862 | hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL); |
863 | if (r) |
864 | return r; |
865 | } |
866 | |
867 | return r; |
868 | } |
869 | |
870 | static int sdma_v2_4_sw_fini(void *handle) |
871 | { |
872 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
873 | int i; |
874 | |
875 | for (i = 0; i < adev->sdma.num_instances; i++) |
876 | amdgpu_ring_fini(ring: &adev->sdma.instance[i].ring); |
877 | |
878 | sdma_v2_4_free_microcode(adev); |
879 | return 0; |
880 | } |
881 | |
882 | static int sdma_v2_4_hw_init(void *handle) |
883 | { |
884 | int r; |
885 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
886 | |
887 | sdma_v2_4_init_golden_registers(adev); |
888 | |
889 | r = sdma_v2_4_start(adev); |
890 | if (r) |
891 | return r; |
892 | |
893 | return r; |
894 | } |
895 | |
896 | static int sdma_v2_4_hw_fini(void *handle) |
897 | { |
898 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
899 | |
900 | sdma_v2_4_enable(adev, enable: false); |
901 | |
902 | return 0; |
903 | } |
904 | |
905 | static int sdma_v2_4_suspend(void *handle) |
906 | { |
907 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
908 | |
909 | return sdma_v2_4_hw_fini(handle: adev); |
910 | } |
911 | |
912 | static int sdma_v2_4_resume(void *handle) |
913 | { |
914 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
915 | |
916 | return sdma_v2_4_hw_init(handle: adev); |
917 | } |
918 | |
919 | static bool sdma_v2_4_is_idle(void *handle) |
920 | { |
921 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
922 | u32 tmp = RREG32(mmSRBM_STATUS2); |
923 | |
924 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | |
925 | SRBM_STATUS2__SDMA1_BUSY_MASK)) |
926 | return false; |
927 | |
928 | return true; |
929 | } |
930 | |
931 | static int sdma_v2_4_wait_for_idle(void *handle) |
932 | { |
933 | unsigned i; |
934 | u32 tmp; |
935 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
936 | |
937 | for (i = 0; i < adev->usec_timeout; i++) { |
938 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | |
939 | SRBM_STATUS2__SDMA1_BUSY_MASK); |
940 | |
941 | if (!tmp) |
942 | return 0; |
943 | udelay(1); |
944 | } |
945 | return -ETIMEDOUT; |
946 | } |
947 | |
948 | static int sdma_v2_4_soft_reset(void *handle) |
949 | { |
950 | u32 srbm_soft_reset = 0; |
951 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
952 | u32 tmp = RREG32(mmSRBM_STATUS2); |
953 | |
954 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { |
955 | /* sdma0 */ |
956 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); |
957 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); |
958 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); |
959 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; |
960 | } |
961 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { |
962 | /* sdma1 */ |
963 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); |
964 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); |
965 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); |
966 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; |
967 | } |
968 | |
969 | if (srbm_soft_reset) { |
970 | tmp = RREG32(mmSRBM_SOFT_RESET); |
971 | tmp |= srbm_soft_reset; |
972 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n" , tmp); |
973 | WREG32(mmSRBM_SOFT_RESET, tmp); |
974 | tmp = RREG32(mmSRBM_SOFT_RESET); |
975 | |
976 | udelay(50); |
977 | |
978 | tmp &= ~srbm_soft_reset; |
979 | WREG32(mmSRBM_SOFT_RESET, tmp); |
980 | tmp = RREG32(mmSRBM_SOFT_RESET); |
981 | |
982 | /* Wait a little for things to settle down */ |
983 | udelay(50); |
984 | } |
985 | |
986 | return 0; |
987 | } |
988 | |
989 | static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, |
990 | struct amdgpu_irq_src *src, |
991 | unsigned type, |
992 | enum amdgpu_interrupt_state state) |
993 | { |
994 | u32 sdma_cntl; |
995 | |
996 | switch (type) { |
997 | case AMDGPU_SDMA_IRQ_INSTANCE0: |
998 | switch (state) { |
999 | case AMDGPU_IRQ_STATE_DISABLE: |
1000 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); |
1001 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); |
1002 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); |
1003 | break; |
1004 | case AMDGPU_IRQ_STATE_ENABLE: |
1005 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); |
1006 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); |
1007 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); |
1008 | break; |
1009 | default: |
1010 | break; |
1011 | } |
1012 | break; |
1013 | case AMDGPU_SDMA_IRQ_INSTANCE1: |
1014 | switch (state) { |
1015 | case AMDGPU_IRQ_STATE_DISABLE: |
1016 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); |
1017 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); |
1018 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); |
1019 | break; |
1020 | case AMDGPU_IRQ_STATE_ENABLE: |
1021 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); |
1022 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); |
1023 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); |
1024 | break; |
1025 | default: |
1026 | break; |
1027 | } |
1028 | break; |
1029 | default: |
1030 | break; |
1031 | } |
1032 | return 0; |
1033 | } |
1034 | |
1035 | static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, |
1036 | struct amdgpu_irq_src *source, |
1037 | struct amdgpu_iv_entry *entry) |
1038 | { |
1039 | u8 instance_id, queue_id; |
1040 | |
1041 | instance_id = (entry->ring_id & 0x3) >> 0; |
1042 | queue_id = (entry->ring_id & 0xc) >> 2; |
1043 | DRM_DEBUG("IH: SDMA trap\n" ); |
1044 | switch (instance_id) { |
1045 | case 0: |
1046 | switch (queue_id) { |
1047 | case 0: |
1048 | amdgpu_fence_process(ring: &adev->sdma.instance[0].ring); |
1049 | break; |
1050 | case 1: |
1051 | /* XXX compute */ |
1052 | break; |
1053 | case 2: |
1054 | /* XXX compute */ |
1055 | break; |
1056 | } |
1057 | break; |
1058 | case 1: |
1059 | switch (queue_id) { |
1060 | case 0: |
1061 | amdgpu_fence_process(ring: &adev->sdma.instance[1].ring); |
1062 | break; |
1063 | case 1: |
1064 | /* XXX compute */ |
1065 | break; |
1066 | case 2: |
1067 | /* XXX compute */ |
1068 | break; |
1069 | } |
1070 | break; |
1071 | } |
1072 | return 0; |
1073 | } |
1074 | |
1075 | static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, |
1076 | struct amdgpu_irq_src *source, |
1077 | struct amdgpu_iv_entry *entry) |
1078 | { |
1079 | u8 instance_id, queue_id; |
1080 | |
1081 | DRM_ERROR("Illegal instruction in SDMA command stream\n" ); |
1082 | instance_id = (entry->ring_id & 0x3) >> 0; |
1083 | queue_id = (entry->ring_id & 0xc) >> 2; |
1084 | |
1085 | if (instance_id <= 1 && queue_id == 0) |
1086 | drm_sched_fault(sched: &adev->sdma.instance[instance_id].ring.sched); |
1087 | return 0; |
1088 | } |
1089 | |
1090 | static int sdma_v2_4_set_clockgating_state(void *handle, |
1091 | enum amd_clockgating_state state) |
1092 | { |
1093 | /* XXX handled via the smc on VI */ |
1094 | return 0; |
1095 | } |
1096 | |
1097 | static int sdma_v2_4_set_powergating_state(void *handle, |
1098 | enum amd_powergating_state state) |
1099 | { |
1100 | return 0; |
1101 | } |
1102 | |
1103 | static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { |
1104 | .name = "sdma_v2_4" , |
1105 | .early_init = sdma_v2_4_early_init, |
1106 | .late_init = NULL, |
1107 | .sw_init = sdma_v2_4_sw_init, |
1108 | .sw_fini = sdma_v2_4_sw_fini, |
1109 | .hw_init = sdma_v2_4_hw_init, |
1110 | .hw_fini = sdma_v2_4_hw_fini, |
1111 | .suspend = sdma_v2_4_suspend, |
1112 | .resume = sdma_v2_4_resume, |
1113 | .is_idle = sdma_v2_4_is_idle, |
1114 | .wait_for_idle = sdma_v2_4_wait_for_idle, |
1115 | .soft_reset = sdma_v2_4_soft_reset, |
1116 | .set_clockgating_state = sdma_v2_4_set_clockgating_state, |
1117 | .set_powergating_state = sdma_v2_4_set_powergating_state, |
1118 | }; |
1119 | |
1120 | static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { |
1121 | .type = AMDGPU_RING_TYPE_SDMA, |
1122 | .align_mask = 0xf, |
1123 | .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), |
1124 | .support_64bit_ptrs = false, |
1125 | .secure_submission_supported = true, |
1126 | .get_rptr = sdma_v2_4_ring_get_rptr, |
1127 | .get_wptr = sdma_v2_4_ring_get_wptr, |
1128 | .set_wptr = sdma_v2_4_ring_set_wptr, |
1129 | .emit_frame_size = |
1130 | 6 + /* sdma_v2_4_ring_emit_hdp_flush */ |
1131 | 3 + /* hdp invalidate */ |
1132 | 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ |
1133 | VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ |
1134 | 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ |
1135 | .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ |
1136 | .emit_ib = sdma_v2_4_ring_emit_ib, |
1137 | .emit_fence = sdma_v2_4_ring_emit_fence, |
1138 | .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, |
1139 | .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, |
1140 | .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, |
1141 | .test_ring = sdma_v2_4_ring_test_ring, |
1142 | .test_ib = sdma_v2_4_ring_test_ib, |
1143 | .insert_nop = sdma_v2_4_ring_insert_nop, |
1144 | .pad_ib = sdma_v2_4_ring_pad_ib, |
1145 | .emit_wreg = sdma_v2_4_ring_emit_wreg, |
1146 | }; |
1147 | |
1148 | static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) |
1149 | { |
1150 | int i; |
1151 | |
1152 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1153 | adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; |
1154 | adev->sdma.instance[i].ring.me = i; |
1155 | } |
1156 | } |
1157 | |
1158 | static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { |
1159 | .set = sdma_v2_4_set_trap_irq_state, |
1160 | .process = sdma_v2_4_process_trap_irq, |
1161 | }; |
1162 | |
1163 | static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { |
1164 | .process = sdma_v2_4_process_illegal_inst_irq, |
1165 | }; |
1166 | |
1167 | static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) |
1168 | { |
1169 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1170 | adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; |
1171 | adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; |
1172 | } |
1173 | |
1174 | /** |
1175 | * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine |
1176 | * |
1177 | * @ib: indirect buffer to copy to |
1178 | * @src_offset: src GPU address |
1179 | * @dst_offset: dst GPU address |
1180 | * @byte_count: number of bytes to xfer |
1181 | * @tmz: unused |
1182 | * |
1183 | * Copy GPU buffers using the DMA engine (VI). |
1184 | * Used by the amdgpu ttm implementation to move pages if |
1185 | * registered as the asic copy callback. |
1186 | */ |
1187 | static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, |
1188 | uint64_t src_offset, |
1189 | uint64_t dst_offset, |
1190 | uint32_t byte_count, |
1191 | bool tmz) |
1192 | { |
1193 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
1194 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); |
1195 | ib->ptr[ib->length_dw++] = byte_count; |
1196 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
1197 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); |
1198 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); |
1199 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); |
1200 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); |
1201 | } |
1202 | |
1203 | /** |
1204 | * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine |
1205 | * |
1206 | * @ib: indirect buffer to copy to |
1207 | * @src_data: value to write to buffer |
1208 | * @dst_offset: dst GPU address |
1209 | * @byte_count: number of bytes to xfer |
1210 | * |
1211 | * Fill GPU buffers using the DMA engine (VI). |
1212 | */ |
1213 | static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, |
1214 | uint32_t src_data, |
1215 | uint64_t dst_offset, |
1216 | uint32_t byte_count) |
1217 | { |
1218 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); |
1219 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); |
1220 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); |
1221 | ib->ptr[ib->length_dw++] = src_data; |
1222 | ib->ptr[ib->length_dw++] = byte_count; |
1223 | } |
1224 | |
1225 | static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { |
1226 | .copy_max_bytes = 0x1fffff, |
1227 | .copy_num_dw = 7, |
1228 | .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, |
1229 | |
1230 | .fill_max_bytes = 0x1fffff, |
1231 | .fill_num_dw = 7, |
1232 | .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, |
1233 | }; |
1234 | |
1235 | static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) |
1236 | { |
1237 | adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; |
1238 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
1239 | } |
1240 | |
1241 | static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { |
1242 | .copy_pte_num_dw = 7, |
1243 | .copy_pte = sdma_v2_4_vm_copy_pte, |
1244 | |
1245 | .write_pte = sdma_v2_4_vm_write_pte, |
1246 | .set_pte_pde = sdma_v2_4_vm_set_pte_pde, |
1247 | }; |
1248 | |
1249 | static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) |
1250 | { |
1251 | unsigned i; |
1252 | |
1253 | adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; |
1254 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1255 | adev->vm_manager.vm_pte_scheds[i] = |
1256 | &adev->sdma.instance[i].ring.sched; |
1257 | } |
1258 | adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; |
1259 | } |
1260 | |
1261 | const struct amdgpu_ip_block_version sdma_v2_4_ip_block = |
1262 | { |
1263 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
1264 | .major = 2, |
1265 | .minor = 4, |
1266 | .rev = 0, |
1267 | .funcs = &sdma_v2_4_ip_funcs, |
1268 | }; |
1269 | |