1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drmP.h>
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
29#include "amd_pcie.h"
30#include "sid.h"
31#include "r600_dpm.h"
32#include "si_dpm.h"
33#include "atom.h"
34#include "../include/pptable.h"
35#include <linux/math64.h>
36#include <linux/seq_file.h>
37#include <linux/firmware.h>
38
39#define MC_CG_ARB_FREQ_F0 0x0a
40#define MC_CG_ARB_FREQ_F1 0x0b
41#define MC_CG_ARB_FREQ_F2 0x0c
42#define MC_CG_ARB_FREQ_F3 0x0d
43
44#define SMC_RAM_END 0x20000
45
46#define SCLK_MIN_DEEPSLEEP_FREQ 1350
47
48
49/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
55#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
56
57#define BIOS_SCRATCH_4 0x5cd
58
59MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
60MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
61MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
62MODULE_FIRMWARE("amdgpu/verde_smc.bin");
63MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
64MODULE_FIRMWARE("amdgpu/oland_smc.bin");
65MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
66MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
67MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
68MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
69
70static const struct amd_pm_funcs si_dpm_funcs;
71
72union power_info {
73 struct _ATOM_POWERPLAY_INFO info;
74 struct _ATOM_POWERPLAY_INFO_V2 info_2;
75 struct _ATOM_POWERPLAY_INFO_V3 info_3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
77 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
78 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
79 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
80 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
81};
82
83union fan_info {
84 struct _ATOM_PPLIB_FANTABLE fan;
85 struct _ATOM_PPLIB_FANTABLE2 fan2;
86 struct _ATOM_PPLIB_FANTABLE3 fan3;
87};
88
89union pplib_clock_info {
90 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
91 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
92 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
93 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
94 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
95};
96
97static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
98{
99 R600_UTC_DFLT_00,
100 R600_UTC_DFLT_01,
101 R600_UTC_DFLT_02,
102 R600_UTC_DFLT_03,
103 R600_UTC_DFLT_04,
104 R600_UTC_DFLT_05,
105 R600_UTC_DFLT_06,
106 R600_UTC_DFLT_07,
107 R600_UTC_DFLT_08,
108 R600_UTC_DFLT_09,
109 R600_UTC_DFLT_10,
110 R600_UTC_DFLT_11,
111 R600_UTC_DFLT_12,
112 R600_UTC_DFLT_13,
113 R600_UTC_DFLT_14,
114};
115
116static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
117{
118 R600_DTC_DFLT_00,
119 R600_DTC_DFLT_01,
120 R600_DTC_DFLT_02,
121 R600_DTC_DFLT_03,
122 R600_DTC_DFLT_04,
123 R600_DTC_DFLT_05,
124 R600_DTC_DFLT_06,
125 R600_DTC_DFLT_07,
126 R600_DTC_DFLT_08,
127 R600_DTC_DFLT_09,
128 R600_DTC_DFLT_10,
129 R600_DTC_DFLT_11,
130 R600_DTC_DFLT_12,
131 R600_DTC_DFLT_13,
132 R600_DTC_DFLT_14,
133};
134
135static const struct si_cac_config_reg cac_weights_tahiti[] =
136{
137 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
140 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
141 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
144 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
146 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
147 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
148 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
149 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
150 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
151 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
152 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
154 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
155 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
156 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
157 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
158 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
159 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
165 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
168 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
169 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
172 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
174 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
175 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
177 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
194 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
195 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
196 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
197 { 0xFFFFFFFF }
198};
199
200static const struct si_cac_config_reg lcac_tahiti[] =
201{
202 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
203 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
204 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
205 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
206 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
207 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
208 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
209 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
210 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
211 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
212 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
213 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
214 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
215 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
216 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
217 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
218 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
219 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
220 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
221 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
222 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
223 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
224 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
225 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
226 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
227 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
228 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
229 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
230 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
231 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
232 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
233 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
234 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
235 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
236 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
237 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
238 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
239 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
240 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
241 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
242 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
243 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
244 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
245 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
246 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
247 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
248 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
249 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
250 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
251 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
252 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
253 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
254 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
255 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
256 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
257 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
258 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
259 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
260 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
261 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
262 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
263 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
264 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
265 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
266 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
267 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
268 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
269 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
270 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
271 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
272 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
273 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
274 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
275 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
276 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
277 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
278 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
279 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
280 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
281 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
282 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
283 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
284 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
285 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
286 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
287 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
288 { 0xFFFFFFFF }
289
290};
291
292static const struct si_cac_config_reg cac_override_tahiti[] =
293{
294 { 0xFFFFFFFF }
295};
296
297static const struct si_powertune_data powertune_data_tahiti =
298{
299 ((1 << 16) | 27027),
300 6,
301 0,
302 4,
303 95,
304 {
305 0UL,
306 0UL,
307 4521550UL,
308 309631529UL,
309 -1270850L,
310 4513710L,
311 40
312 },
313 595000000UL,
314 12,
315 {
316 0,
317 0,
318 0,
319 0,
320 0,
321 0,
322 0,
323 0
324 },
325 true
326};
327
328static const struct si_dte_data dte_data_tahiti =
329{
330 { 1159409, 0, 0, 0, 0 },
331 { 777, 0, 0, 0, 0 },
332 2,
333 54000,
334 127000,
335 25,
336 2,
337 10,
338 13,
339 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
340 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
341 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
342 85,
343 false
344};
345
346#if 0
347static const struct si_dte_data dte_data_tahiti_le =
348{
349 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
350 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
351 0x5,
352 0xAFC8,
353 0x64,
354 0x32,
355 1,
356 0,
357 0x10,
358 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
359 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
360 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
361 85,
362 true
363};
364#endif
365
366static const struct si_dte_data dte_data_tahiti_pro =
367{
368 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
369 { 0x0, 0x0, 0x0, 0x0, 0x0 },
370 5,
371 45000,
372 100,
373 0xA,
374 1,
375 0,
376 0x10,
377 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
378 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
379 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
380 90,
381 true
382};
383
384static const struct si_dte_data dte_data_new_zealand =
385{
386 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
387 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
388 0x5,
389 0xAFC8,
390 0x69,
391 0x32,
392 1,
393 0,
394 0x10,
395 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
396 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
397 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
398 85,
399 true
400};
401
402static const struct si_dte_data dte_data_aruba_pro =
403{
404 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
405 { 0x0, 0x0, 0x0, 0x0, 0x0 },
406 5,
407 45000,
408 100,
409 0xA,
410 1,
411 0,
412 0x10,
413 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
414 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
415 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
416 90,
417 true
418};
419
420static const struct si_dte_data dte_data_malta =
421{
422 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
423 { 0x0, 0x0, 0x0, 0x0, 0x0 },
424 5,
425 45000,
426 100,
427 0xA,
428 1,
429 0,
430 0x10,
431 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
432 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
433 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
434 90,
435 true
436};
437
438static const struct si_cac_config_reg cac_weights_pitcairn[] =
439{
440 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
441 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
442 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
443 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
444 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
445 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
446 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
447 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
448 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
449 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
450 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
451 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
452 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
453 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
454 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
455 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
457 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
458 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
459 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
460 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
461 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
462 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
463 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
464 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
466 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
467 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
471 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
472 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
473 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
474 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
475 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
476 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
477 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
479 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
497 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
498 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
499 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
500 { 0xFFFFFFFF }
501};
502
503static const struct si_cac_config_reg lcac_pitcairn[] =
504{
505 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
506 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
507 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
508 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
509 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
510 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
511 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
512 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
513 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
514 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
515 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
516 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
517 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
518 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
519 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
520 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
521 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
522 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
523 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
524 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
525 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
526 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
527 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
528 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
529 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
530 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
531 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
532 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
533 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
534 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
535 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
536 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
537 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
538 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
539 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
540 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
541 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
542 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
543 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
544 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
545 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
546 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
547 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
548 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
549 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
550 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
551 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
552 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
553 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
554 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
555 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
556 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
557 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
558 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
559 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
560 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
561 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
562 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
563 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
564 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
565 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
566 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
567 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
568 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
569 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
570 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
571 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
572 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
573 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
574 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
575 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
576 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
577 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
578 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
579 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
580 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
581 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
582 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
583 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
584 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
585 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
586 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
587 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
588 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
589 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
590 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
591 { 0xFFFFFFFF }
592};
593
594static const struct si_cac_config_reg cac_override_pitcairn[] =
595{
596 { 0xFFFFFFFF }
597};
598
599static const struct si_powertune_data powertune_data_pitcairn =
600{
601 ((1 << 16) | 27027),
602 5,
603 0,
604 6,
605 100,
606 {
607 51600000UL,
608 1800000UL,
609 7194395UL,
610 309631529UL,
611 -1270850L,
612 4513710L,
613 100
614 },
615 117830498UL,
616 12,
617 {
618 0,
619 0,
620 0,
621 0,
622 0,
623 0,
624 0,
625 0
626 },
627 true
628};
629
630static const struct si_dte_data dte_data_pitcairn =
631{
632 { 0, 0, 0, 0, 0 },
633 { 0, 0, 0, 0, 0 },
634 0,
635 0,
636 0,
637 0,
638 0,
639 0,
640 0,
641 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
642 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
643 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
644 0,
645 false
646};
647
648static const struct si_dte_data dte_data_curacao_xt =
649{
650 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
651 { 0x0, 0x0, 0x0, 0x0, 0x0 },
652 5,
653 45000,
654 100,
655 0xA,
656 1,
657 0,
658 0x10,
659 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
660 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
661 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
662 90,
663 true
664};
665
666static const struct si_dte_data dte_data_curacao_pro =
667{
668 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
669 { 0x0, 0x0, 0x0, 0x0, 0x0 },
670 5,
671 45000,
672 100,
673 0xA,
674 1,
675 0,
676 0x10,
677 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
678 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
679 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
680 90,
681 true
682};
683
684static const struct si_dte_data dte_data_neptune_xt =
685{
686 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
687 { 0x0, 0x0, 0x0, 0x0, 0x0 },
688 5,
689 45000,
690 100,
691 0xA,
692 1,
693 0,
694 0x10,
695 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
696 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
697 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
698 90,
699 true
700};
701
702static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
703{
704 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
705 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
706 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
707 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
708 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
709 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
710 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
711 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
712 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
713 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
714 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
715 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
716 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
717 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
718 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
719 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
720 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
721 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
722 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
723 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
724 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
725 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
726 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
727 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
728 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
729 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
730 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
731 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
732 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
733 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
734 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
735 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
736 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
737 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
738 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
739 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
740 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
741 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
742 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
744 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
745 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
748 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
749 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
761 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
762 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
763 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
764 { 0xFFFFFFFF }
765};
766
767static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
768{
769 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
770 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
771 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
772 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
773 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
774 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
775 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
776 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
777 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
778 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
779 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
780 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
781 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
782 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
783 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
784 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
785 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
786 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
787 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
788 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
789 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
790 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
791 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
792 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
793 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
794 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
795 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
796 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
797 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
798 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
799 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
800 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
801 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
802 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
803 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
804 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
805 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
806 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
807 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
809 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
810 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
813 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
814 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
826 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
827 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
828 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
829 { 0xFFFFFFFF }
830};
831
832static const struct si_cac_config_reg cac_weights_heathrow[] =
833{
834 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
835 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
836 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
837 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
838 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
839 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
840 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
841 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
842 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
843 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
844 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
845 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
846 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
847 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
848 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
849 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
850 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
851 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
852 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
853 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
854 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
855 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
856 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
857 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
858 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
859 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
860 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
861 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
862 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
863 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
864 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
865 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
866 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
867 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
868 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
869 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
870 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
871 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
872 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
874 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
875 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
878 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
879 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
891 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
892 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
893 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
894 { 0xFFFFFFFF }
895};
896
897static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
898{
899 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
900 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
901 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
902 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
903 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
904 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
905 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
906 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
907 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
908 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
909 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
910 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
911 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
912 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
913 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
914 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
915 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
916 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
917 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
918 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
919 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
920 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
921 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
922 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
923 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
924 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
925 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
926 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
927 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
928 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
929 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
930 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
931 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
932 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
933 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
934 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
935 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
936 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
937 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
939 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
940 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
943 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
944 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
956 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
957 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
958 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
959 { 0xFFFFFFFF }
960};
961
962static const struct si_cac_config_reg cac_weights_cape_verde[] =
963{
964 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
965 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
966 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
967 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
968 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
969 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
970 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
971 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
972 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
973 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
974 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
975 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
976 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
977 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
978 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
979 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
980 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
981 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
982 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
983 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
984 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
985 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
986 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
987 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
988 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
989 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
990 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
991 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
992 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
993 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
994 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
995 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
996 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
997 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
998 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
999 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1000 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1001 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1002 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1004 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1005 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1021 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1022 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1023 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1024 { 0xFFFFFFFF }
1025};
1026
1027static const struct si_cac_config_reg lcac_cape_verde[] =
1028{
1029 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1030 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1032 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1034 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1036 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1038 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1042 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1044 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1046 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1048 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1054 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1058 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1060 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1062 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1066 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1067 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1068 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1070 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1071 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1074 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1081 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1082 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1083 { 0xFFFFFFFF }
1084};
1085
1086static const struct si_cac_config_reg cac_override_cape_verde[] =
1087{
1088 { 0xFFFFFFFF }
1089};
1090
1091static const struct si_powertune_data powertune_data_cape_verde =
1092{
1093 ((1 << 16) | 0x6993),
1094 5,
1095 0,
1096 7,
1097 105,
1098 {
1099 0UL,
1100 0UL,
1101 7194395UL,
1102 309631529UL,
1103 -1270850L,
1104 4513710L,
1105 100
1106 },
1107 117830498UL,
1108 12,
1109 {
1110 0,
1111 0,
1112 0,
1113 0,
1114 0,
1115 0,
1116 0,
1117 0
1118 },
1119 true
1120};
1121
1122static const struct si_dte_data dte_data_cape_verde =
1123{
1124 { 0, 0, 0, 0, 0 },
1125 { 0, 0, 0, 0, 0 },
1126 0,
1127 0,
1128 0,
1129 0,
1130 0,
1131 0,
1132 0,
1133 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1134 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1135 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1136 0,
1137 false
1138};
1139
1140static const struct si_dte_data dte_data_venus_xtx =
1141{
1142 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1143 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1144 5,
1145 55000,
1146 0x69,
1147 0xA,
1148 1,
1149 0,
1150 0x3,
1151 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1152 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1153 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1154 90,
1155 true
1156};
1157
1158static const struct si_dte_data dte_data_venus_xt =
1159{
1160 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1161 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1162 5,
1163 55000,
1164 0x69,
1165 0xA,
1166 1,
1167 0,
1168 0x3,
1169 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1170 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1171 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1172 90,
1173 true
1174};
1175
1176static const struct si_dte_data dte_data_venus_pro =
1177{
1178 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1179 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1180 5,
1181 55000,
1182 0x69,
1183 0xA,
1184 1,
1185 0,
1186 0x3,
1187 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1188 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1189 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1190 90,
1191 true
1192};
1193
1194static const struct si_cac_config_reg cac_weights_oland[] =
1195{
1196 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1197 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1198 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1199 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1200 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1201 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1202 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1203 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1205 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1206 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1207 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1208 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1210 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1211 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1212 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1213 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1214 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1215 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1216 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1217 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1218 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1219 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1220 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1221 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1222 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1223 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1225 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1226 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1227 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1228 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1229 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1230 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1231 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1232 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1233 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1234 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1236 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1237 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1253 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1256 { 0xFFFFFFFF }
1257};
1258
1259static const struct si_cac_config_reg cac_weights_mars_pro[] =
1260{
1261 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1262 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1265 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1267 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1268 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1270 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1271 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1272 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1273 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1275 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1276 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1277 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1278 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1279 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1280 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1281 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1282 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1283 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1284 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1285 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1286 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1287 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1288 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1289 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1290 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1291 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1292 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1293 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1294 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1295 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1296 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1297 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1298 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1299 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1301 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1302 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1306 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1318 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1321 { 0xFFFFFFFF }
1322};
1323
1324static const struct si_cac_config_reg cac_weights_mars_xt[] =
1325{
1326 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1327 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1330 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1332 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1333 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1335 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1336 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1337 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1338 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1340 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1341 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1342 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1343 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1344 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1345 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1346 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1347 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1348 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1349 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1350 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1351 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1352 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1353 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1354 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1355 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1356 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1357 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1358 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1359 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1360 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1361 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1362 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1363 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1364 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1366 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1367 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1371 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1383 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1386 { 0xFFFFFFFF }
1387};
1388
1389static const struct si_cac_config_reg cac_weights_oland_pro[] =
1390{
1391 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1392 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1395 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1397 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1398 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1400 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1401 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1402 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1403 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1405 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1406 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1407 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1408 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1409 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1410 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1411 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1412 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1413 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1414 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1415 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1416 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1417 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1418 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1419 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1420 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1421 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1422 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1423 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1424 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1425 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1426 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1427 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1428 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1429 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1431 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1432 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1435 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1436 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1448 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1451 { 0xFFFFFFFF }
1452};
1453
1454static const struct si_cac_config_reg cac_weights_oland_xt[] =
1455{
1456 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1457 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1458 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1459 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1460 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1462 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1463 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1464 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1465 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1466 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1467 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1468 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1469 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1470 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1471 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1472 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1473 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1474 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1475 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1476 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1477 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1478 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1479 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1480 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1481 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1482 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1483 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1488 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1489 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1490 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1491 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1492 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1493 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1494 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1496 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1497 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1500 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1501 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1513 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1514 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1515 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517};
1518
1519static const struct si_cac_config_reg lcac_oland[] =
1520{
1521 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1522 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1524 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1526 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1528 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1530 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1532 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1534 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1536 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1547 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1550 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1563 { 0xFFFFFFFF }
1564};
1565
1566static const struct si_cac_config_reg lcac_mars_pro[] =
1567{
1568 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1569 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1571 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1573 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1575 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1577 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1579 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1581 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1583 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1594 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1597 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1608 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1609 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1610 { 0xFFFFFFFF }
1611};
1612
1613static const struct si_cac_config_reg cac_override_oland[] =
1614{
1615 { 0xFFFFFFFF }
1616};
1617
1618static const struct si_powertune_data powertune_data_oland =
1619{
1620 ((1 << 16) | 0x6993),
1621 5,
1622 0,
1623 7,
1624 105,
1625 {
1626 0UL,
1627 0UL,
1628 7194395UL,
1629 309631529UL,
1630 -1270850L,
1631 4513710L,
1632 100
1633 },
1634 117830498UL,
1635 12,
1636 {
1637 0,
1638 0,
1639 0,
1640 0,
1641 0,
1642 0,
1643 0,
1644 0
1645 },
1646 true
1647};
1648
1649static const struct si_powertune_data powertune_data_mars_pro =
1650{
1651 ((1 << 16) | 0x6993),
1652 5,
1653 0,
1654 7,
1655 105,
1656 {
1657 0UL,
1658 0UL,
1659 7194395UL,
1660 309631529UL,
1661 -1270850L,
1662 4513710L,
1663 100
1664 },
1665 117830498UL,
1666 12,
1667 {
1668 0,
1669 0,
1670 0,
1671 0,
1672 0,
1673 0,
1674 0,
1675 0
1676 },
1677 true
1678};
1679
1680static const struct si_dte_data dte_data_oland =
1681{
1682 { 0, 0, 0, 0, 0 },
1683 { 0, 0, 0, 0, 0 },
1684 0,
1685 0,
1686 0,
1687 0,
1688 0,
1689 0,
1690 0,
1691 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1692 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1693 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1694 0,
1695 false
1696};
1697
1698static const struct si_dte_data dte_data_mars_pro =
1699{
1700 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1701 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1702 5,
1703 55000,
1704 105,
1705 0xA,
1706 1,
1707 0,
1708 0x10,
1709 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1710 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1711 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1712 90,
1713 true
1714};
1715
1716static const struct si_dte_data dte_data_sun_xt =
1717{
1718 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1719 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1720 5,
1721 55000,
1722 105,
1723 0xA,
1724 1,
1725 0,
1726 0x10,
1727 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1728 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1729 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1730 90,
1731 true
1732};
1733
1734
1735static const struct si_cac_config_reg cac_weights_hainan[] =
1736{
1737 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1738 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1739 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1740 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1741 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1743 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1744 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1745 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1746 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1747 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1748 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1749 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1750 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1752 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1753 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1754 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1755 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1756 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1757 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1758 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1759 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1760 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1761 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1763 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1764 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1765 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1768 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1769 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1770 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1771 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1772 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1773 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1774 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1776 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1777 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1779 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1794 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1795 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1796 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1797 { 0xFFFFFFFF }
1798};
1799
1800static const struct si_powertune_data powertune_data_hainan =
1801{
1802 ((1 << 16) | 0x6993),
1803 5,
1804 0,
1805 9,
1806 105,
1807 {
1808 0UL,
1809 0UL,
1810 7194395UL,
1811 309631529UL,
1812 -1270850L,
1813 4513710L,
1814 100
1815 },
1816 117830498UL,
1817 12,
1818 {
1819 0,
1820 0,
1821 0,
1822 0,
1823 0,
1824 0,
1825 0,
1826 0
1827 },
1828 true
1829};
1830
1831static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1832static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1833static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1834static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1835
1836static int si_populate_voltage_value(struct amdgpu_device *adev,
1837 const struct atom_voltage_table *table,
1838 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1839static int si_get_std_voltage_value(struct amdgpu_device *adev,
1840 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1841 u16 *std_voltage);
1842static int si_write_smc_soft_register(struct amdgpu_device *adev,
1843 u16 reg_offset, u32 value);
1844static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1845 struct rv7xx_pl *pl,
1846 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1847static int si_calculate_sclk_params(struct amdgpu_device *adev,
1848 u32 engine_clock,
1849 SISLANDS_SMC_SCLK_VALUE *sclk);
1850
1851static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1852static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1853static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1854
1855static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1856{
1857 struct si_power_info *pi = adev->pm.dpm.priv;
1858 return pi;
1859}
1860
1861static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1862 u16 v, s32 t, u32 ileakage, u32 *leakage)
1863{
1864 s64 kt, kv, leakage_w, i_leakage, vddc;
1865 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1866 s64 tmp;
1867
1868 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1869 vddc = div64_s64(drm_int2fixp(v), 1000);
1870 temperature = div64_s64(drm_int2fixp(t), 1000);
1871
1872 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1873 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1874 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1875 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1876 t_ref = drm_int2fixp(coeff->t_ref);
1877
1878 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1879 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1880 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1881 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1882
1883 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1884
1885 *leakage = drm_fixp2int(leakage_w * 1000);
1886}
1887
1888static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1889 const struct ni_leakage_coeffients *coeff,
1890 u16 v,
1891 s32 t,
1892 u32 i_leakage,
1893 u32 *leakage)
1894{
1895 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1896}
1897
1898static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1899 const u32 fixed_kt, u16 v,
1900 u32 ileakage, u32 *leakage)
1901{
1902 s64 kt, kv, leakage_w, i_leakage, vddc;
1903
1904 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1905 vddc = div64_s64(drm_int2fixp(v), 1000);
1906
1907 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1908 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1909 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1910
1911 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1912
1913 *leakage = drm_fixp2int(leakage_w * 1000);
1914}
1915
1916static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1917 const struct ni_leakage_coeffients *coeff,
1918 const u32 fixed_kt,
1919 u16 v,
1920 u32 i_leakage,
1921 u32 *leakage)
1922{
1923 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1924}
1925
1926
1927static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1928 struct si_dte_data *dte_data)
1929{
1930 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1931 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1932 u32 k = dte_data->k;
1933 u32 t_max = dte_data->max_t;
1934 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1935 u32 t_0 = dte_data->t0;
1936 u32 i;
1937
1938 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1939 dte_data->tdep_count = 3;
1940
1941 for (i = 0; i < k; i++) {
1942 dte_data->r[i] =
1943 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1944 (p_limit2 * (u32)100);
1945 }
1946
1947 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1948
1949 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1950 dte_data->tdep_r[i] = dte_data->r[4];
1951 }
1952 } else {
1953 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1954 }
1955}
1956
1957static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1958{
1959 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1960
1961 return pi;
1962}
1963
1964static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1965{
1966 struct ni_power_info *pi = adev->pm.dpm.priv;
1967
1968 return pi;
1969}
1970
1971static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1972{
1973 struct si_ps *ps = aps->ps_priv;
1974
1975 return ps;
1976}
1977
1978static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1979{
1980 struct ni_power_info *ni_pi = ni_get_pi(adev);
1981 struct si_power_info *si_pi = si_get_pi(adev);
1982 bool update_dte_from_pl2 = false;
1983
1984 if (adev->asic_type == CHIP_TAHITI) {
1985 si_pi->cac_weights = cac_weights_tahiti;
1986 si_pi->lcac_config = lcac_tahiti;
1987 si_pi->cac_override = cac_override_tahiti;
1988 si_pi->powertune_data = &powertune_data_tahiti;
1989 si_pi->dte_data = dte_data_tahiti;
1990
1991 switch (adev->pdev->device) {
1992 case 0x6798:
1993 si_pi->dte_data.enable_dte_by_default = true;
1994 break;
1995 case 0x6799:
1996 si_pi->dte_data = dte_data_new_zealand;
1997 break;
1998 case 0x6790:
1999 case 0x6791:
2000 case 0x6792:
2001 case 0x679E:
2002 si_pi->dte_data = dte_data_aruba_pro;
2003 update_dte_from_pl2 = true;
2004 break;
2005 case 0x679B:
2006 si_pi->dte_data = dte_data_malta;
2007 update_dte_from_pl2 = true;
2008 break;
2009 case 0x679A:
2010 si_pi->dte_data = dte_data_tahiti_pro;
2011 update_dte_from_pl2 = true;
2012 break;
2013 default:
2014 if (si_pi->dte_data.enable_dte_by_default == true)
2015 DRM_ERROR("DTE is not enabled!\n");
2016 break;
2017 }
2018 } else if (adev->asic_type == CHIP_PITCAIRN) {
2019 si_pi->cac_weights = cac_weights_pitcairn;
2020 si_pi->lcac_config = lcac_pitcairn;
2021 si_pi->cac_override = cac_override_pitcairn;
2022 si_pi->powertune_data = &powertune_data_pitcairn;
2023
2024 switch (adev->pdev->device) {
2025 case 0x6810:
2026 case 0x6818:
2027 si_pi->dte_data = dte_data_curacao_xt;
2028 update_dte_from_pl2 = true;
2029 break;
2030 case 0x6819:
2031 case 0x6811:
2032 si_pi->dte_data = dte_data_curacao_pro;
2033 update_dte_from_pl2 = true;
2034 break;
2035 case 0x6800:
2036 case 0x6806:
2037 si_pi->dte_data = dte_data_neptune_xt;
2038 update_dte_from_pl2 = true;
2039 break;
2040 default:
2041 si_pi->dte_data = dte_data_pitcairn;
2042 break;
2043 }
2044 } else if (adev->asic_type == CHIP_VERDE) {
2045 si_pi->lcac_config = lcac_cape_verde;
2046 si_pi->cac_override = cac_override_cape_verde;
2047 si_pi->powertune_data = &powertune_data_cape_verde;
2048
2049 switch (adev->pdev->device) {
2050 case 0x683B:
2051 case 0x683F:
2052 case 0x6829:
2053 case 0x6835:
2054 si_pi->cac_weights = cac_weights_cape_verde_pro;
2055 si_pi->dte_data = dte_data_cape_verde;
2056 break;
2057 case 0x682C:
2058 si_pi->cac_weights = cac_weights_cape_verde_pro;
2059 si_pi->dte_data = dte_data_sun_xt;
2060 update_dte_from_pl2 = true;
2061 break;
2062 case 0x6825:
2063 case 0x6827:
2064 si_pi->cac_weights = cac_weights_heathrow;
2065 si_pi->dte_data = dte_data_cape_verde;
2066 break;
2067 case 0x6824:
2068 case 0x682D:
2069 si_pi->cac_weights = cac_weights_chelsea_xt;
2070 si_pi->dte_data = dte_data_cape_verde;
2071 break;
2072 case 0x682F:
2073 si_pi->cac_weights = cac_weights_chelsea_pro;
2074 si_pi->dte_data = dte_data_cape_verde;
2075 break;
2076 case 0x6820:
2077 si_pi->cac_weights = cac_weights_heathrow;
2078 si_pi->dte_data = dte_data_venus_xtx;
2079 break;
2080 case 0x6821:
2081 si_pi->cac_weights = cac_weights_heathrow;
2082 si_pi->dte_data = dte_data_venus_xt;
2083 break;
2084 case 0x6823:
2085 case 0x682B:
2086 case 0x6822:
2087 case 0x682A:
2088 si_pi->cac_weights = cac_weights_chelsea_pro;
2089 si_pi->dte_data = dte_data_venus_pro;
2090 break;
2091 default:
2092 si_pi->cac_weights = cac_weights_cape_verde;
2093 si_pi->dte_data = dte_data_cape_verde;
2094 break;
2095 }
2096 } else if (adev->asic_type == CHIP_OLAND) {
2097 si_pi->lcac_config = lcac_mars_pro;
2098 si_pi->cac_override = cac_override_oland;
2099 si_pi->powertune_data = &powertune_data_mars_pro;
2100 si_pi->dte_data = dte_data_mars_pro;
2101
2102 switch (adev->pdev->device) {
2103 case 0x6601:
2104 case 0x6621:
2105 case 0x6603:
2106 case 0x6605:
2107 si_pi->cac_weights = cac_weights_mars_pro;
2108 update_dte_from_pl2 = true;
2109 break;
2110 case 0x6600:
2111 case 0x6606:
2112 case 0x6620:
2113 case 0x6604:
2114 si_pi->cac_weights = cac_weights_mars_xt;
2115 update_dte_from_pl2 = true;
2116 break;
2117 case 0x6611:
2118 case 0x6613:
2119 case 0x6608:
2120 si_pi->cac_weights = cac_weights_oland_pro;
2121 update_dte_from_pl2 = true;
2122 break;
2123 case 0x6610:
2124 si_pi->cac_weights = cac_weights_oland_xt;
2125 update_dte_from_pl2 = true;
2126 break;
2127 default:
2128 si_pi->cac_weights = cac_weights_oland;
2129 si_pi->lcac_config = lcac_oland;
2130 si_pi->cac_override = cac_override_oland;
2131 si_pi->powertune_data = &powertune_data_oland;
2132 si_pi->dte_data = dte_data_oland;
2133 break;
2134 }
2135 } else if (adev->asic_type == CHIP_HAINAN) {
2136 si_pi->cac_weights = cac_weights_hainan;
2137 si_pi->lcac_config = lcac_oland;
2138 si_pi->cac_override = cac_override_oland;
2139 si_pi->powertune_data = &powertune_data_hainan;
2140 si_pi->dte_data = dte_data_sun_xt;
2141 update_dte_from_pl2 = true;
2142 } else {
2143 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2144 return;
2145 }
2146
2147 ni_pi->enable_power_containment = false;
2148 ni_pi->enable_cac = false;
2149 ni_pi->enable_sq_ramping = false;
2150 si_pi->enable_dte = false;
2151
2152 if (si_pi->powertune_data->enable_powertune_by_default) {
2153 ni_pi->enable_power_containment = true;
2154 ni_pi->enable_cac = true;
2155 if (si_pi->dte_data.enable_dte_by_default) {
2156 si_pi->enable_dte = true;
2157 if (update_dte_from_pl2)
2158 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2159
2160 }
2161 ni_pi->enable_sq_ramping = true;
2162 }
2163
2164 ni_pi->driver_calculate_cac_leakage = true;
2165 ni_pi->cac_configuration_required = true;
2166
2167 if (ni_pi->cac_configuration_required) {
2168 ni_pi->support_cac_long_term_average = true;
2169 si_pi->dyn_powertune_data.l2_lta_window_size =
2170 si_pi->powertune_data->l2_lta_window_size_default;
2171 si_pi->dyn_powertune_data.lts_truncate =
2172 si_pi->powertune_data->lts_truncate_default;
2173 } else {
2174 ni_pi->support_cac_long_term_average = false;
2175 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2176 si_pi->dyn_powertune_data.lts_truncate = 0;
2177 }
2178
2179 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2180}
2181
2182static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2183{
2184 return 1;
2185}
2186
2187static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2188{
2189 u32 xclk;
2190 u32 wintime;
2191 u32 cac_window;
2192 u32 cac_window_size;
2193
2194 xclk = amdgpu_asic_get_xclk(adev);
2195
2196 if (xclk == 0)
2197 return 0;
2198
2199 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2200 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2201
2202 wintime = (cac_window_size * 100) / xclk;
2203
2204 return wintime;
2205}
2206
2207static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2208{
2209 return power_in_watts;
2210}
2211
2212static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2213 bool adjust_polarity,
2214 u32 tdp_adjustment,
2215 u32 *tdp_limit,
2216 u32 *near_tdp_limit)
2217{
2218 u32 adjustment_delta, max_tdp_limit;
2219
2220 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2221 return -EINVAL;
2222
2223 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2224
2225 if (adjust_polarity) {
2226 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2228 } else {
2229 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2230 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2231 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2232 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2233 else
2234 *near_tdp_limit = 0;
2235 }
2236
2237 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2238 return -EINVAL;
2239 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2240 return -EINVAL;
2241
2242 return 0;
2243}
2244
2245static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2246 struct amdgpu_ps *amdgpu_state)
2247{
2248 struct ni_power_info *ni_pi = ni_get_pi(adev);
2249 struct si_power_info *si_pi = si_get_pi(adev);
2250
2251 if (ni_pi->enable_power_containment) {
2252 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2253 PP_SIslands_PAPMParameters *papm_parm;
2254 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2255 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2256 u32 tdp_limit;
2257 u32 near_tdp_limit;
2258 int ret;
2259
2260 if (scaling_factor == 0)
2261 return -EINVAL;
2262
2263 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2264
2265 ret = si_calculate_adjusted_tdp_limits(adev,
2266 false, /* ??? */
2267 adev->pm.dpm.tdp_adjustment,
2268 &tdp_limit,
2269 &near_tdp_limit);
2270 if (ret)
2271 return ret;
2272
2273 smc_table->dpm2Params.TDPLimit =
2274 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2275 smc_table->dpm2Params.NearTDPLimit =
2276 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2277 smc_table->dpm2Params.SafePowerLimit =
2278 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2279
2280 ret = amdgpu_si_copy_bytes_to_smc(adev,
2281 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2282 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2283 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2284 sizeof(u32) * 3,
2285 si_pi->sram_end);
2286 if (ret)
2287 return ret;
2288
2289 if (si_pi->enable_ppm) {
2290 papm_parm = &si_pi->papm_parm;
2291 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2292 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2293 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2294 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2295 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2296 papm_parm->PlatformPowerLimit = 0xffffffff;
2297 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2298
2299 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2300 (u8 *)papm_parm,
2301 sizeof(PP_SIslands_PAPMParameters),
2302 si_pi->sram_end);
2303 if (ret)
2304 return ret;
2305 }
2306 }
2307 return 0;
2308}
2309
2310static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2311 struct amdgpu_ps *amdgpu_state)
2312{
2313 struct ni_power_info *ni_pi = ni_get_pi(adev);
2314 struct si_power_info *si_pi = si_get_pi(adev);
2315
2316 if (ni_pi->enable_power_containment) {
2317 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2318 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2319 int ret;
2320
2321 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2322
2323 smc_table->dpm2Params.NearTDPLimit =
2324 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2325 smc_table->dpm2Params.SafePowerLimit =
2326 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2327
2328 ret = amdgpu_si_copy_bytes_to_smc(adev,
2329 (si_pi->state_table_start +
2330 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2331 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2332 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2333 sizeof(u32) * 2,
2334 si_pi->sram_end);
2335 if (ret)
2336 return ret;
2337 }
2338
2339 return 0;
2340}
2341
2342static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2343 const u16 prev_std_vddc,
2344 const u16 curr_std_vddc)
2345{
2346 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2347 u64 prev_vddc = (u64)prev_std_vddc;
2348 u64 curr_vddc = (u64)curr_std_vddc;
2349 u64 pwr_efficiency_ratio, n, d;
2350
2351 if ((prev_vddc == 0) || (curr_vddc == 0))
2352 return 0;
2353
2354 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2355 d = prev_vddc * prev_vddc;
2356 pwr_efficiency_ratio = div64_u64(n, d);
2357
2358 if (pwr_efficiency_ratio > (u64)0xFFFF)
2359 return 0;
2360
2361 return (u16)pwr_efficiency_ratio;
2362}
2363
2364static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2365 struct amdgpu_ps *amdgpu_state)
2366{
2367 struct si_power_info *si_pi = si_get_pi(adev);
2368
2369 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2370 amdgpu_state->vclk && amdgpu_state->dclk)
2371 return true;
2372
2373 return false;
2374}
2375
2376struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2377{
2378 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2379
2380 return pi;
2381}
2382
2383static int si_populate_power_containment_values(struct amdgpu_device *adev,
2384 struct amdgpu_ps *amdgpu_state,
2385 SISLANDS_SMC_SWSTATE *smc_state)
2386{
2387 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2388 struct ni_power_info *ni_pi = ni_get_pi(adev);
2389 struct si_ps *state = si_get_ps(amdgpu_state);
2390 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2391 u32 prev_sclk;
2392 u32 max_sclk;
2393 u32 min_sclk;
2394 u16 prev_std_vddc;
2395 u16 curr_std_vddc;
2396 int i;
2397 u16 pwr_efficiency_ratio;
2398 u8 max_ps_percent;
2399 bool disable_uvd_power_tune;
2400 int ret;
2401
2402 if (ni_pi->enable_power_containment == false)
2403 return 0;
2404
2405 if (state->performance_level_count == 0)
2406 return -EINVAL;
2407
2408 if (smc_state->levelCount != state->performance_level_count)
2409 return -EINVAL;
2410
2411 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2412
2413 smc_state->levels[0].dpm2.MaxPS = 0;
2414 smc_state->levels[0].dpm2.NearTDPDec = 0;
2415 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2416 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2417 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2418
2419 for (i = 1; i < state->performance_level_count; i++) {
2420 prev_sclk = state->performance_levels[i-1].sclk;
2421 max_sclk = state->performance_levels[i].sclk;
2422 if (i == 1)
2423 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2424 else
2425 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2426
2427 if (prev_sclk > max_sclk)
2428 return -EINVAL;
2429
2430 if ((max_ps_percent == 0) ||
2431 (prev_sclk == max_sclk) ||
2432 disable_uvd_power_tune)
2433 min_sclk = max_sclk;
2434 else if (i == 1)
2435 min_sclk = prev_sclk;
2436 else
2437 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2438
2439 if (min_sclk < state->performance_levels[0].sclk)
2440 min_sclk = state->performance_levels[0].sclk;
2441
2442 if (min_sclk == 0)
2443 return -EINVAL;
2444
2445 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2446 state->performance_levels[i-1].vddc, &vddc);
2447 if (ret)
2448 return ret;
2449
2450 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2451 if (ret)
2452 return ret;
2453
2454 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2455 state->performance_levels[i].vddc, &vddc);
2456 if (ret)
2457 return ret;
2458
2459 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2460 if (ret)
2461 return ret;
2462
2463 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2464 prev_std_vddc, curr_std_vddc);
2465
2466 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2467 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2468 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2469 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2470 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2471 }
2472
2473 return 0;
2474}
2475
2476static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2477 struct amdgpu_ps *amdgpu_state,
2478 SISLANDS_SMC_SWSTATE *smc_state)
2479{
2480 struct ni_power_info *ni_pi = ni_get_pi(adev);
2481 struct si_ps *state = si_get_ps(amdgpu_state);
2482 u32 sq_power_throttle, sq_power_throttle2;
2483 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2484 int i;
2485
2486 if (state->performance_level_count == 0)
2487 return -EINVAL;
2488
2489 if (smc_state->levelCount != state->performance_level_count)
2490 return -EINVAL;
2491
2492 if (adev->pm.dpm.sq_ramping_threshold == 0)
2493 return -EINVAL;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2508 enable_sq_ramping = false;
2509
2510 for (i = 0; i < state->performance_level_count; i++) {
2511 sq_power_throttle = 0;
2512 sq_power_throttle2 = 0;
2513
2514 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2515 enable_sq_ramping) {
2516 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2517 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2518 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2519 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2520 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2521 } else {
2522 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2523 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2524 }
2525
2526 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2527 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2528 }
2529
2530 return 0;
2531}
2532
2533static int si_enable_power_containment(struct amdgpu_device *adev,
2534 struct amdgpu_ps *amdgpu_new_state,
2535 bool enable)
2536{
2537 struct ni_power_info *ni_pi = ni_get_pi(adev);
2538 PPSMC_Result smc_result;
2539 int ret = 0;
2540
2541 if (ni_pi->enable_power_containment) {
2542 if (enable) {
2543 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2544 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2545 if (smc_result != PPSMC_Result_OK) {
2546 ret = -EINVAL;
2547 ni_pi->pc_enabled = false;
2548 } else {
2549 ni_pi->pc_enabled = true;
2550 }
2551 }
2552 } else {
2553 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2554 if (smc_result != PPSMC_Result_OK)
2555 ret = -EINVAL;
2556 ni_pi->pc_enabled = false;
2557 }
2558 }
2559
2560 return ret;
2561}
2562
2563static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2564{
2565 struct si_power_info *si_pi = si_get_pi(adev);
2566 int ret = 0;
2567 struct si_dte_data *dte_data = &si_pi->dte_data;
2568 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2569 u32 table_size;
2570 u8 tdep_count;
2571 u32 i;
2572
2573 if (dte_data == NULL)
2574 si_pi->enable_dte = false;
2575
2576 if (si_pi->enable_dte == false)
2577 return 0;
2578
2579 if (dte_data->k <= 0)
2580 return -EINVAL;
2581
2582 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2583 if (dte_tables == NULL) {
2584 si_pi->enable_dte = false;
2585 return -ENOMEM;
2586 }
2587
2588 table_size = dte_data->k;
2589
2590 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2591 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2592
2593 tdep_count = dte_data->tdep_count;
2594 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2595 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2596
2597 dte_tables->K = cpu_to_be32(table_size);
2598 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2599 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2600 dte_tables->WindowSize = dte_data->window_size;
2601 dte_tables->temp_select = dte_data->temp_select;
2602 dte_tables->DTE_mode = dte_data->dte_mode;
2603 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2604
2605 if (tdep_count > 0)
2606 table_size--;
2607
2608 for (i = 0; i < table_size; i++) {
2609 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2610 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2611 }
2612
2613 dte_tables->Tdep_count = tdep_count;
2614
2615 for (i = 0; i < (u32)tdep_count; i++) {
2616 dte_tables->T_limits[i] = dte_data->t_limits[i];
2617 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2618 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2619 }
2620
2621 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2622 (u8 *)dte_tables,
2623 sizeof(Smc_SIslands_DTE_Configuration),
2624 si_pi->sram_end);
2625 kfree(dte_tables);
2626
2627 return ret;
2628}
2629
2630static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2631 u16 *max, u16 *min)
2632{
2633 struct si_power_info *si_pi = si_get_pi(adev);
2634 struct amdgpu_cac_leakage_table *table =
2635 &adev->pm.dpm.dyn_state.cac_leakage_table;
2636 u32 i;
2637 u32 v0_loadline;
2638
2639 if (table == NULL)
2640 return -EINVAL;
2641
2642 *max = 0;
2643 *min = 0xFFFF;
2644
2645 for (i = 0; i < table->count; i++) {
2646 if (table->entries[i].vddc > *max)
2647 *max = table->entries[i].vddc;
2648 if (table->entries[i].vddc < *min)
2649 *min = table->entries[i].vddc;
2650 }
2651
2652 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2653 return -EINVAL;
2654
2655 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2656
2657 if (v0_loadline > 0xFFFFUL)
2658 return -EINVAL;
2659
2660 *min = (u16)v0_loadline;
2661
2662 if ((*min > *max) || (*max == 0) || (*min == 0))
2663 return -EINVAL;
2664
2665 return 0;
2666}
2667
2668static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2669{
2670 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2671 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2672}
2673
2674static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2675 PP_SIslands_CacConfig *cac_tables,
2676 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2677 u16 t0, u16 t_step)
2678{
2679 struct si_power_info *si_pi = si_get_pi(adev);
2680 u32 leakage;
2681 unsigned int i, j;
2682 s32 t;
2683 u32 smc_leakage;
2684 u32 scaling_factor;
2685 u16 voltage;
2686
2687 scaling_factor = si_get_smc_power_scaling_factor(adev);
2688
2689 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2690 t = (1000 * (i * t_step + t0));
2691
2692 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2693 voltage = vddc_max - (vddc_step * j);
2694
2695 si_calculate_leakage_for_v_and_t(adev,
2696 &si_pi->powertune_data->leakage_coefficients,
2697 voltage,
2698 t,
2699 si_pi->dyn_powertune_data.cac_leakage,
2700 &leakage);
2701
2702 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2703
2704 if (smc_leakage > 0xFFFF)
2705 smc_leakage = 0xFFFF;
2706
2707 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2708 cpu_to_be16((u16)smc_leakage);
2709 }
2710 }
2711 return 0;
2712}
2713
2714static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2715 PP_SIslands_CacConfig *cac_tables,
2716 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2717{
2718 struct si_power_info *si_pi = si_get_pi(adev);
2719 u32 leakage;
2720 unsigned int i, j;
2721 u32 smc_leakage;
2722 u32 scaling_factor;
2723 u16 voltage;
2724
2725 scaling_factor = si_get_smc_power_scaling_factor(adev);
2726
2727 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2728 voltage = vddc_max - (vddc_step * j);
2729
2730 si_calculate_leakage_for_v(adev,
2731 &si_pi->powertune_data->leakage_coefficients,
2732 si_pi->powertune_data->fixed_kt,
2733 voltage,
2734 si_pi->dyn_powertune_data.cac_leakage,
2735 &leakage);
2736
2737 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2738
2739 if (smc_leakage > 0xFFFF)
2740 smc_leakage = 0xFFFF;
2741
2742 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2743 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2744 cpu_to_be16((u16)smc_leakage);
2745 }
2746 return 0;
2747}
2748
2749static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2750{
2751 struct ni_power_info *ni_pi = ni_get_pi(adev);
2752 struct si_power_info *si_pi = si_get_pi(adev);
2753 PP_SIslands_CacConfig *cac_tables = NULL;
2754 u16 vddc_max, vddc_min, vddc_step;
2755 u16 t0, t_step;
2756 u32 load_line_slope, reg;
2757 int ret = 0;
2758 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2759
2760 if (ni_pi->enable_cac == false)
2761 return 0;
2762
2763 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2764 if (!cac_tables)
2765 return -ENOMEM;
2766
2767 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2768 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2769 WREG32(CG_CAC_CTRL, reg);
2770
2771 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2772 si_pi->dyn_powertune_data.dc_pwr_value =
2773 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2774 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2775 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2776
2777 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2778
2779 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2780 if (ret)
2781 goto done_free;
2782
2783 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2784 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2785 t_step = 4;
2786 t0 = 60;
2787
2788 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2789 ret = si_init_dte_leakage_table(adev, cac_tables,
2790 vddc_max, vddc_min, vddc_step,
2791 t0, t_step);
2792 else
2793 ret = si_init_simplified_leakage_table(adev, cac_tables,
2794 vddc_max, vddc_min, vddc_step);
2795 if (ret)
2796 goto done_free;
2797
2798 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2799
2800 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2801 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2802 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2803 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2804 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2805 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2806 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2807 cac_tables->calculation_repeats = cpu_to_be32(2);
2808 cac_tables->dc_cac = cpu_to_be32(0);
2809 cac_tables->log2_PG_LKG_SCALE = 12;
2810 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2811 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2812 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2813
2814 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2815 (u8 *)cac_tables,
2816 sizeof(PP_SIslands_CacConfig),
2817 si_pi->sram_end);
2818
2819 if (ret)
2820 goto done_free;
2821
2822 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2823
2824done_free:
2825 if (ret) {
2826 ni_pi->enable_cac = false;
2827 ni_pi->enable_power_containment = false;
2828 }
2829
2830 kfree(cac_tables);
2831
2832 return ret;
2833}
2834
2835static int si_program_cac_config_registers(struct amdgpu_device *adev,
2836 const struct si_cac_config_reg *cac_config_regs)
2837{
2838 const struct si_cac_config_reg *config_regs = cac_config_regs;
2839 u32 data = 0, offset;
2840
2841 if (!config_regs)
2842 return -EINVAL;
2843
2844 while (config_regs->offset != 0xFFFFFFFF) {
2845 switch (config_regs->type) {
2846 case SISLANDS_CACCONFIG_CGIND:
2847 offset = SMC_CG_IND_START + config_regs->offset;
2848 if (offset < SMC_CG_IND_END)
2849 data = RREG32_SMC(offset);
2850 break;
2851 default:
2852 data = RREG32(config_regs->offset);
2853 break;
2854 }
2855
2856 data &= ~config_regs->mask;
2857 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2858
2859 switch (config_regs->type) {
2860 case SISLANDS_CACCONFIG_CGIND:
2861 offset = SMC_CG_IND_START + config_regs->offset;
2862 if (offset < SMC_CG_IND_END)
2863 WREG32_SMC(offset, data);
2864 break;
2865 default:
2866 WREG32(config_regs->offset, data);
2867 break;
2868 }
2869 config_regs++;
2870 }
2871 return 0;
2872}
2873
2874static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2875{
2876 struct ni_power_info *ni_pi = ni_get_pi(adev);
2877 struct si_power_info *si_pi = si_get_pi(adev);
2878 int ret;
2879
2880 if ((ni_pi->enable_cac == false) ||
2881 (ni_pi->cac_configuration_required == false))
2882 return 0;
2883
2884 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2885 if (ret)
2886 return ret;
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2888 if (ret)
2889 return ret;
2890 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2891 if (ret)
2892 return ret;
2893
2894 return 0;
2895}
2896
2897static int si_enable_smc_cac(struct amdgpu_device *adev,
2898 struct amdgpu_ps *amdgpu_new_state,
2899 bool enable)
2900{
2901 struct ni_power_info *ni_pi = ni_get_pi(adev);
2902 struct si_power_info *si_pi = si_get_pi(adev);
2903 PPSMC_Result smc_result;
2904 int ret = 0;
2905
2906 if (ni_pi->enable_cac) {
2907 if (enable) {
2908 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2909 if (ni_pi->support_cac_long_term_average) {
2910 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2911 if (smc_result != PPSMC_Result_OK)
2912 ni_pi->support_cac_long_term_average = false;
2913 }
2914
2915 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2916 if (smc_result != PPSMC_Result_OK) {
2917 ret = -EINVAL;
2918 ni_pi->cac_enabled = false;
2919 } else {
2920 ni_pi->cac_enabled = true;
2921 }
2922
2923 if (si_pi->enable_dte) {
2924 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2925 if (smc_result != PPSMC_Result_OK)
2926 ret = -EINVAL;
2927 }
2928 }
2929 } else if (ni_pi->cac_enabled) {
2930 if (si_pi->enable_dte)
2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2932
2933 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2934
2935 ni_pi->cac_enabled = false;
2936
2937 if (ni_pi->support_cac_long_term_average)
2938 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2939 }
2940 }
2941 return ret;
2942}
2943
2944static int si_init_smc_spll_table(struct amdgpu_device *adev)
2945{
2946 struct ni_power_info *ni_pi = ni_get_pi(adev);
2947 struct si_power_info *si_pi = si_get_pi(adev);
2948 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2949 SISLANDS_SMC_SCLK_VALUE sclk_params;
2950 u32 fb_div, p_div;
2951 u32 clk_s, clk_v;
2952 u32 sclk = 0;
2953 int ret = 0;
2954 u32 tmp;
2955 int i;
2956
2957 if (si_pi->spll_table_start == 0)
2958 return -EINVAL;
2959
2960 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2961 if (spll_table == NULL)
2962 return -ENOMEM;
2963
2964 for (i = 0; i < 256; i++) {
2965 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2966 if (ret)
2967 break;
2968 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2969 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2970 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2971 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2972
2973 fb_div &= ~0x00001FFF;
2974 fb_div >>= 1;
2975 clk_v >>= 6;
2976
2977 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2978 ret = -EINVAL;
2979 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2980 ret = -EINVAL;
2981 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2982 ret = -EINVAL;
2983 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2984 ret = -EINVAL;
2985
2986 if (ret)
2987 break;
2988
2989 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2990 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2991 spll_table->freq[i] = cpu_to_be32(tmp);
2992
2993 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2994 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2995 spll_table->ss[i] = cpu_to_be32(tmp);
2996
2997 sclk += 512;
2998 }
2999
3000
3001 if (!ret)
3002 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3003 (u8 *)spll_table,
3004 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3005 si_pi->sram_end);
3006
3007 if (ret)
3008 ni_pi->enable_power_containment = false;
3009
3010 kfree(spll_table);
3011
3012 return ret;
3013}
3014
3015static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3016 u16 vce_voltage)
3017{
3018 u16 highest_leakage = 0;
3019 struct si_power_info *si_pi = si_get_pi(adev);
3020 int i;
3021
3022 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3023 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3024 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3025 }
3026
3027 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3028 return highest_leakage;
3029
3030 return vce_voltage;
3031}
3032
3033static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3034 u32 evclk, u32 ecclk, u16 *voltage)
3035{
3036 u32 i;
3037 int ret = -EINVAL;
3038 struct amdgpu_vce_clock_voltage_dependency_table *table =
3039 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3040
3041 if (((evclk == 0) && (ecclk == 0)) ||
3042 (table && (table->count == 0))) {
3043 *voltage = 0;
3044 return 0;
3045 }
3046
3047 for (i = 0; i < table->count; i++) {
3048 if ((evclk <= table->entries[i].evclk) &&
3049 (ecclk <= table->entries[i].ecclk)) {
3050 *voltage = table->entries[i].v;
3051 ret = 0;
3052 break;
3053 }
3054 }
3055
3056 /* if no match return the highest voltage */
3057 if (ret)
3058 *voltage = table->entries[table->count - 1].v;
3059
3060 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3061
3062 return ret;
3063}
3064
3065static bool si_dpm_vblank_too_short(void *handle)
3066{
3067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3068 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3069 /* we never hit the non-gddr5 limit so disable it */
3070 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3071
3072 if (vblank_time < switch_limit)
3073 return true;
3074 else
3075 return false;
3076
3077}
3078
3079static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3080 u32 arb_freq_src, u32 arb_freq_dest)
3081{
3082 u32 mc_arb_dram_timing;
3083 u32 mc_arb_dram_timing2;
3084 u32 burst_time;
3085 u32 mc_cg_config;
3086
3087 switch (arb_freq_src) {
3088 case MC_CG_ARB_FREQ_F0:
3089 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3090 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3091 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3092 break;
3093 case MC_CG_ARB_FREQ_F1:
3094 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3095 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3096 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3097 break;
3098 case MC_CG_ARB_FREQ_F2:
3099 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3100 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3101 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3102 break;
3103 case MC_CG_ARB_FREQ_F3:
3104 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3105 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3106 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3107 break;
3108 default:
3109 return -EINVAL;
3110 }
3111
3112 switch (arb_freq_dest) {
3113 case MC_CG_ARB_FREQ_F0:
3114 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3115 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3116 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3117 break;
3118 case MC_CG_ARB_FREQ_F1:
3119 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3120 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3121 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3122 break;
3123 case MC_CG_ARB_FREQ_F2:
3124 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3125 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3126 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3127 break;
3128 case MC_CG_ARB_FREQ_F3:
3129 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3130 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3131 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3132 break;
3133 default:
3134 return -EINVAL;
3135 }
3136
3137 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3138 WREG32(MC_CG_CONFIG, mc_cg_config);
3139 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3140
3141 return 0;
3142}
3143
3144static void ni_update_current_ps(struct amdgpu_device *adev,
3145 struct amdgpu_ps *rps)
3146{
3147 struct si_ps *new_ps = si_get_ps(rps);
3148 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3149 struct ni_power_info *ni_pi = ni_get_pi(adev);
3150
3151 eg_pi->current_rps = *rps;
3152 ni_pi->current_ps = *new_ps;
3153 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3154 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3155}
3156
3157static void ni_update_requested_ps(struct amdgpu_device *adev,
3158 struct amdgpu_ps *rps)
3159{
3160 struct si_ps *new_ps = si_get_ps(rps);
3161 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3162 struct ni_power_info *ni_pi = ni_get_pi(adev);
3163
3164 eg_pi->requested_rps = *rps;
3165 ni_pi->requested_ps = *new_ps;
3166 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3167 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3168}
3169
3170static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3171 struct amdgpu_ps *new_ps,
3172 struct amdgpu_ps *old_ps)
3173{
3174 struct si_ps *new_state = si_get_ps(new_ps);
3175 struct si_ps *current_state = si_get_ps(old_ps);
3176
3177 if ((new_ps->vclk == old_ps->vclk) &&
3178 (new_ps->dclk == old_ps->dclk))
3179 return;
3180
3181 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3182 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3183 return;
3184
3185 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3186}
3187
3188static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3189 struct amdgpu_ps *new_ps,
3190 struct amdgpu_ps *old_ps)
3191{
3192 struct si_ps *new_state = si_get_ps(new_ps);
3193 struct si_ps *current_state = si_get_ps(old_ps);
3194
3195 if ((new_ps->vclk == old_ps->vclk) &&
3196 (new_ps->dclk == old_ps->dclk))
3197 return;
3198
3199 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3200 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3201 return;
3202
3203 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3204}
3205
3206static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3207{
3208 unsigned int i;
3209
3210 for (i = 0; i < table->count; i++)
3211 if (voltage <= table->entries[i].value)
3212 return table->entries[i].value;
3213
3214 return table->entries[table->count - 1].value;
3215}
3216
3217static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3218 u32 max_clock, u32 requested_clock)
3219{
3220 unsigned int i;
3221
3222 if ((clocks == NULL) || (clocks->count == 0))
3223 return (requested_clock < max_clock) ? requested_clock : max_clock;
3224
3225 for (i = 0; i < clocks->count; i++) {
3226 if (clocks->values[i] >= requested_clock)
3227 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3228 }
3229
3230 return (clocks->values[clocks->count - 1] < max_clock) ?
3231 clocks->values[clocks->count - 1] : max_clock;
3232}
3233
3234static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3235 u32 max_mclk, u32 requested_mclk)
3236{
3237 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3238 max_mclk, requested_mclk);
3239}
3240
3241static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3242 u32 max_sclk, u32 requested_sclk)
3243{
3244 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3245 max_sclk, requested_sclk);
3246}
3247
3248static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3249 u32 *max_clock)
3250{
3251 u32 i, clock = 0;
3252
3253 if ((table == NULL) || (table->count == 0)) {
3254 *max_clock = clock;
3255 return;
3256 }
3257
3258 for (i = 0; i < table->count; i++) {
3259 if (clock < table->entries[i].clk)
3260 clock = table->entries[i].clk;
3261 }
3262 *max_clock = clock;
3263}
3264
3265static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3266 u32 clock, u16 max_voltage, u16 *voltage)
3267{
3268 u32 i;
3269
3270 if ((table == NULL) || (table->count == 0))
3271 return;
3272
3273 for (i= 0; i < table->count; i++) {
3274 if (clock <= table->entries[i].clk) {
3275 if (*voltage < table->entries[i].v)
3276 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3277 table->entries[i].v : max_voltage);
3278 return;
3279 }
3280 }
3281
3282 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3283}
3284
3285static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3286 const struct amdgpu_clock_and_voltage_limits *max_limits,
3287 struct rv7xx_pl *pl)
3288{
3289
3290 if ((pl->mclk == 0) || (pl->sclk == 0))
3291 return;
3292
3293 if (pl->mclk == pl->sclk)
3294 return;
3295
3296 if (pl->mclk > pl->sclk) {
3297 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3298 pl->sclk = btc_get_valid_sclk(adev,
3299 max_limits->sclk,
3300 (pl->mclk +
3301 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3302 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3303 } else {
3304 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3305 pl->mclk = btc_get_valid_mclk(adev,
3306 max_limits->mclk,
3307 pl->sclk -
3308 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3309 }
3310}
3311
3312static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3313 u16 max_vddc, u16 max_vddci,
3314 u16 *vddc, u16 *vddci)
3315{
3316 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3317 u16 new_voltage;
3318
3319 if ((0 == *vddc) || (0 == *vddci))
3320 return;
3321
3322 if (*vddc > *vddci) {
3323 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3324 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3325 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3326 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3327 }
3328 } else {
3329 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3330 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3331 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3332 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3333 }
3334 }
3335}
3336
3337static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3338 u32 *p, u32 *u)
3339{
3340 u32 b_c = 0;
3341 u32 i_c;
3342 u32 tmp;
3343
3344 i_c = (i * r_c) / 100;
3345 tmp = i_c >> p_b;
3346
3347 while (tmp) {
3348 b_c++;
3349 tmp >>= 1;
3350 }
3351
3352 *u = (b_c + 1) / 2;
3353 *p = i_c / (1 << (2 * (*u)));
3354}
3355
3356static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3357{
3358 u32 k, a, ah, al;
3359 u32 t1;
3360
3361 if ((fl == 0) || (fh == 0) || (fl > fh))
3362 return -EINVAL;
3363
3364 k = (100 * fh) / fl;
3365 t1 = (t * (k - 100));
3366 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3367 a = (a + 5) / 10;
3368 ah = ((a * t) + 5000) / 10000;
3369 al = a - ah;
3370
3371 *th = t - ah;
3372 *tl = t + al;
3373
3374 return 0;
3375}
3376
3377static bool r600_is_uvd_state(u32 class, u32 class2)
3378{
3379 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3380 return true;
3381 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3382 return true;
3383 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3384 return true;
3385 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3386 return true;
3387 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3388 return true;
3389 return false;
3390}
3391
3392static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3393{
3394 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3395}
3396
3397static void rv770_get_max_vddc(struct amdgpu_device *adev)
3398{
3399 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3400 u16 vddc;
3401
3402 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3403 pi->max_vddc = 0;
3404 else
3405 pi->max_vddc = vddc;
3406}
3407
3408static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3409{
3410 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3411 struct amdgpu_atom_ss ss;
3412
3413 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3414 ASIC_INTERNAL_ENGINE_SS, 0);
3415 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3416 ASIC_INTERNAL_MEMORY_SS, 0);
3417
3418 if (pi->sclk_ss || pi->mclk_ss)
3419 pi->dynamic_ss = true;
3420 else
3421 pi->dynamic_ss = false;
3422}
3423
3424
3425static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3426 struct amdgpu_ps *rps)
3427{
3428 struct si_ps *ps = si_get_ps(rps);
3429 struct amdgpu_clock_and_voltage_limits *max_limits;
3430 bool disable_mclk_switching = false;
3431 bool disable_sclk_switching = false;
3432 u32 mclk, sclk;
3433 u16 vddc, vddci, min_vce_voltage = 0;
3434 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3435 u32 max_sclk = 0, max_mclk = 0;
3436 int i;
3437
3438 if (adev->asic_type == CHIP_HAINAN) {
3439 if ((adev->pdev->revision == 0x81) ||
3440 (adev->pdev->revision == 0x83) ||
3441 (adev->pdev->revision == 0xC3) ||
3442 (adev->pdev->device == 0x6664) ||
3443 (adev->pdev->device == 0x6665) ||
3444 (adev->pdev->device == 0x6667)) {
3445 max_sclk = 75000;
3446 }
3447 if ((adev->pdev->revision == 0xC3) ||
3448 (adev->pdev->device == 0x6665)) {
3449 max_sclk = 60000;
3450 max_mclk = 80000;
3451 }
3452 } else if (adev->asic_type == CHIP_OLAND) {
3453 if ((adev->pdev->revision == 0xC7) ||
3454 (adev->pdev->revision == 0x80) ||
3455 (adev->pdev->revision == 0x81) ||
3456 (adev->pdev->revision == 0x83) ||
3457 (adev->pdev->revision == 0x87) ||
3458 (adev->pdev->device == 0x6604) ||
3459 (adev->pdev->device == 0x6605)) {
3460 max_sclk = 75000;
3461 }
3462 }
3463
3464 if (rps->vce_active) {
3465 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].