| 1 | /* |
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| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef SI_ENUMS_H |
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| 24 | #define SI_ENUMS_H |
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| 25 | |
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| 26 | #define VBLANK_INT_MASK (1 << 0) |
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| 27 | #define DC_HPDx_INT_EN (1 << 16) |
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| 28 | #define VBLANK_ACK (1 << 4) |
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| 29 | #define VLINE_ACK (1 << 4) |
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| 30 | |
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| 31 | #define CURSOR_WIDTH 64 |
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| 32 | #define CURSOR_HEIGHT 64 |
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| 33 | |
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| 34 | #define VGA_VSTATUS_CNTL 0xFFFCFFFF |
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| 35 | #define PRIORITY_MARK_MASK 0x7fff |
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| 36 | #define PRIORITY_OFF (1 << 16) |
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| 37 | #define PRIORITY_ALWAYS_ON (1 << 20) |
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| 38 | #define INTERLEAVE_EN (1 << 0) |
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| 39 | |
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| 40 | #define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
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| 41 | #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) |
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| 42 | #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) |
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| 43 | |
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| 44 | #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) |
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| 45 | #define GRPH_ENDIAN_NONE 0 |
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| 46 | #define GRPH_ENDIAN_8IN16 1 |
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| 47 | #define GRPH_ENDIAN_8IN32 2 |
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| 48 | #define GRPH_ENDIAN_8IN64 3 |
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| 49 | #define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) |
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| 50 | #define GRPH_RED_SEL_R 0 |
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| 51 | #define GRPH_RED_SEL_G 1 |
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| 52 | #define GRPH_RED_SEL_B 2 |
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| 53 | #define GRPH_RED_SEL_A 3 |
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| 54 | #define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) |
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| 55 | #define GRPH_GREEN_SEL_G 0 |
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| 56 | #define GRPH_GREEN_SEL_B 1 |
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| 57 | #define GRPH_GREEN_SEL_A 2 |
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| 58 | #define GRPH_GREEN_SEL_R 3 |
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| 59 | #define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) |
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| 60 | #define GRPH_BLUE_SEL_B 0 |
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| 61 | #define GRPH_BLUE_SEL_A 1 |
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| 62 | #define GRPH_BLUE_SEL_R 2 |
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| 63 | #define GRPH_BLUE_SEL_G 3 |
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| 64 | #define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) |
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| 65 | #define GRPH_ALPHA_SEL_A 0 |
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| 66 | #define GRPH_ALPHA_SEL_R 1 |
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| 67 | #define GRPH_ALPHA_SEL_G 2 |
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| 68 | #define GRPH_ALPHA_SEL_B 3 |
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| 69 | |
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| 70 | #define GRPH_DEPTH(x) (((x) & 0x3) << 0) |
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| 71 | #define GRPH_DEPTH_8BPP 0 |
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| 72 | #define GRPH_DEPTH_16BPP 1 |
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| 73 | #define GRPH_DEPTH_32BPP 2 |
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| 74 | |
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| 75 | #define GRPH_FORMAT(x) (((x) & 0x7) << 8) |
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| 76 | #define GRPH_FORMAT_INDEXED 0 |
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| 77 | #define GRPH_FORMAT_ARGB1555 0 |
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| 78 | #define GRPH_FORMAT_ARGB565 1 |
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| 79 | #define GRPH_FORMAT_ARGB4444 2 |
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| 80 | #define GRPH_FORMAT_AI88 3 |
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| 81 | #define GRPH_FORMAT_MONO16 4 |
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| 82 | #define GRPH_FORMAT_BGRA5551 5 |
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| 83 | #define GRPH_FORMAT_ARGB8888 0 |
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| 84 | #define GRPH_FORMAT_ARGB2101010 1 |
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| 85 | #define GRPH_FORMAT_32BPP_DIG 2 |
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| 86 | #define GRPH_FORMAT_8B_ARGB2101010 3 |
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| 87 | #define GRPH_FORMAT_BGRA1010102 4 |
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| 88 | #define GRPH_FORMAT_8B_BGRA1010102 5 |
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| 89 | #define GRPH_FORMAT_RGB111110 6 |
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| 90 | #define GRPH_FORMAT_BGR101111 7 |
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| 91 | |
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| 92 | #define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) |
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| 93 | #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) |
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| 94 | #define GRPH_ARRAY_LINEAR_GENERAL 0 |
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| 95 | #define GRPH_ARRAY_LINEAR_ALIGNED 1 |
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| 96 | #define GRPH_ARRAY_1D_TILED_THIN1 2 |
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| 97 | #define GRPH_ARRAY_2D_TILED_THIN1 4 |
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| 98 | #define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) |
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| 99 | #define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) |
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| 100 | #define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) |
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| 101 | #define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) |
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| 102 | #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) |
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| 103 | #define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) |
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| 104 | |
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| 105 | #define CURSOR_EN (1 << 0) |
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| 106 | #define CURSOR_MODE(x) (((x) & 0x3) << 8) |
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| 107 | #define CURSOR_MONO 0 |
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| 108 | #define CURSOR_24_1 1 |
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| 109 | #define CURSOR_24_8_PRE_MULT 2 |
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| 110 | #define CURSOR_24_8_UNPRE_MULT 3 |
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| 111 | #define CURSOR_2X_MAGNIFY (1 << 16) |
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| 112 | #define CURSOR_FORCE_MC_ON (1 << 20) |
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| 113 | #define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) |
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| 114 | #define CURSOR_URGENT_ALWAYS 0 |
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| 115 | #define CURSOR_URGENT_1_8 1 |
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| 116 | #define CURSOR_URGENT_1_4 2 |
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| 117 | #define CURSOR_URGENT_3_8 3 |
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| 118 | #define CURSOR_URGENT_1_2 4 |
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| 119 | #define CURSOR_UPDATE_PENDING (1 << 0) |
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| 120 | #define CURSOR_UPDATE_TAKEN (1 << 1) |
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| 121 | #define CURSOR_UPDATE_LOCK (1 << 16) |
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| 122 | #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) |
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| 123 | |
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| 124 | #define SI_CRTC0_REGISTER_OFFSET 0 |
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| 125 | #define SI_CRTC1_REGISTER_OFFSET 0x300 |
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| 126 | #define SI_CRTC2_REGISTER_OFFSET 0x2600 |
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| 127 | #define SI_CRTC3_REGISTER_OFFSET 0x2900 |
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| 128 | #define SI_CRTC4_REGISTER_OFFSET 0x2c00 |
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| 129 | #define SI_CRTC5_REGISTER_OFFSET 0x2f00 |
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| 130 | |
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| 131 | #define DMA0_REGISTER_OFFSET 0x000 |
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| 132 | #define DMA1_REGISTER_OFFSET 0x200 |
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| 133 | #define ES_AND_GS_AUTO 3 |
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| 134 | #define RADEON_PACKET_TYPE3 3 |
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| 135 | #define CE_PARTITION_BASE 3 |
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| 136 | #define BUF_SWAP_32BIT (2 << 16) |
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| 137 | |
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| 138 | #define GFX_POWER_STATUS (1 << 1) |
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| 139 | #define GFX_CLOCK_STATUS (1 << 2) |
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| 140 | #define GFX_LS_STATUS (1 << 3) |
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| 141 | #define RLC_BUSY_STATUS (1 << 0) |
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| 142 | |
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| 143 | #define RLC_PUD(x) ((x) << 0) |
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| 144 | #define RLC_PUD_MASK (0xff << 0) |
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| 145 | #define RLC_PDD(x) ((x) << 8) |
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| 146 | #define RLC_PDD_MASK (0xff << 8) |
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| 147 | #define RLC_TTPD(x) ((x) << 16) |
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| 148 | #define RLC_TTPD_MASK (0xff << 16) |
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| 149 | #define RLC_MSD(x) ((x) << 24) |
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| 150 | #define RLC_MSD_MASK (0xff << 24) |
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| 151 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) |
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| 152 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
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| 153 | #define EVENT_TYPE(x) ((x) << 0) |
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| 154 | #define EVENT_INDEX(x) ((x) << 8) |
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| 155 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
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| 156 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
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| 157 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
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| 158 | |
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| 159 | #define GFX6_NUM_GFX_RINGS 1 |
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| 160 | #define GFX6_NUM_COMPUTE_RINGS 2 |
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| 161 | #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 |
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| 162 | #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D |
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| 163 | |
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| 164 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
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| 165 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
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| 166 | #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
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| 167 | |
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| 168 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
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| 169 | (((op) & 0xFF) << 8) | \ |
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| 170 | ((n) & 0x3FFF) << 16) |
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| 171 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) |
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| 172 | #define PACKET3_NOP 0x10 |
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| 173 | #define PACKET3_SET_BASE 0x11 |
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| 174 | #define PACKET3_BASE_INDEX(x) ((x) << 0) |
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| 175 | #define PACKET3_CLEAR_STATE 0x12 |
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| 176 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
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| 177 | #define PACKET3_DISPATCH_DIRECT 0x15 |
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| 178 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
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| 179 | #define PACKET3_ALLOC_GDS 0x1B |
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| 180 | #define PACKET3_WRITE_GDS_RAM 0x1C |
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| 181 | #define PACKET3_ATOMIC_GDS 0x1D |
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| 182 | #define PACKET3_ATOMIC 0x1E |
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| 183 | #define PACKET3_OCCLUSION_QUERY 0x1F |
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| 184 | #define PACKET3_SET_PREDICATION 0x20 |
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| 185 | #define PACKET3_REG_RMW 0x21 |
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| 186 | #define PACKET3_COND_EXEC 0x22 |
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| 187 | #define PACKET3_PRED_EXEC 0x23 |
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| 188 | #define PACKET3_DRAW_INDIRECT 0x24 |
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| 189 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
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| 190 | #define PACKET3_INDEX_BASE 0x26 |
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| 191 | #define PACKET3_DRAW_INDEX_2 0x27 |
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| 192 | #define PACKET3_CONTEXT_CONTROL 0x28 |
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| 193 | #define PACKET3_INDEX_TYPE 0x2A |
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| 194 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C |
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| 195 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
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| 196 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
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| 197 | #define PACKET3_NUM_INSTANCES 0x2F |
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| 198 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
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| 199 | #define PACKET3_INDIRECT_BUFFER_CONST 0x31 |
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| 200 | #define PACKET3_INDIRECT_BUFFER 0x3F |
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| 201 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
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| 202 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
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| 203 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
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| 204 | #define PACKET3_WRITE_DATA 0x37 |
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| 205 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
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| 206 | #define PACKET3_MEM_SEMAPHORE 0x39 |
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| 207 | #define PACKET3_MPEG_INDEX 0x3A |
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| 208 | #define PACKET3_COPY_DW 0x3B |
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| 209 | #define PACKET3_WAIT_REG_MEM 0x3C |
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| 210 | #define PACKET3_MEM_WRITE 0x3D |
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| 211 | #define PACKET3_COPY_DATA 0x40 |
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| 212 | #define PACKET3_CP_DMA 0x41 |
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| 213 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
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| 214 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
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| 215 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) |
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| 216 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
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| 217 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
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| 218 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) |
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| 219 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) |
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| 220 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) |
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| 221 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) |
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| 222 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
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| 223 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
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| 224 | # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) |
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| 225 | #define PACKET3_PFP_SYNC_ME 0x42 |
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| 226 | #define PACKET3_SURFACE_SYNC 0x43 |
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| 227 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) |
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| 228 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) |
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| 229 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
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| 230 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
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| 231 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
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| 232 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
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| 233 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
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| 234 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
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| 235 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
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| 236 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
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| 237 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
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| 238 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) |
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| 239 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) |
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| 240 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) |
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| 241 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
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| 242 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
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| 243 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
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| 244 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) |
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| 245 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) |
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| 246 | #define PACKET3_ME_INITIALIZE 0x44 |
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| 247 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
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| 248 | #define PACKET3_COND_WRITE 0x45 |
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| 249 | #define PACKET3_EVENT_WRITE 0x46 |
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| 250 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
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| 251 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
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| 252 | #define PACKET3_PREAMBLE_CNTL 0x4A |
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| 253 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
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| 254 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
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| 255 | #define PACKET3_ONE_REG_WRITE 0x57 |
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| 256 | #define PACKET3_LOAD_CONFIG_REG 0x5F |
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| 257 | #define PACKET3_LOAD_CONTEXT_REG 0x60 |
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| 258 | #define PACKET3_LOAD_SH_REG 0x61 |
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| 259 | #define PACKET3_SET_CONFIG_REG 0x68 |
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| 260 | #define PACKET3_SET_CONFIG_REG_START 0x00002000 |
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| 261 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00 |
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| 262 | #define PACKET3_SET_CONTEXT_REG 0x69 |
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| 263 | #define PACKET3_SET_CONTEXT_REG_START 0x000a000 |
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| 264 | #define PACKET3_SET_CONTEXT_REG_END 0x000a400 |
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| 265 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
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| 266 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 |
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| 267 | #define PACKET3_SET_SH_REG 0x76 |
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| 268 | #define PACKET3_SET_SH_REG_START 0x00002c00 |
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| 269 | #define PACKET3_SET_SH_REG_END 0x00003000 |
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| 270 | #define PACKET3_SET_SH_REG_OFFSET 0x77 |
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| 271 | #define PACKET3_ME_WRITE 0x7A |
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| 272 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D |
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| 273 | #define PACKET3_SCRATCH_RAM_READ 0x7E |
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| 274 | #define PACKET3_CE_WRITE 0x7F |
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| 275 | #define PACKET3_LOAD_CONST_RAM 0x80 |
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| 276 | #define PACKET3_WRITE_CONST_RAM 0x81 |
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| 277 | #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 |
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| 278 | #define PACKET3_DUMP_CONST_RAM 0x83 |
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| 279 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 |
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| 280 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 |
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| 281 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 |
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| 282 | #define PACKET3_WAIT_ON_DE_COUNTER 0x87 |
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| 283 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 |
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| 284 | #define PACKET3_SET_CE_DE_COUNTERS 0x89 |
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| 285 | #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A |
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| 286 | #define PACKET3_SWITCH_BUFFER 0x8B |
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| 287 | #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) |
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| 288 | #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
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| 289 | #define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
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| 290 | |
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| 291 | #endif |
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| 292 | |
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