1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/bsearch.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include "kfd_priv.h"
27#include "kfd_device_queue_manager.h"
28#include "kfd_pm4_headers_vi.h"
29#include "cwsr_trap_handler.h"
30#include "kfd_iommu.h"
31#include "amdgpu_amdkfd.h"
32
33#define MQD_SIZE_ALIGNED 768
34
35/*
36 * kfd_locked is used to lock the kfd driver during suspend or reset
37 * once locked, kfd driver will stop any further GPU execution.
38 * create process (open) will return -EAGAIN.
39 */
40static atomic_t kfd_locked = ATOMIC_INIT(0);
41
42#ifdef KFD_SUPPORT_IOMMU_V2
43static const struct kfd_device_info kaveri_device_info = {
44 .asic_family = CHIP_KAVERI,
45 .max_pasid_bits = 16,
46 /* max num of queues for KV.TODO should be a dynamic value */
47 .max_no_of_hqd = 24,
48 .doorbell_size = 4,
49 .ih_ring_entry_size = 4 * sizeof(uint32_t),
50 .event_interrupt_class = &event_interrupt_class_cik,
51 .num_of_watch_points = 4,
52 .mqd_size_aligned = MQD_SIZE_ALIGNED,
53 .supports_cwsr = false,
54 .needs_iommu_device = true,
55 .needs_pci_atomics = false,
56 .num_sdma_engines = 2,
57 .num_sdma_queues_per_engine = 2,
58};
59
60static const struct kfd_device_info carrizo_device_info = {
61 .asic_family = CHIP_CARRIZO,
62 .max_pasid_bits = 16,
63 /* max num of queues for CZ.TODO should be a dynamic value */
64 .max_no_of_hqd = 24,
65 .doorbell_size = 4,
66 .ih_ring_entry_size = 4 * sizeof(uint32_t),
67 .event_interrupt_class = &event_interrupt_class_cik,
68 .num_of_watch_points = 4,
69 .mqd_size_aligned = MQD_SIZE_ALIGNED,
70 .supports_cwsr = true,
71 .needs_iommu_device = true,
72 .needs_pci_atomics = false,
73 .num_sdma_engines = 2,
74 .num_sdma_queues_per_engine = 2,
75};
76
77static const struct kfd_device_info raven_device_info = {
78 .asic_family = CHIP_RAVEN,
79 .max_pasid_bits = 16,
80 .max_no_of_hqd = 24,
81 .doorbell_size = 8,
82 .ih_ring_entry_size = 8 * sizeof(uint32_t),
83 .event_interrupt_class = &event_interrupt_class_v9,
84 .num_of_watch_points = 4,
85 .mqd_size_aligned = MQD_SIZE_ALIGNED,
86 .supports_cwsr = true,
87 .needs_iommu_device = true,
88 .needs_pci_atomics = true,
89 .num_sdma_engines = 1,
90 .num_sdma_queues_per_engine = 2,
91};
92#endif
93
94static const struct kfd_device_info hawaii_device_info = {
95 .asic_family = CHIP_HAWAII,
96 .max_pasid_bits = 16,
97 /* max num of queues for KV.TODO should be a dynamic value */
98 .max_no_of_hqd = 24,
99 .doorbell_size = 4,
100 .ih_ring_entry_size = 4 * sizeof(uint32_t),
101 .event_interrupt_class = &event_interrupt_class_cik,
102 .num_of_watch_points = 4,
103 .mqd_size_aligned = MQD_SIZE_ALIGNED,
104 .supports_cwsr = false,
105 .needs_iommu_device = false,
106 .needs_pci_atomics = false,
107 .num_sdma_engines = 2,
108 .num_sdma_queues_per_engine = 2,
109};
110
111static const struct kfd_device_info tonga_device_info = {
112 .asic_family = CHIP_TONGA,
113 .max_pasid_bits = 16,
114 .max_no_of_hqd = 24,
115 .doorbell_size = 4,
116 .ih_ring_entry_size = 4 * sizeof(uint32_t),
117 .event_interrupt_class = &event_interrupt_class_cik,
118 .num_of_watch_points = 4,
119 .mqd_size_aligned = MQD_SIZE_ALIGNED,
120 .supports_cwsr = false,
121 .needs_iommu_device = false,
122 .needs_pci_atomics = true,
123 .num_sdma_engines = 2,
124 .num_sdma_queues_per_engine = 2,
125};
126
127static const struct kfd_device_info fiji_device_info = {
128 .asic_family = CHIP_FIJI,
129 .max_pasid_bits = 16,
130 .max_no_of_hqd = 24,
131 .doorbell_size = 4,
132 .ih_ring_entry_size = 4 * sizeof(uint32_t),
133 .event_interrupt_class = &event_interrupt_class_cik,
134 .num_of_watch_points = 4,
135 .mqd_size_aligned = MQD_SIZE_ALIGNED,
136 .supports_cwsr = true,
137 .needs_iommu_device = false,
138 .needs_pci_atomics = true,
139 .num_sdma_engines = 2,
140 .num_sdma_queues_per_engine = 2,
141};
142
143static const struct kfd_device_info fiji_vf_device_info = {
144 .asic_family = CHIP_FIJI,
145 .max_pasid_bits = 16,
146 .max_no_of_hqd = 24,
147 .doorbell_size = 4,
148 .ih_ring_entry_size = 4 * sizeof(uint32_t),
149 .event_interrupt_class = &event_interrupt_class_cik,
150 .num_of_watch_points = 4,
151 .mqd_size_aligned = MQD_SIZE_ALIGNED,
152 .supports_cwsr = true,
153 .needs_iommu_device = false,
154 .needs_pci_atomics = false,
155 .num_sdma_engines = 2,
156 .num_sdma_queues_per_engine = 2,
157};
158
159
160static const struct kfd_device_info polaris10_device_info = {
161 .asic_family = CHIP_POLARIS10,
162 .max_pasid_bits = 16,
163 .max_no_of_hqd = 24,
164 .doorbell_size = 4,
165 .ih_ring_entry_size = 4 * sizeof(uint32_t),
166 .event_interrupt_class = &event_interrupt_class_cik,
167 .num_of_watch_points = 4,
168 .mqd_size_aligned = MQD_SIZE_ALIGNED,
169 .supports_cwsr = true,
170 .needs_iommu_device = false,
171 .needs_pci_atomics = true,
172 .num_sdma_engines = 2,
173 .num_sdma_queues_per_engine = 2,
174};
175
176static const struct kfd_device_info polaris10_vf_device_info = {
177 .asic_family = CHIP_POLARIS10,
178 .max_pasid_bits = 16,
179 .max_no_of_hqd = 24,
180 .doorbell_size = 4,
181 .ih_ring_entry_size = 4 * sizeof(uint32_t),
182 .event_interrupt_class = &event_interrupt_class_cik,
183 .num_of_watch_points = 4,
184 .mqd_size_aligned = MQD_SIZE_ALIGNED,
185 .supports_cwsr = true,
186 .needs_iommu_device = false,
187 .needs_pci_atomics = false,
188 .num_sdma_engines = 2,
189 .num_sdma_queues_per_engine = 2,
190};
191
192static const struct kfd_device_info polaris11_device_info = {
193 .asic_family = CHIP_POLARIS11,
194 .max_pasid_bits = 16,
195 .max_no_of_hqd = 24,
196 .doorbell_size = 4,
197 .ih_ring_entry_size = 4 * sizeof(uint32_t),
198 .event_interrupt_class = &event_interrupt_class_cik,
199 .num_of_watch_points = 4,
200 .mqd_size_aligned = MQD_SIZE_ALIGNED,
201 .supports_cwsr = true,
202 .needs_iommu_device = false,
203 .needs_pci_atomics = true,
204 .num_sdma_engines = 2,
205 .num_sdma_queues_per_engine = 2,
206};
207
208static const struct kfd_device_info polaris12_device_info = {
209 .asic_family = CHIP_POLARIS12,
210 .max_pasid_bits = 16,
211 .max_no_of_hqd = 24,
212 .doorbell_size = 4,
213 .ih_ring_entry_size = 4 * sizeof(uint32_t),
214 .event_interrupt_class = &event_interrupt_class_cik,
215 .num_of_watch_points = 4,
216 .mqd_size_aligned = MQD_SIZE_ALIGNED,
217 .supports_cwsr = true,
218 .needs_iommu_device = false,
219 .needs_pci_atomics = true,
220 .num_sdma_engines = 2,
221 .num_sdma_queues_per_engine = 2,
222};
223
224static const struct kfd_device_info vega10_device_info = {
225 .asic_family = CHIP_VEGA10,
226 .max_pasid_bits = 16,
227 .max_no_of_hqd = 24,
228 .doorbell_size = 8,
229 .ih_ring_entry_size = 8 * sizeof(uint32_t),
230 .event_interrupt_class = &event_interrupt_class_v9,
231 .num_of_watch_points = 4,
232 .mqd_size_aligned = MQD_SIZE_ALIGNED,
233 .supports_cwsr = true,
234 .needs_iommu_device = false,
235 .needs_pci_atomics = false,
236 .num_sdma_engines = 2,
237 .num_sdma_queues_per_engine = 2,
238};
239
240static const struct kfd_device_info vega10_vf_device_info = {
241 .asic_family = CHIP_VEGA10,
242 .max_pasid_bits = 16,
243 .max_no_of_hqd = 24,
244 .doorbell_size = 8,
245 .ih_ring_entry_size = 8 * sizeof(uint32_t),
246 .event_interrupt_class = &event_interrupt_class_v9,
247 .num_of_watch_points = 4,
248 .mqd_size_aligned = MQD_SIZE_ALIGNED,
249 .supports_cwsr = true,
250 .needs_iommu_device = false,
251 .needs_pci_atomics = false,
252 .num_sdma_engines = 2,
253 .num_sdma_queues_per_engine = 2,
254};
255
256static const struct kfd_device_info vega12_device_info = {
257 .asic_family = CHIP_VEGA12,
258 .max_pasid_bits = 16,
259 .max_no_of_hqd = 24,
260 .doorbell_size = 8,
261 .ih_ring_entry_size = 8 * sizeof(uint32_t),
262 .event_interrupt_class = &event_interrupt_class_v9,
263 .num_of_watch_points = 4,
264 .mqd_size_aligned = MQD_SIZE_ALIGNED,
265 .supports_cwsr = true,
266 .needs_iommu_device = false,
267 .needs_pci_atomics = false,
268 .num_sdma_engines = 2,
269 .num_sdma_queues_per_engine = 2,
270};
271
272static const struct kfd_device_info vega20_device_info = {
273 .asic_family = CHIP_VEGA20,
274 .max_pasid_bits = 16,
275 .max_no_of_hqd = 24,
276 .doorbell_size = 8,
277 .ih_ring_entry_size = 8 * sizeof(uint32_t),
278 .event_interrupt_class = &event_interrupt_class_v9,
279 .num_of_watch_points = 4,
280 .mqd_size_aligned = MQD_SIZE_ALIGNED,
281 .supports_cwsr = true,
282 .needs_iommu_device = false,
283 .needs_pci_atomics = false,
284 .num_sdma_engines = 2,
285 .num_sdma_queues_per_engine = 8,
286};
287
288struct kfd_deviceid {
289 unsigned short did;
290 const struct kfd_device_info *device_info;
291};
292
293static const struct kfd_deviceid supported_devices[] = {
294#ifdef KFD_SUPPORT_IOMMU_V2
295 { 0x1304, &kaveri_device_info }, /* Kaveri */
296 { 0x1305, &kaveri_device_info }, /* Kaveri */
297 { 0x1306, &kaveri_device_info }, /* Kaveri */
298 { 0x1307, &kaveri_device_info }, /* Kaveri */
299 { 0x1309, &kaveri_device_info }, /* Kaveri */
300 { 0x130A, &kaveri_device_info }, /* Kaveri */
301 { 0x130B, &kaveri_device_info }, /* Kaveri */
302 { 0x130C, &kaveri_device_info }, /* Kaveri */
303 { 0x130D, &kaveri_device_info }, /* Kaveri */
304 { 0x130E, &kaveri_device_info }, /* Kaveri */
305 { 0x130F, &kaveri_device_info }, /* Kaveri */
306 { 0x1310, &kaveri_device_info }, /* Kaveri */
307 { 0x1311, &kaveri_device_info }, /* Kaveri */
308 { 0x1312, &kaveri_device_info }, /* Kaveri */
309 { 0x1313, &kaveri_device_info }, /* Kaveri */
310 { 0x1315, &kaveri_device_info }, /* Kaveri */
311 { 0x1316, &kaveri_device_info }, /* Kaveri */
312 { 0x1317, &kaveri_device_info }, /* Kaveri */
313 { 0x1318, &kaveri_device_info }, /* Kaveri */
314 { 0x131B, &kaveri_device_info }, /* Kaveri */
315 { 0x131C, &kaveri_device_info }, /* Kaveri */
316 { 0x131D, &kaveri_device_info }, /* Kaveri */
317 { 0x9870, &carrizo_device_info }, /* Carrizo */
318 { 0x9874, &carrizo_device_info }, /* Carrizo */
319 { 0x9875, &carrizo_device_info }, /* Carrizo */
320 { 0x9876, &carrizo_device_info }, /* Carrizo */
321 { 0x9877, &carrizo_device_info }, /* Carrizo */
322 { 0x15DD, &raven_device_info }, /* Raven */
323#endif
324 { 0x67A0, &hawaii_device_info }, /* Hawaii */
325 { 0x67A1, &hawaii_device_info }, /* Hawaii */
326 { 0x67A2, &hawaii_device_info }, /* Hawaii */
327 { 0x67A8, &hawaii_device_info }, /* Hawaii */
328 { 0x67A9, &hawaii_device_info }, /* Hawaii */
329 { 0x67AA, &hawaii_device_info }, /* Hawaii */
330 { 0x67B0, &hawaii_device_info }, /* Hawaii */
331 { 0x67B1, &hawaii_device_info }, /* Hawaii */
332 { 0x67B8, &hawaii_device_info }, /* Hawaii */
333 { 0x67B9, &hawaii_device_info }, /* Hawaii */
334 { 0x67BA, &hawaii_device_info }, /* Hawaii */
335 { 0x67BE, &hawaii_device_info }, /* Hawaii */
336 { 0x6920, &tonga_device_info }, /* Tonga */
337 { 0x6921, &tonga_device_info }, /* Tonga */
338 { 0x6928, &tonga_device_info }, /* Tonga */
339 { 0x6929, &tonga_device_info }, /* Tonga */
340 { 0x692B, &tonga_device_info }, /* Tonga */
341 { 0x6938, &tonga_device_info }, /* Tonga */
342 { 0x6939, &tonga_device_info }, /* Tonga */
343 { 0x7300, &fiji_device_info }, /* Fiji */
344 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/
345 { 0x67C0, &polaris10_device_info }, /* Polaris10 */
346 { 0x67C1, &polaris10_device_info }, /* Polaris10 */
347 { 0x67C2, &polaris10_device_info }, /* Polaris10 */
348 { 0x67C4, &polaris10_device_info }, /* Polaris10 */
349 { 0x67C7, &polaris10_device_info }, /* Polaris10 */
350 { 0x67C8, &polaris10_device_info }, /* Polaris10 */
351 { 0x67C9, &polaris10_device_info }, /* Polaris10 */
352 { 0x67CA, &polaris10_device_info }, /* Polaris10 */
353 { 0x67CC, &polaris10_device_info }, /* Polaris10 */
354 { 0x67CF, &polaris10_device_info }, /* Polaris10 */
355 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/
356 { 0x67DF, &polaris10_device_info }, /* Polaris10 */
357 { 0x67E0, &polaris11_device_info }, /* Polaris11 */
358 { 0x67E1, &polaris11_device_info }, /* Polaris11 */
359 { 0x67E3, &polaris11_device_info }, /* Polaris11 */
360 { 0x67E7, &polaris11_device_info }, /* Polaris11 */
361 { 0x67E8, &polaris11_device_info }, /* Polaris11 */
362 { 0x67E9, &polaris11_device_info }, /* Polaris11 */
363 { 0x67EB, &polaris11_device_info }, /* Polaris11 */
364 { 0x67EF, &polaris11_device_info }, /* Polaris11 */
365 { 0x67FF, &polaris11_device_info }, /* Polaris11 */
366 { 0x6980, &polaris12_device_info }, /* Polaris12 */
367 { 0x6981, &polaris12_device_info }, /* Polaris12 */
368 { 0x6985, &polaris12_device_info }, /* Polaris12 */
369 { 0x6986, &polaris12_device_info }, /* Polaris12 */
370 { 0x6987, &polaris12_device_info }, /* Polaris12 */
371 { 0x6995, &polaris12_device_info }, /* Polaris12 */
372 { 0x6997, &polaris12_device_info }, /* Polaris12 */
373 { 0x699F, &polaris12_device_info }, /* Polaris12 */
374 { 0x6860, &vega10_device_info }, /* Vega10 */
375 { 0x6861, &vega10_device_info }, /* Vega10 */
376 { 0x6862, &vega10_device_info }, /* Vega10 */
377 { 0x6863, &vega10_device_info }, /* Vega10 */
378 { 0x6864, &vega10_device_info }, /* Vega10 */
379 { 0x6867, &vega10_device_info }, /* Vega10 */
380 { 0x6868, &vega10_device_info }, /* Vega10 */
381 { 0x6869, &vega10_device_info }, /* Vega10 */
382 { 0x686A, &vega10_device_info }, /* Vega10 */
383 { 0x686B, &vega10_device_info }, /* Vega10 */
384 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/
385 { 0x686D, &vega10_device_info }, /* Vega10 */
386 { 0x686E, &vega10_device_info }, /* Vega10 */
387 { 0x686F, &vega10_device_info }, /* Vega10 */
388 { 0x687F, &vega10_device_info }, /* Vega10 */
389 { 0x69A0, &vega12_device_info }, /* Vega12 */
390 { 0x69A1, &vega12_device_info }, /* Vega12 */
391 { 0x69A2, &vega12_device_info }, /* Vega12 */
392 { 0x69A3, &vega12_device_info }, /* Vega12 */
393 { 0x69AF, &vega12_device_info }, /* Vega12 */
394 { 0x66a0, &vega20_device_info }, /* Vega20 */
395 { 0x66a1, &vega20_device_info }, /* Vega20 */
396 { 0x66a2, &vega20_device_info }, /* Vega20 */
397 { 0x66a3, &vega20_device_info }, /* Vega20 */
398 { 0x66a4, &vega20_device_info }, /* Vega20 */
399 { 0x66a7, &vega20_device_info }, /* Vega20 */
400 { 0x66af, &vega20_device_info } /* Vega20 */
401};
402
403static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
404 unsigned int chunk_size);
405static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
406
407static int kfd_resume(struct kfd_dev *kfd);
408
409static const struct kfd_device_info *lookup_device_info(unsigned short did)
410{
411 size_t i;
412
413 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
414 if (supported_devices[i].did == did) {
415 WARN_ON(!supported_devices[i].device_info);
416 return supported_devices[i].device_info;
417 }
418 }
419
420 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n",
421 did);
422
423 return NULL;
424}
425
426struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
427 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
428{
429 struct kfd_dev *kfd;
430 int ret;
431 const struct kfd_device_info *device_info =
432 lookup_device_info(pdev->device);
433
434 if (!device_info) {
435 dev_err(kfd_device, "kgd2kfd_probe failed\n");
436 return NULL;
437 }
438
439 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
440 if (!kfd)
441 return NULL;
442
443 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
444 * 32 and 64-bit requests are possible and must be
445 * supported.
446 */
447 ret = pci_enable_atomic_ops_to_root(pdev,
448 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
449 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
450 if (device_info->needs_pci_atomics && ret < 0) {
451 dev_info(kfd_device,
452 "skipped device %x:%x, PCI rejects atomics\n",
453 pdev->vendor, pdev->device);
454 kfree(kfd);
455 return NULL;
456 } else if (!ret)
457 kfd->pci_atomic_requested = true;
458
459 kfd->kgd = kgd;
460 kfd->device_info = device_info;
461 kfd->pdev = pdev;
462 kfd->init_complete = false;
463 kfd->kfd2kgd = f2g;
464
465 mutex_init(&kfd->doorbell_mutex);
466 memset(&kfd->doorbell_available_index, 0,
467 sizeof(kfd->doorbell_available_index));
468
469 return kfd;
470}
471
472static void kfd_cwsr_init(struct kfd_dev *kfd)
473{
474 if (cwsr_enable && kfd->device_info->supports_cwsr) {
475 if (kfd->device_info->asic_family < CHIP_VEGA10) {
476 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
477 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
478 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
479 } else {
480 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
481 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
482 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
483 }
484
485 kfd->cwsr_enabled = true;
486 }
487}
488
489bool kgd2kfd_device_init(struct kfd_dev *kfd,
490 const struct kgd2kfd_shared_resources *gpu_resources)
491{
492 unsigned int size;
493
494 kfd->mec_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd,
495 KGD_ENGINE_MEC1);
496 kfd->sdma_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd,
497 KGD_ENGINE_SDMA1);
498 kfd->shared_resources = *gpu_resources;
499
500 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
501 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
502 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
503 - kfd->vm_info.first_vmid_kfd + 1;
504
505 /* Verify module parameters regarding mapped process number*/
506 if ((hws_max_conc_proc < 0)
507 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
508 dev_err(kfd_device,
509 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
510 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
511 kfd->vm_info.vmid_num_kfd);
512 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
513 } else
514 kfd->max_proc_per_quantum = hws_max_conc_proc;
515
516 /* calculate max size of mqds needed for queues */
517 size = max_num_of_queues_per_device *
518 kfd->device_info->mqd_size_aligned;
519
520 /*
521 * calculate max size of runlist packet.
522 * There can be only 2 packets at once
523 */
524 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
525 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
526 + sizeof(struct pm4_mes_runlist)) * 2;
527
528 /* Add size of HIQ & DIQ */
529 size += KFD_KERNEL_QUEUE_SIZE * 2;
530
531 /* add another 512KB for all other allocations on gart (HPD, fences) */
532 size += 512 * 1024;
533
534 if (amdgpu_amdkfd_alloc_gtt_mem(
535 kfd->kgd, size, &kfd->gtt_mem,
536 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
537 false)) {
538 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
539 goto out;
540 }
541
542 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
543
544 /* Initialize GTT sa with 512 byte chunk size */
545 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
546 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
547 goto kfd_gtt_sa_init_error;
548 }
549
550 if (kfd_doorbell_init(kfd)) {
551 dev_err(kfd_device,
552 "Error initializing doorbell aperture\n");
553 goto kfd_doorbell_error;
554 }
555
556 if (kfd->kfd2kgd->get_hive_id)
557 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
558
559 if (kfd_topology_add_device(kfd)) {
560 dev_err(kfd_device, "Error adding device to topology\n");
561 goto kfd_topology_add_device_error;
562 }
563
564 if (kfd_interrupt_init(kfd)) {
565 dev_err(kfd_device, "Error initializing interrupts\n");
566 goto kfd_interrupt_error;
567 }
568
569 kfd->dqm = device_queue_manager_init(kfd);
570 if (!kfd->dqm) {
571 dev_err(kfd_device, "Error initializing queue manager\n");
572 goto device_queue_manager_error;
573 }
574
575 if (kfd_iommu_device_init(kfd)) {
576 dev_err(kfd_device, "Error initializing iommuv2\n");
577 goto device_iommu_error;
578 }
579
580 kfd_cwsr_init(kfd);
581
582 if (kfd_resume(kfd))
583 goto kfd_resume_error;
584
585 kfd->dbgmgr = NULL;
586
587 kfd->init_complete = true;
588 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
589 kfd->pdev->device);
590
591 pr_debug("Starting kfd with the following scheduling policy %d\n",
592 kfd->dqm->sched_policy);
593
594 goto out;
595
596kfd_resume_error:
597device_iommu_error:
598 device_queue_manager_uninit(kfd->dqm);
599device_queue_manager_error:
600 kfd_interrupt_exit(kfd);
601kfd_interrupt_error:
602 kfd_topology_remove_device(kfd);
603kfd_topology_add_device_error:
604 kfd_doorbell_fini(kfd);
605kfd_doorbell_error:
606 kfd_gtt_sa_fini(kfd);
607kfd_gtt_sa_init_error:
608 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
609 dev_err(kfd_device,
610 "device %x:%x NOT added due to errors\n",
611 kfd->pdev->vendor, kfd->pdev->device);
612out:
613 return kfd->init_complete;
614}
615
616void kgd2kfd_device_exit(struct kfd_dev *kfd)
617{
618 if (kfd->init_complete) {
619 kgd2kfd_suspend(kfd);
620 device_queue_manager_uninit(kfd->dqm);
621 kfd_interrupt_exit(kfd);
622 kfd_topology_remove_device(kfd);
623 kfd_doorbell_fini(kfd);
624 kfd_gtt_sa_fini(kfd);
625 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
626 }
627
628 kfree(kfd);
629}
630
631int kgd2kfd_pre_reset(struct kfd_dev *kfd)
632{
633 if (!kfd->init_complete)
634 return 0;
635 kgd2kfd_suspend(kfd);
636
637 /* hold dqm->lock to prevent further execution*/
638 dqm_lock(kfd->dqm);
639
640 kfd_signal_reset_event(kfd);
641 return 0;
642}
643
644/*
645 * Fix me. KFD won't be able to resume existing process for now.
646 * We will keep all existing process in a evicted state and
647 * wait the process to be terminated.
648 */
649
650int kgd2kfd_post_reset(struct kfd_dev *kfd)
651{
652 int ret, count;
653
654 if (!kfd->init_complete)
655 return 0;
656
657 dqm_unlock(kfd->dqm);
658
659 ret = kfd_resume(kfd);
660 if (ret)
661 return ret;
662 count = atomic_dec_return(&kfd_locked);
663 WARN_ONCE(count != 0, "KFD reset ref. error");
664 return 0;
665}
666
667bool kfd_is_locked(void)
668{
669 return (atomic_read(&kfd_locked) > 0);
670}
671
672void kgd2kfd_suspend(struct kfd_dev *kfd)
673{
674 if (!kfd->init_complete)
675 return;
676
677 /* For first KFD device suspend all the KFD processes */
678 if (atomic_inc_return(&kfd_locked) == 1)
679 kfd_suspend_all_processes();
680
681 kfd->dqm->ops.stop(kfd->dqm);
682
683 kfd_iommu_suspend(kfd);
684}
685
686int kgd2kfd_resume(struct kfd_dev *kfd)
687{
688 int ret, count;
689
690 if (!kfd->init_complete)
691 return 0;
692
693 ret = kfd_resume(kfd);
694 if (ret)
695 return ret;
696
697 count = atomic_dec_return(&kfd_locked);
698 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
699 if (count == 0)
700 ret = kfd_resume_all_processes();
701
702 return ret;
703}
704
705static int kfd_resume(struct kfd_dev *kfd)
706{
707 int err = 0;
708
709 err = kfd_iommu_resume(kfd);
710 if (err) {
711 dev_err(kfd_device,
712 "Failed to resume IOMMU for device %x:%x\n",
713 kfd->pdev->vendor, kfd->pdev->device);
714 return err;
715 }
716
717 err = kfd->dqm->ops.start(kfd->dqm);
718 if (err) {
719 dev_err(kfd_device,
720 "Error starting queue manager for device %x:%x\n",
721 kfd->pdev->vendor, kfd->pdev->device);
722 goto dqm_start_error;
723 }
724
725 return err;
726
727dqm_start_error:
728 kfd_iommu_suspend(kfd);
729 return err;
730}
731
732/* This is called directly from KGD at ISR. */
733void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
734{
735 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
736 bool is_patched = false;
737 unsigned long flags;
738
739 if (!kfd->init_complete)
740 return;
741
742 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
743 dev_err_once(kfd_device, "Ring entry too small\n");
744 return;
745 }
746
747 spin_lock_irqsave(&kfd->interrupt_lock, flags);
748
749 if (kfd->interrupts_active
750 && interrupt_is_wanted(kfd, ih_ring_entry,
751 patched_ihre, &is_patched)
752 && enqueue_ih_ring_entry(kfd,
753 is_patched ? patched_ihre : ih_ring_entry))
754 queue_work(kfd->ih_wq, &kfd->interrupt_work);
755
756 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
757}
758
759int kgd2kfd_quiesce_mm(struct mm_struct *mm)
760{
761 struct kfd_process *p;
762 int r;
763
764 /* Because we are called from arbitrary context (workqueue) as opposed
765 * to process context, kfd_process could attempt to exit while we are
766 * running so the lookup function increments the process ref count.
767 */
768 p = kfd_lookup_process_by_mm(mm);
769 if (!p)
770 return -ESRCH;
771
772 r = kfd_process_evict_queues(p);
773
774 kfd_unref_process(p);
775 return r;
776}
777
778int kgd2kfd_resume_mm(struct mm_struct *mm)
779{
780 struct kfd_process *p;
781 int r;
782
783 /* Because we are called from arbitrary context (workqueue) as opposed
784 * to process context, kfd_process could attempt to exit while we are
785 * running so the lookup function increments the process ref count.
786 */
787 p = kfd_lookup_process_by_mm(mm);
788 if (!p)
789 return -ESRCH;
790
791 r = kfd_process_restore_queues(p);
792
793 kfd_unref_process(p);
794 return r;
795}
796
797/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
798 * prepare for safe eviction of KFD BOs that belong to the specified
799 * process.
800 *
801 * @mm: mm_struct that identifies the specified KFD process
802 * @fence: eviction fence attached to KFD process BOs
803 *
804 */
805int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
806 struct dma_fence *fence)
807{
808 struct kfd_process *p;
809 unsigned long active_time;
810 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
811
812 if (!fence)
813 return -EINVAL;
814
815 if (dma_fence_is_signaled(fence))
816 return 0;
817
818 p = kfd_lookup_process_by_mm(mm);
819 if (!p)
820 return -ENODEV;
821
822 if (fence->seqno == p->last_eviction_seqno)
823 goto out;
824
825 p->last_eviction_seqno = fence->seqno;
826
827 /* Avoid KFD process starvation. Wait for at least
828 * PROCESS_ACTIVE_TIME_MS before evicting the process again
829 */
830 active_time = get_jiffies_64() - p->last_restore_timestamp;
831 if (delay_jiffies > active_time)
832 delay_jiffies -= active_time;
833 else
834 delay_jiffies = 0;
835
836 /* During process initialization eviction_work.dwork is initialized
837 * to kfd_evict_bo_worker
838 */
839 schedule_delayed_work(&p->eviction_work, delay_jiffies);
840out:
841 kfd_unref_process(p);
842 return 0;
843}
844
845static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
846 unsigned int chunk_size)
847{
848 unsigned int num_of_longs;
849
850 if (WARN_ON(buf_size < chunk_size))
851 return -EINVAL;
852 if (WARN_ON(buf_size == 0))
853 return -EINVAL;
854 if (WARN_ON(chunk_size == 0))
855 return -EINVAL;
856
857 kfd->gtt_sa_chunk_size = chunk_size;
858 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
859
860 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
861 BITS_PER_LONG;
862
863 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
864
865 if (!kfd->gtt_sa_bitmap)
866 return -ENOMEM;
867
868 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
869 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
870
871 mutex_init(&kfd->gtt_sa_lock);
872
873 return 0;
874
875}
876
877static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
878{
879 mutex_destroy(&kfd->gtt_sa_lock);
880 kfree(kfd->gtt_sa_bitmap);
881}
882
883static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
884 unsigned int bit_num,
885 unsigned int chunk_size)
886{
887 return start_addr + bit_num * chunk_size;
888}
889
890static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
891 unsigned int bit_num,
892 unsigned int chunk_size)
893{
894 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
895}
896
897int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
898 struct kfd_mem_obj **mem_obj)
899{
900 unsigned int found, start_search, cur_size;
901
902 if (size == 0)
903 return -EINVAL;
904
905 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
906 return -ENOMEM;
907
908 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
909 if (!(*mem_obj))
910 return -ENOMEM;
911
912 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
913
914 start_search = 0;
915
916 mutex_lock(&kfd->gtt_sa_lock);
917
918kfd_gtt_restart_search:
919 /* Find the first chunk that is free */
920 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
921 kfd->gtt_sa_num_of_chunks,
922 start_search);
923
924 pr_debug("Found = %d\n", found);
925
926 /* If there wasn't any free chunk, bail out */
927 if (found == kfd->gtt_sa_num_of_chunks)
928 goto kfd_gtt_no_free_chunk;
929
930 /* Update fields of mem_obj */
931 (*mem_obj)->range_start = found;
932 (*mem_obj)->range_end = found;
933 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
934 kfd->gtt_start_gpu_addr,
935 found,
936 kfd->gtt_sa_chunk_size);
937 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
938 kfd->gtt_start_cpu_ptr,
939 found,
940 kfd->gtt_sa_chunk_size);
941
942 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
943 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
944
945 /* If we need only one chunk, mark it as allocated and get out */
946 if (size <= kfd->gtt_sa_chunk_size) {
947 pr_debug("Single bit\n");
948 set_bit(found, kfd->gtt_sa_bitmap);
949 goto kfd_gtt_out;
950 }
951
952 /* Otherwise, try to see if we have enough contiguous chunks */
953 cur_size = size - kfd->gtt_sa_chunk_size;
954 do {
955 (*mem_obj)->range_end =
956 find_next_zero_bit(kfd->gtt_sa_bitmap,
957 kfd->gtt_sa_num_of_chunks, ++found);
958 /*
959 * If next free chunk is not contiguous than we need to
960 * restart our search from the last free chunk we found (which
961 * wasn't contiguous to the previous ones
962 */
963 if ((*mem_obj)->range_end != found) {
964 start_search = found;
965 goto kfd_gtt_restart_search;
966 }
967
968 /*
969 * If we reached end of buffer, bail out with error
970 */
971 if (found == kfd->gtt_sa_num_of_chunks)
972 goto kfd_gtt_no_free_chunk;
973
974 /* Check if we don't need another chunk */
975 if (cur_size <= kfd->gtt_sa_chunk_size)
976 cur_size = 0;
977 else
978 cur_size -= kfd->gtt_sa_chunk_size;
979
980 } while (cur_size > 0);
981
982 pr_debug("range_start = %d, range_end = %d\n",
983 (*mem_obj)->range_start, (*mem_obj)->range_end);
984
985 /* Mark the chunks as allocated */
986 for (found = (*mem_obj)->range_start;
987 found <= (*mem_obj)->range_end;
988 found++)
989 set_bit(found, kfd->gtt_sa_bitmap);
990
991kfd_gtt_out:
992 mutex_unlock(&kfd->gtt_sa_lock);
993 return 0;
994
995kfd_gtt_no_free_chunk:
996 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj);
997 mutex_unlock(&kfd->gtt_sa_lock);
998 kfree(mem_obj);
999 return -ENOMEM;
1000}
1001
1002int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1003{
1004 unsigned int bit;
1005
1006 /* Act like kfree when trying to free a NULL object */
1007 if (!mem_obj)
1008 return 0;
1009
1010 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1011 mem_obj, mem_obj->range_start, mem_obj->range_end);
1012
1013 mutex_lock(&kfd->gtt_sa_lock);
1014
1015 /* Mark the chunks as free */
1016 for (bit = mem_obj->range_start;
1017 bit <= mem_obj->range_end;
1018 bit++)
1019 clear_bit(bit, kfd->gtt_sa_bitmap);
1020
1021 mutex_unlock(&kfd->gtt_sa_lock);
1022
1023 kfree(mem_obj);
1024 return 0;
1025}
1026
1027#if defined(CONFIG_DEBUG_FS)
1028
1029/* This function will send a package to HIQ to hang the HWS
1030 * which will trigger a GPU reset and bring the HWS back to normal state
1031 */
1032int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1033{
1034 int r = 0;
1035
1036 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1037 pr_err("HWS is not enabled");
1038 return -EINVAL;
1039 }
1040
1041 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1042 if (!r)
1043 r = dqm_debugfs_execute_queues(dev->dqm);
1044
1045 return r;
1046}
1047
1048#endif
1049