1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
2 | /* |
3 | * Copyright 2016-2022 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | */ |
24 | |
25 | #ifndef F32_MES_PM4_PACKETS_H |
26 | #define F32_MES_PM4_PACKETS_H |
27 | |
28 | #ifndef PM4_MES_HEADER_DEFINED |
29 | #define |
30 | union { |
31 | struct { |
32 | uint32_t : 8; /* < reserved */ |
33 | uint32_t : 8; /* < IT opcode */ |
34 | uint32_t : 14;/* < number of DWORDs - 1 in the |
35 | * information body. |
36 | */ |
37 | uint32_t : 2; /* < packet identifier. |
38 | * It should be 3 for type 3 packets |
39 | */ |
40 | }; |
41 | uint32_t ; |
42 | }; |
43 | #endif /* PM4_MES_HEADER_DEFINED */ |
44 | |
45 | /*--------------------MES_SET_RESOURCES--------------------*/ |
46 | |
47 | #ifndef PM4_MES_SET_RESOURCES_DEFINED |
48 | #define PM4_MES_SET_RESOURCES_DEFINED |
49 | enum mes_set_resources_queue_type_enum { |
50 | queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, |
51 | queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, |
52 | queue_type__mes_set_resources__hsa_debug_interface_queue = 4 |
53 | }; |
54 | |
55 | |
56 | struct pm4_mes_set_resources { |
57 | union { |
58 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
59 | uint32_t ordinal1; |
60 | }; |
61 | |
62 | union { |
63 | struct { |
64 | uint32_t vmid_mask:16; |
65 | uint32_t unmap_latency:8; |
66 | uint32_t reserved1:5; |
67 | enum mes_set_resources_queue_type_enum queue_type:3; |
68 | } bitfields2; |
69 | uint32_t ordinal2; |
70 | }; |
71 | |
72 | uint32_t queue_mask_lo; |
73 | uint32_t queue_mask_hi; |
74 | uint32_t gws_mask_lo; |
75 | uint32_t gws_mask_hi; |
76 | |
77 | union { |
78 | struct { |
79 | uint32_t oac_mask:16; |
80 | uint32_t reserved2:16; |
81 | } bitfields7; |
82 | uint32_t ordinal7; |
83 | }; |
84 | |
85 | union { |
86 | struct { |
87 | uint32_t gds_heap_base:10; |
88 | uint32_t reserved3:1; |
89 | uint32_t gds_heap_size:10; |
90 | uint32_t reserved4:11; |
91 | } bitfields8; |
92 | uint32_t ordinal8; |
93 | }; |
94 | |
95 | }; |
96 | #endif |
97 | |
98 | /*--------------------MES_RUN_LIST--------------------*/ |
99 | |
100 | #ifndef PM4_MES_RUN_LIST_DEFINED |
101 | #define PM4_MES_RUN_LIST_DEFINED |
102 | |
103 | struct pm4_mes_runlist { |
104 | union { |
105 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
106 | uint32_t ordinal1; |
107 | }; |
108 | |
109 | union { |
110 | struct { |
111 | uint32_t reserved1:2; |
112 | uint32_t ib_base_lo:30; |
113 | } bitfields2; |
114 | uint32_t ordinal2; |
115 | }; |
116 | |
117 | uint32_t ib_base_hi; |
118 | |
119 | union { |
120 | struct { |
121 | uint32_t ib_size:20; |
122 | uint32_t chain:1; |
123 | uint32_t offload_polling:1; |
124 | uint32_t chained_runlist_idle_disable:1; |
125 | uint32_t valid:1; |
126 | uint32_t process_cnt:4; |
127 | uint32_t reserved3:4; |
128 | } bitfields4; |
129 | uint32_t ordinal4; |
130 | }; |
131 | |
132 | }; |
133 | #endif |
134 | |
135 | /*--------------------MES_MAP_PROCESS--------------------*/ |
136 | |
137 | #ifndef PM4_MES_MAP_PROCESS_DEFINED |
138 | #define PM4_MES_MAP_PROCESS_DEFINED |
139 | |
140 | struct pm4_mes_map_process { |
141 | union { |
142 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
143 | uint32_t ordinal1; |
144 | }; |
145 | |
146 | union { |
147 | struct { |
148 | uint32_t pasid:16; |
149 | uint32_t reserved1:2; |
150 | uint32_t debug_vmid:4; |
151 | uint32_t new_debug:1; |
152 | uint32_t reserved2:1; |
153 | uint32_t diq_enable:1; |
154 | uint32_t process_quantum:7; |
155 | } bitfields2; |
156 | uint32_t ordinal2; |
157 | }; |
158 | |
159 | uint32_t vm_context_page_table_base_addr_lo32; |
160 | |
161 | uint32_t vm_context_page_table_base_addr_hi32; |
162 | |
163 | uint32_t sh_mem_bases; |
164 | |
165 | uint32_t sh_mem_config; |
166 | |
167 | uint32_t sq_shader_tba_lo; |
168 | |
169 | uint32_t sq_shader_tba_hi; |
170 | |
171 | uint32_t sq_shader_tma_lo; |
172 | |
173 | uint32_t sq_shader_tma_hi; |
174 | |
175 | uint32_t reserved6; |
176 | |
177 | uint32_t gds_addr_lo; |
178 | |
179 | uint32_t gds_addr_hi; |
180 | |
181 | union { |
182 | struct { |
183 | uint32_t num_gws:7; |
184 | uint32_t sdma_enable:1; |
185 | uint32_t num_oac:4; |
186 | uint32_t gds_size_hi:4; |
187 | uint32_t gds_size:6; |
188 | uint32_t num_queues:10; |
189 | } bitfields14; |
190 | uint32_t ordinal14; |
191 | }; |
192 | |
193 | uint32_t completion_signal_lo; |
194 | |
195 | uint32_t completion_signal_hi; |
196 | |
197 | }; |
198 | |
199 | #endif |
200 | |
201 | /*--------------------MES_MAP_PROCESS_VM--------------------*/ |
202 | |
203 | #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED |
204 | #define PM4_MES_MAP_PROCESS_VM_DEFINED |
205 | |
206 | struct PM4_MES_MAP_PROCESS_VM { |
207 | union { |
208 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
209 | uint32_t ordinal1; |
210 | }; |
211 | |
212 | uint32_t reserved1; |
213 | |
214 | uint32_t vm_context_cntl; |
215 | |
216 | uint32_t reserved2; |
217 | |
218 | uint32_t vm_context_page_table_end_addr_lo32; |
219 | |
220 | uint32_t vm_context_page_table_end_addr_hi32; |
221 | |
222 | uint32_t vm_context_page_table_start_addr_lo32; |
223 | |
224 | uint32_t vm_context_page_table_start_addr_hi32; |
225 | |
226 | uint32_t reserved3; |
227 | |
228 | uint32_t reserved4; |
229 | |
230 | uint32_t reserved5; |
231 | |
232 | uint32_t reserved6; |
233 | |
234 | uint32_t reserved7; |
235 | |
236 | uint32_t reserved8; |
237 | |
238 | uint32_t completion_signal_lo32; |
239 | |
240 | uint32_t completion_signal_hi32; |
241 | |
242 | }; |
243 | #endif |
244 | |
245 | /*--------------------MES_MAP_QUEUES--------------------*/ |
246 | |
247 | #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED |
248 | #define PM4_MES_MAP_QUEUES_VI_DEFINED |
249 | enum mes_map_queues_queue_sel_enum { |
250 | queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, |
251 | queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 |
252 | }; |
253 | |
254 | enum mes_map_queues_queue_type_enum { |
255 | queue_type__mes_map_queues__normal_compute_vi = 0, |
256 | queue_type__mes_map_queues__debug_interface_queue_vi = 1, |
257 | queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, |
258 | queue_type__mes_map_queues__low_latency_static_queue_vi = 3 |
259 | }; |
260 | |
261 | enum mes_map_queues_engine_sel_enum { |
262 | engine_sel__mes_map_queues__compute_vi = 0, |
263 | engine_sel__mes_map_queues__sdma0_vi = 2, |
264 | engine_sel__mes_map_queues__sdma1_vi = 3 |
265 | }; |
266 | |
267 | enum mes_map_queues_extended_engine_sel_enum { |
268 | extended_engine_sel__mes_map_queues__legacy_engine_sel = 0, |
269 | extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1, |
270 | extended_engine_sel__mes_map_queues__sdma8_to_15_sel = 2 |
271 | }; |
272 | |
273 | struct pm4_mes_map_queues { |
274 | union { |
275 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
276 | uint32_t ordinal1; |
277 | }; |
278 | |
279 | union { |
280 | struct { |
281 | uint32_t reserved1:2; |
282 | enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2; |
283 | enum mes_map_queues_queue_sel_enum queue_sel:2; |
284 | uint32_t reserved5:6; |
285 | uint32_t gws_control_queue:1; |
286 | uint32_t reserved2:8; |
287 | enum mes_map_queues_queue_type_enum queue_type:3; |
288 | uint32_t reserved3:2; |
289 | enum mes_map_queues_engine_sel_enum engine_sel:3; |
290 | uint32_t num_queues:3; |
291 | } bitfields2; |
292 | uint32_t ordinal2; |
293 | }; |
294 | |
295 | union { |
296 | struct { |
297 | uint32_t reserved3:1; |
298 | uint32_t check_disable:1; |
299 | uint32_t doorbell_offset:26; |
300 | uint32_t reserved4:4; |
301 | } bitfields3; |
302 | uint32_t ordinal3; |
303 | }; |
304 | |
305 | uint32_t mqd_addr_lo; |
306 | uint32_t mqd_addr_hi; |
307 | uint32_t wptr_addr_lo; |
308 | uint32_t wptr_addr_hi; |
309 | }; |
310 | #endif |
311 | |
312 | /*--------------------MES_QUERY_STATUS--------------------*/ |
313 | |
314 | #ifndef PM4_MES_QUERY_STATUS_DEFINED |
315 | #define PM4_MES_QUERY_STATUS_DEFINED |
316 | enum mes_query_status_interrupt_sel_enum { |
317 | interrupt_sel__mes_query_status__completion_status = 0, |
318 | interrupt_sel__mes_query_status__process_status = 1, |
319 | interrupt_sel__mes_query_status__queue_status = 2 |
320 | }; |
321 | |
322 | enum mes_query_status_command_enum { |
323 | command__mes_query_status__interrupt_only = 0, |
324 | command__mes_query_status__fence_only_immediate = 1, |
325 | command__mes_query_status__fence_only_after_write_ack = 2, |
326 | command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 |
327 | }; |
328 | |
329 | enum mes_query_status_engine_sel_enum { |
330 | engine_sel__mes_query_status__compute = 0, |
331 | engine_sel__mes_query_status__sdma0_queue = 2, |
332 | engine_sel__mes_query_status__sdma1_queue = 3 |
333 | }; |
334 | |
335 | struct pm4_mes_query_status { |
336 | union { |
337 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
338 | uint32_t ordinal1; |
339 | }; |
340 | |
341 | union { |
342 | struct { |
343 | uint32_t context_id:28; |
344 | enum mes_query_status_interrupt_sel_enum interrupt_sel:2; |
345 | enum mes_query_status_command_enum command:2; |
346 | } bitfields2; |
347 | uint32_t ordinal2; |
348 | }; |
349 | |
350 | union { |
351 | struct { |
352 | uint32_t pasid:16; |
353 | uint32_t reserved1:16; |
354 | } bitfields3a; |
355 | struct { |
356 | uint32_t reserved2:2; |
357 | uint32_t doorbell_offset:26; |
358 | enum mes_query_status_engine_sel_enum engine_sel:3; |
359 | uint32_t reserved3:1; |
360 | } bitfields3b; |
361 | uint32_t ordinal3; |
362 | }; |
363 | |
364 | uint32_t addr_lo; |
365 | uint32_t addr_hi; |
366 | uint32_t data_lo; |
367 | uint32_t data_hi; |
368 | }; |
369 | #endif |
370 | |
371 | /*--------------------MES_UNMAP_QUEUES--------------------*/ |
372 | |
373 | #ifndef PM4_MES_UNMAP_QUEUES_DEFINED |
374 | #define PM4_MES_UNMAP_QUEUES_DEFINED |
375 | enum mes_unmap_queues_action_enum { |
376 | action__mes_unmap_queues__preempt_queues = 0, |
377 | action__mes_unmap_queues__reset_queues = 1, |
378 | action__mes_unmap_queues__disable_process_queues = 2, |
379 | action__mes_unmap_queues__reserved = 3 |
380 | }; |
381 | |
382 | enum mes_unmap_queues_queue_sel_enum { |
383 | queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, |
384 | queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, |
385 | queue_sel__mes_unmap_queues__unmap_all_queues = 2, |
386 | queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 |
387 | }; |
388 | |
389 | enum mes_unmap_queues_engine_sel_enum { |
390 | engine_sel__mes_unmap_queues__compute = 0, |
391 | engine_sel__mes_unmap_queues__sdma0 = 2, |
392 | engine_sel__mes_unmap_queues__sdmal = 3 |
393 | }; |
394 | |
395 | enum mes_unmap_queues_extended_engine_sel_enum { |
396 | extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0, |
397 | extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1 |
398 | }; |
399 | |
400 | struct pm4_mes_unmap_queues { |
401 | union { |
402 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
403 | uint32_t ordinal1; |
404 | }; |
405 | |
406 | union { |
407 | struct { |
408 | enum mes_unmap_queues_action_enum action:2; |
409 | enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2; |
410 | enum mes_unmap_queues_queue_sel_enum queue_sel:2; |
411 | uint32_t reserved2:20; |
412 | enum mes_unmap_queues_engine_sel_enum engine_sel:3; |
413 | uint32_t num_queues:3; |
414 | } bitfields2; |
415 | uint32_t ordinal2; |
416 | }; |
417 | |
418 | union { |
419 | struct { |
420 | uint32_t pasid:16; |
421 | uint32_t reserved3:16; |
422 | } bitfields3a; |
423 | struct { |
424 | uint32_t reserved4:2; |
425 | uint32_t doorbell_offset0:26; |
426 | int32_t reserved5:4; |
427 | } bitfields3b; |
428 | uint32_t ordinal3; |
429 | }; |
430 | |
431 | union { |
432 | struct { |
433 | uint32_t reserved6:2; |
434 | uint32_t doorbell_offset1:26; |
435 | uint32_t reserved7:4; |
436 | } bitfields4; |
437 | uint32_t ordinal4; |
438 | }; |
439 | |
440 | union { |
441 | struct { |
442 | uint32_t reserved8:2; |
443 | uint32_t doorbell_offset2:26; |
444 | uint32_t reserved9:4; |
445 | } bitfields5; |
446 | uint32_t ordinal5; |
447 | }; |
448 | |
449 | union { |
450 | struct { |
451 | uint32_t reserved10:2; |
452 | uint32_t doorbell_offset3:26; |
453 | uint32_t reserved11:4; |
454 | } bitfields6; |
455 | uint32_t ordinal6; |
456 | }; |
457 | }; |
458 | #endif |
459 | |
460 | #ifndef PM4_MEC_RELEASE_MEM_DEFINED |
461 | #define PM4_MEC_RELEASE_MEM_DEFINED |
462 | |
463 | enum mec_release_mem_event_index_enum { |
464 | event_index__mec_release_mem__end_of_pipe = 5, |
465 | event_index__mec_release_mem__shader_done = 6 |
466 | }; |
467 | |
468 | enum mec_release_mem_cache_policy_enum { |
469 | cache_policy__mec_release_mem__lru = 0, |
470 | cache_policy__mec_release_mem__stream = 1 |
471 | }; |
472 | |
473 | enum mec_release_mem_pq_exe_status_enum { |
474 | pq_exe_status__mec_release_mem__default = 0, |
475 | pq_exe_status__mec_release_mem__phase_update = 1 |
476 | }; |
477 | |
478 | enum mec_release_mem_dst_sel_enum { |
479 | dst_sel__mec_release_mem__memory_controller = 0, |
480 | dst_sel__mec_release_mem__tc_l2 = 1, |
481 | dst_sel__mec_release_mem__queue_write_pointer_register = 2, |
482 | dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 |
483 | }; |
484 | |
485 | enum mec_release_mem_int_sel_enum { |
486 | int_sel__mec_release_mem__none = 0, |
487 | int_sel__mec_release_mem__send_interrupt_only = 1, |
488 | int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, |
489 | int_sel__mec_release_mem__send_data_after_write_confirm = 3, |
490 | int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, |
491 | int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, |
492 | int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 |
493 | }; |
494 | |
495 | enum mec_release_mem_data_sel_enum { |
496 | data_sel__mec_release_mem__none = 0, |
497 | data_sel__mec_release_mem__send_32_bit_low = 1, |
498 | data_sel__mec_release_mem__send_64_bit_data = 2, |
499 | data_sel__mec_release_mem__send_gpu_clock_counter = 3, |
500 | data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, |
501 | data_sel__mec_release_mem__store_gds_data_to_memory = 5 |
502 | }; |
503 | |
504 | struct pm4_mec_release_mem { |
505 | union { |
506 | union PM4_MES_TYPE_3_HEADER ; /*header */ |
507 | unsigned int ordinal1; |
508 | }; |
509 | |
510 | union { |
511 | struct { |
512 | unsigned int event_type:6; |
513 | unsigned int reserved1:2; |
514 | enum mec_release_mem_event_index_enum event_index:4; |
515 | unsigned int tcl1_vol_action_ena:1; |
516 | unsigned int tc_vol_action_ena:1; |
517 | unsigned int reserved2:1; |
518 | unsigned int tc_wb_action_ena:1; |
519 | unsigned int tcl1_action_ena:1; |
520 | unsigned int tc_action_ena:1; |
521 | uint32_t reserved3:1; |
522 | uint32_t tc_nc_action_ena:1; |
523 | uint32_t tc_wc_action_ena:1; |
524 | uint32_t tc_md_action_ena:1; |
525 | uint32_t reserved4:3; |
526 | enum mec_release_mem_cache_policy_enum cache_policy:2; |
527 | uint32_t reserved5:2; |
528 | enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; |
529 | uint32_t reserved6:2; |
530 | } bitfields2; |
531 | unsigned int ordinal2; |
532 | }; |
533 | |
534 | union { |
535 | struct { |
536 | uint32_t reserved7:16; |
537 | enum mec_release_mem_dst_sel_enum dst_sel:2; |
538 | uint32_t reserved8:6; |
539 | enum mec_release_mem_int_sel_enum int_sel:3; |
540 | uint32_t reserved9:2; |
541 | enum mec_release_mem_data_sel_enum data_sel:3; |
542 | } bitfields3; |
543 | unsigned int ordinal3; |
544 | }; |
545 | |
546 | union { |
547 | struct { |
548 | uint32_t reserved10:2; |
549 | unsigned int address_lo_32b:30; |
550 | } bitfields4; |
551 | struct { |
552 | uint32_t reserved11:3; |
553 | uint32_t address_lo_64b:29; |
554 | } bitfields4b; |
555 | uint32_t reserved12; |
556 | unsigned int ordinal4; |
557 | }; |
558 | |
559 | union { |
560 | uint32_t address_hi; |
561 | uint32_t reserved13; |
562 | uint32_t ordinal5; |
563 | }; |
564 | |
565 | union { |
566 | uint32_t data_lo; |
567 | uint32_t cmp_data_lo; |
568 | struct { |
569 | uint32_t dw_offset:16; |
570 | uint32_t num_dwords:16; |
571 | } bitfields6c; |
572 | uint32_t reserved14; |
573 | uint32_t ordinal6; |
574 | }; |
575 | |
576 | union { |
577 | uint32_t data_hi; |
578 | uint32_t cmp_data_hi; |
579 | uint32_t reserved15; |
580 | uint32_t reserved16; |
581 | uint32_t ordinal7; |
582 | }; |
583 | |
584 | uint32_t int_ctxid; |
585 | |
586 | }; |
587 | |
588 | #endif |
589 | |
590 | #ifndef PM4_MEC_WRITE_DATA_DEFINED |
591 | #define PM4_MEC_WRITE_DATA_DEFINED |
592 | |
593 | enum WRITE_DATA_dst_sel_enum { |
594 | dst_sel___write_data__mem_mapped_register = 0, |
595 | dst_sel___write_data__tc_l2 = 2, |
596 | dst_sel___write_data__gds = 3, |
597 | dst_sel___write_data__memory = 5, |
598 | dst_sel___write_data__memory_mapped_adc_persistent_state = 6, |
599 | }; |
600 | |
601 | enum WRITE_DATA_addr_incr_enum { |
602 | addr_incr___write_data__increment_address = 0, |
603 | addr_incr___write_data__do_not_increment_address = 1 |
604 | }; |
605 | |
606 | enum WRITE_DATA_wr_confirm_enum { |
607 | wr_confirm___write_data__do_not_wait_for_write_confirmation = 0, |
608 | wr_confirm___write_data__wait_for_write_confirmation = 1 |
609 | }; |
610 | |
611 | enum WRITE_DATA_cache_policy_enum { |
612 | cache_policy___write_data__lru = 0, |
613 | cache_policy___write_data__stream = 1 |
614 | }; |
615 | |
616 | |
617 | struct pm4_mec_write_data_mmio { |
618 | union { |
619 | union PM4_MES_TYPE_3_HEADER ; /*header */ |
620 | unsigned int ordinal1; |
621 | }; |
622 | |
623 | union { |
624 | struct { |
625 | unsigned int reserved1:8; |
626 | unsigned int dst_sel:4; |
627 | unsigned int reserved2:4; |
628 | unsigned int addr_incr:1; |
629 | unsigned int reserved3:2; |
630 | unsigned int resume_vf:1; |
631 | unsigned int wr_confirm:1; |
632 | unsigned int reserved4:4; |
633 | unsigned int cache_policy:2; |
634 | unsigned int reserved5:5; |
635 | } bitfields2; |
636 | unsigned int ordinal2; |
637 | }; |
638 | |
639 | union { |
640 | struct { |
641 | unsigned int dst_mmreg_addr:18; |
642 | unsigned int reserved6:14; |
643 | } bitfields3; |
644 | unsigned int ordinal3; |
645 | }; |
646 | |
647 | uint32_t reserved7; |
648 | |
649 | uint32_t data; |
650 | |
651 | }; |
652 | |
653 | #endif |
654 | |
655 | enum { |
656 | CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 |
657 | }; |
658 | #endif |
659 | |
660 | |