1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef F32_MES_PM4_PACKETS_H
25#define F32_MES_PM4_PACKETS_H
26
27#ifndef PM4_MES_HEADER_DEFINED
28#define PM4_MES_HEADER_DEFINED
29union PM4_MES_TYPE_3_HEADER {
30 struct {
31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < Number of DWORDS - 1 in the
34 * information body
35 */
36 uint32_t type : 2; /* < packet identifier
37 * It should be 3 for type 3 packets
38 */
39 };
40 uint32_t u32All;
41};
42#endif /* PM4_MES_HEADER_DEFINED */
43
44/*--------------------MES_SET_RESOURCES--------------------*/
45
46#ifndef PM4_MES_SET_RESOURCES_DEFINED
47#define PM4_MES_SET_RESOURCES_DEFINED
48enum mes_set_resources_queue_type_enum {
49 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
50 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
51 queue_type__mes_set_resources__hsa_debug_interface_queue = 4
52};
53
54
55struct pm4_mes_set_resources {
56 union {
57 union PM4_MES_TYPE_3_HEADER header; /* header */
58 uint32_t ordinal1;
59 };
60
61 union {
62 struct {
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
65 uint32_t reserved1:5;
66 enum mes_set_resources_queue_type_enum queue_type:3;
67 } bitfields2;
68 uint32_t ordinal2;
69 };
70
71 uint32_t queue_mask_lo;
72 uint32_t queue_mask_hi;
73 uint32_t gws_mask_lo;
74 uint32_t gws_mask_hi;
75
76 union {
77 struct {
78 uint32_t oac_mask:16;
79 uint32_t reserved2:16;
80 } bitfields7;
81 uint32_t ordinal7;
82 };
83
84 union {
85 struct {
86 uint32_t gds_heap_base:6;
87 uint32_t reserved3:5;
88 uint32_t gds_heap_size:6;
89 uint32_t reserved4:15;
90 } bitfields8;
91 uint32_t ordinal8;
92 };
93
94};
95#endif
96
97/*--------------------MES_RUN_LIST--------------------*/
98
99#ifndef PM4_MES_RUN_LIST_DEFINED
100#define PM4_MES_RUN_LIST_DEFINED
101
102struct pm4_mes_runlist {
103 union {
104 union PM4_MES_TYPE_3_HEADER header; /* header */
105 uint32_t ordinal1;
106 };
107
108 union {
109 struct {
110 uint32_t reserved1:2;
111 uint32_t ib_base_lo:30;
112 } bitfields2;
113 uint32_t ordinal2;
114 };
115
116 union {
117 struct {
118 uint32_t ib_base_hi:16;
119 uint32_t reserved2:16;
120 } bitfields3;
121 uint32_t ordinal3;
122 };
123
124 union {
125 struct {
126 uint32_t ib_size:20;
127 uint32_t chain:1;
128 uint32_t offload_polling:1;
129 uint32_t reserved2:1;
130 uint32_t valid:1;
131 uint32_t process_cnt:4;
132 uint32_t reserved3:4;
133 } bitfields4;
134 uint32_t ordinal4;
135 };
136
137};
138#endif
139
140/*--------------------MES_MAP_PROCESS--------------------*/
141
142#ifndef PM4_MES_MAP_PROCESS_DEFINED
143#define PM4_MES_MAP_PROCESS_DEFINED
144
145struct pm4_mes_map_process {
146 union {
147 union PM4_MES_TYPE_3_HEADER header; /* header */
148 uint32_t ordinal1;
149 };
150
151 union {
152 struct {
153 uint32_t pasid:16;
154 uint32_t reserved1:8;
155 uint32_t diq_enable:1;
156 uint32_t process_quantum:7;
157 } bitfields2;
158 uint32_t ordinal2;
159 };
160
161 union {
162 struct {
163 uint32_t page_table_base:28;
164 uint32_t reserved3:4;
165 } bitfields3;
166 uint32_t ordinal3;
167 };
168
169 uint32_t reserved;
170
171 uint32_t sh_mem_bases;
172 uint32_t sh_mem_config;
173 uint32_t sh_mem_ape1_base;
174 uint32_t sh_mem_ape1_limit;
175
176 uint32_t sh_hidden_private_base_vmid;
177
178 uint32_t reserved2;
179 uint32_t reserved3;
180
181 uint32_t gds_addr_lo;
182 uint32_t gds_addr_hi;
183
184 union {
185 struct {
186 uint32_t num_gws:6;
187 uint32_t reserved4:2;
188 uint32_t num_oac:4;
189 uint32_t reserved5:4;
190 uint32_t gds_size:6;
191 uint32_t num_queues:10;
192 } bitfields10;
193 uint32_t ordinal10;
194 };
195
196 uint32_t completion_signal_lo;
197 uint32_t completion_signal_hi;
198
199};
200
201#endif
202
203/*--------------------MES_MAP_QUEUES--------------------*/
204
205#ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
206#define PM4_MES_MAP_QUEUES_VI_DEFINED
207enum mes_map_queues_queue_sel_vi_enum {
208 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
209queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
210};
211
212enum mes_map_queues_queue_type_vi_enum {
213 queue_type__mes_map_queues__normal_compute_vi = 0,
214 queue_type__mes_map_queues__debug_interface_queue_vi = 1,
215 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
216queue_type__mes_map_queues__low_latency_static_queue_vi = 3
217};
218
219enum mes_map_queues_alloc_format_vi_enum {
220 alloc_format__mes_map_queues__one_per_pipe_vi = 0,
221alloc_format__mes_map_queues__all_on_one_pipe_vi = 1
222};
223
224enum mes_map_queues_engine_sel_vi_enum {
225 engine_sel__mes_map_queues__compute_vi = 0,
226 engine_sel__mes_map_queues__sdma0_vi = 2,
227 engine_sel__mes_map_queues__sdma1_vi = 3
228};
229
230
231struct pm4_mes_map_queues {
232 union {
233 union PM4_MES_TYPE_3_HEADER header; /* header */
234 uint32_t ordinal1;
235 };
236
237 union {
238 struct {
239 uint32_t reserved1:4;
240 enum mes_map_queues_queue_sel_vi_enum queue_sel:2;
241 uint32_t reserved2:15;
242 enum mes_map_queues_queue_type_vi_enum queue_type:3;
243 enum mes_map_queues_alloc_format_vi_enum alloc_format:2;
244 enum mes_map_queues_engine_sel_vi_enum engine_sel:3;
245 uint32_t num_queues:3;
246 } bitfields2;
247 uint32_t ordinal2;
248 };
249
250 union {
251 struct {
252 uint32_t reserved3:1;
253 uint32_t check_disable:1;
254 uint32_t doorbell_offset:21;
255 uint32_t reserved4:3;
256 uint32_t queue:6;
257 } bitfields3;
258 uint32_t ordinal3;
259 };
260
261 uint32_t mqd_addr_lo;
262 uint32_t mqd_addr_hi;
263 uint32_t wptr_addr_lo;
264 uint32_t wptr_addr_hi;
265};
266#endif
267
268/*--------------------MES_QUERY_STATUS--------------------*/
269
270#ifndef PM4_MES_QUERY_STATUS_DEFINED
271#define PM4_MES_QUERY_STATUS_DEFINED
272enum mes_query_status_interrupt_sel_enum {
273 interrupt_sel__mes_query_status__completion_status = 0,
274 interrupt_sel__mes_query_status__process_status = 1,
275 interrupt_sel__mes_query_status__queue_status = 2
276};
277
278enum mes_query_status_command_enum {
279 command__mes_query_status__interrupt_only = 0,
280 command__mes_query_status__fence_only_immediate = 1,
281 command__mes_query_status__fence_only_after_write_ack = 2,
282 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
283};
284
285enum mes_query_status_engine_sel_enum {
286 engine_sel__mes_query_status__compute = 0,
287 engine_sel__mes_query_status__sdma0_queue = 2,
288 engine_sel__mes_query_status__sdma1_queue = 3
289};
290
291struct pm4_mes_query_status {
292 union {
293 union PM4_MES_TYPE_3_HEADER header; /* header */
294 uint32_t ordinal1;
295 };
296
297 union {
298 struct {
299 uint32_t context_id:28;
300 enum mes_query_status_interrupt_sel_enum
301 interrupt_sel:2;
302 enum mes_query_status_command_enum command:2;
303 } bitfields2;
304 uint32_t ordinal2;
305 };
306
307 union {
308 struct {
309 uint32_t pasid:16;
310 uint32_t reserved1:16;
311 } bitfields3a;
312 struct {
313 uint32_t reserved2:2;
314 uint32_t doorbell_offset:21;
315 uint32_t reserved3:2;
316 enum mes_query_status_engine_sel_enum engine_sel:3;
317 uint32_t reserved4:4;
318 } bitfields3b;
319 uint32_t ordinal3;
320 };
321
322 uint32_t addr_lo;
323 uint32_t addr_hi;
324 uint32_t data_lo;
325 uint32_t data_hi;
326};
327#endif
328
329/*--------------------MES_UNMAP_QUEUES--------------------*/
330
331#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
332#define PM4_MES_UNMAP_QUEUES_DEFINED
333enum mes_unmap_queues_action_enum {
334 action__mes_unmap_queues__preempt_queues = 0,
335 action__mes_unmap_queues__reset_queues = 1,
336 action__mes_unmap_queues__disable_process_queues = 2,
337 action__mes_unmap_queues__reserved = 3
338};
339
340enum mes_unmap_queues_queue_sel_enum {
341 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
342 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
343 queue_sel__mes_unmap_queues__unmap_all_queues = 2,
344 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
345};
346
347enum mes_unmap_queues_engine_sel_enum {
348 engine_sel__mes_unmap_queues__compute = 0,
349 engine_sel__mes_unmap_queues__sdma0 = 2,
350 engine_sel__mes_unmap_queues__sdmal = 3
351};
352
353struct pm4_mes_unmap_queues {
354 union {
355 union PM4_MES_TYPE_3_HEADER header; /* header */
356 uint32_t ordinal1;
357 };
358
359 union {
360 struct {
361 enum mes_unmap_queues_action_enum action:2;
362 uint32_t reserved1:2;
363 enum mes_unmap_queues_queue_sel_enum queue_sel:2;
364 uint32_t reserved2:20;
365 enum mes_unmap_queues_engine_sel_enum engine_sel:3;
366 uint32_t num_queues:3;
367 } bitfields2;
368 uint32_t ordinal2;
369 };
370
371 union {
372 struct {
373 uint32_t pasid:16;
374 uint32_t reserved3:16;
375 } bitfields3a;
376 struct {
377 uint32_t reserved4:2;
378 uint32_t doorbell_offset0:21;
379 uint32_t reserved5:9;
380 } bitfields3b;
381 uint32_t ordinal3;
382 };
383
384 union {
385 struct {
386 uint32_t reserved6:2;
387 uint32_t doorbell_offset1:21;
388 uint32_t reserved7:9;
389 } bitfields4;
390 uint32_t ordinal4;
391 };
392
393 union {
394 struct {
395 uint32_t reserved8:2;
396 uint32_t doorbell_offset2:21;
397 uint32_t reserved9:9;
398 } bitfields5;
399 uint32_t ordinal5;
400 };
401
402 union {
403 struct {
404 uint32_t reserved10:2;
405 uint32_t doorbell_offset3:21;
406 uint32_t reserved11:9;
407 } bitfields6;
408 uint32_t ordinal6;
409 };
410};
411#endif
412
413#ifndef PM4_MEC_RELEASE_MEM_DEFINED
414#define PM4_MEC_RELEASE_MEM_DEFINED
415enum RELEASE_MEM_event_index_enum {
416 event_index___release_mem__end_of_pipe = 5,
417 event_index___release_mem__shader_done = 6
418};
419
420enum RELEASE_MEM_cache_policy_enum {
421 cache_policy___release_mem__lru = 0,
422 cache_policy___release_mem__stream = 1,
423 cache_policy___release_mem__bypass = 2
424};
425
426enum RELEASE_MEM_dst_sel_enum {
427 dst_sel___release_mem__memory_controller = 0,
428 dst_sel___release_mem__tc_l2 = 1,
429 dst_sel___release_mem__queue_write_pointer_register = 2,
430 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
431};
432
433enum RELEASE_MEM_int_sel_enum {
434 int_sel___release_mem__none = 0,
435 int_sel___release_mem__send_interrupt_only = 1,
436 int_sel___release_mem__send_interrupt_after_write_confirm = 2,
437 int_sel___release_mem__send_data_after_write_confirm = 3
438};
439
440enum RELEASE_MEM_data_sel_enum {
441 data_sel___release_mem__none = 0,
442 data_sel___release_mem__send_32_bit_low = 1,
443 data_sel___release_mem__send_64_bit_data = 2,
444 data_sel___release_mem__send_gpu_clock_counter = 3,
445 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
446 data_sel___release_mem__store_gds_data_to_memory = 5
447};
448
449struct pm4_mec_release_mem {
450 union {
451 union PM4_MES_TYPE_3_HEADER header; /*header */
452 unsigned int ordinal1;
453 };
454
455 union {
456 struct {
457 unsigned int event_type:6;
458 unsigned int reserved1:2;
459 enum RELEASE_MEM_event_index_enum event_index:4;
460 unsigned int tcl1_vol_action_ena:1;
461 unsigned int tc_vol_action_ena:1;
462 unsigned int reserved2:1;
463 unsigned int tc_wb_action_ena:1;
464 unsigned int tcl1_action_ena:1;
465 unsigned int tc_action_ena:1;
466 unsigned int reserved3:6;
467 unsigned int atc:1;
468 enum RELEASE_MEM_cache_policy_enum cache_policy:2;
469 unsigned int reserved4:5;
470 } bitfields2;
471 unsigned int ordinal2;
472 };
473
474 union {
475 struct {
476 unsigned int reserved5:16;
477 enum RELEASE_MEM_dst_sel_enum dst_sel:2;
478 unsigned int reserved6:6;
479 enum RELEASE_MEM_int_sel_enum int_sel:3;
480 unsigned int reserved7:2;
481 enum RELEASE_MEM_data_sel_enum data_sel:3;
482 } bitfields3;
483 unsigned int ordinal3;
484 };
485
486 union {
487 struct {
488 unsigned int reserved8:2;
489 unsigned int address_lo_32b:30;
490 } bitfields4;
491 struct {
492 unsigned int reserved9:3;
493 unsigned int address_lo_64b:29;
494 } bitfields5;
495 unsigned int ordinal4;
496 };
497
498 unsigned int address_hi;
499
500 unsigned int data_lo;
501
502 unsigned int data_hi;
503};
504#endif
505
506enum {
507 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
508};
509
510#endif
511