1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | /** |
27 | * This file defines external dependencies of Display Core. |
28 | */ |
29 | |
30 | #ifndef __DM_SERVICES_H__ |
31 | |
32 | #define __DM_SERVICES_H__ |
33 | |
34 | /* TODO: remove when DC is complete. */ |
35 | #include "dm_services_types.h" |
36 | #include "logger_interface.h" |
37 | #include "link_service_types.h" |
38 | |
39 | #undef DEPRECATED |
40 | |
41 | struct dmub_srv; |
42 | struct dc_dmub_srv; |
43 | union dmub_rb_cmd; |
44 | |
45 | irq_handler_idx dm_register_interrupt( |
46 | struct dc_context *ctx, |
47 | struct dc_interrupt_params *int_params, |
48 | interrupt_handler ih, |
49 | void *handler_args); |
50 | |
51 | /* |
52 | * |
53 | * GPU registers access |
54 | * |
55 | */ |
56 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, |
57 | const char *func_name); |
58 | |
59 | /* enable for debugging new code, this adds 50k to the driver size. */ |
60 | /* #define DM_CHECK_ADDR_0 */ |
61 | |
62 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, |
63 | uint32_t value, const char *func_name); |
64 | |
65 | #define dm_read_reg(ctx, address) \ |
66 | dm_read_reg_func(ctx, address, __func__) |
67 | |
68 | #define dm_write_reg(ctx, address, value) \ |
69 | dm_write_reg_func(ctx, address, value, __func__) |
70 | |
71 | static inline uint32_t dm_read_index_reg( |
72 | const struct dc_context *ctx, |
73 | enum cgs_ind_reg addr_space, |
74 | uint32_t index) |
75 | { |
76 | return cgs_read_ind_register(ctx->cgs_device, addr_space, index); |
77 | } |
78 | |
79 | static inline void dm_write_index_reg( |
80 | const struct dc_context *ctx, |
81 | enum cgs_ind_reg addr_space, |
82 | uint32_t index, |
83 | uint32_t value) |
84 | { |
85 | cgs_write_ind_register(ctx->cgs_device, addr_space, index, value); |
86 | } |
87 | |
88 | static inline uint32_t get_reg_field_value_ex( |
89 | uint32_t reg_value, |
90 | uint32_t mask, |
91 | uint8_t shift) |
92 | { |
93 | return (mask & reg_value) >> shift; |
94 | } |
95 | |
96 | #define get_reg_field_value(reg_value, reg_name, reg_field)\ |
97 | get_reg_field_value_ex(\ |
98 | (reg_value),\ |
99 | reg_name ## __ ## reg_field ## _MASK,\ |
100 | reg_name ## __ ## reg_field ## __SHIFT) |
101 | |
102 | static inline uint32_t set_reg_field_value_ex( |
103 | uint32_t reg_value, |
104 | uint32_t value, |
105 | uint32_t mask, |
106 | uint8_t shift) |
107 | { |
108 | ASSERT(mask != 0); |
109 | return (reg_value & ~mask) | (mask & (value << shift)); |
110 | } |
111 | |
112 | #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ |
113 | (reg_value) = set_reg_field_value_ex(\ |
114 | (reg_value),\ |
115 | (value),\ |
116 | reg_name ## __ ## reg_field ## _MASK,\ |
117 | reg_name ## __ ## reg_field ## __SHIFT) |
118 | |
119 | uint32_t generic_reg_set_ex(const struct dc_context *ctx, |
120 | uint32_t addr, uint32_t reg_val, int n, |
121 | uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); |
122 | |
123 | uint32_t generic_reg_update_ex(const struct dc_context *ctx, |
124 | uint32_t addr, int n, |
125 | uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); |
126 | |
127 | struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub); |
128 | void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv); |
129 | |
130 | void reg_sequence_start_gather(const struct dc_context *ctx); |
131 | void reg_sequence_start_execute(const struct dc_context *ctx); |
132 | void reg_sequence_wait_done(const struct dc_context *ctx); |
133 | |
134 | #define FD(reg_field) reg_field ## __SHIFT, \ |
135 | reg_field ## _MASK |
136 | |
137 | /* |
138 | * return number of poll before condition is met |
139 | * return 0 if condition is not meet after specified time out tries |
140 | */ |
141 | void generic_reg_wait(const struct dc_context *ctx, |
142 | uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, |
143 | unsigned int delay_between_poll_us, unsigned int time_out_num_tries, |
144 | const char *func_name, int line); |
145 | |
146 | unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...); |
147 | |
148 | /* These macros need to be used with soc15 registers in order to retrieve |
149 | * the actual offset. |
150 | */ |
151 | #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ |
152 | dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) |
153 | |
154 | #define dm_read_reg_soc15(ctx, reg, inst_offset) \ |
155 | dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) |
156 | |
157 | #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ |
158 | generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ |
159 | n, __VA_ARGS__) |
160 | |
161 | #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ |
162 | generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ |
163 | n, __VA_ARGS__) |
164 | |
165 | #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ |
166 | get_reg_field_value_ex(\ |
167 | (reg_value),\ |
168 | block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ |
169 | block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) |
170 | |
171 | #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ |
172 | (reg_value) = set_reg_field_value_ex(\ |
173 | (reg_value),\ |
174 | (value),\ |
175 | block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ |
176 | block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) |
177 | |
178 | /************************************** |
179 | * Power Play (PP) interfaces |
180 | **************************************/ |
181 | |
182 | /* Gets valid clocks levels from pplib |
183 | * |
184 | * input: clk_type - display clk / sclk / mem clk |
185 | * |
186 | * output: array of valid clock levels for given type in ascending order, |
187 | * with invalid levels filtered out |
188 | * |
189 | */ |
190 | bool dm_pp_get_clock_levels_by_type( |
191 | const struct dc_context *ctx, |
192 | enum dm_pp_clock_type clk_type, |
193 | struct dm_pp_clock_levels *clk_level_info); |
194 | |
195 | bool dm_pp_get_clock_levels_by_type_with_latency( |
196 | const struct dc_context *ctx, |
197 | enum dm_pp_clock_type clk_type, |
198 | struct dm_pp_clock_levels_with_latency *clk_level_info); |
199 | |
200 | bool dm_pp_get_clock_levels_by_type_with_voltage( |
201 | const struct dc_context *ctx, |
202 | enum dm_pp_clock_type clk_type, |
203 | struct dm_pp_clock_levels_with_voltage *clk_level_info); |
204 | |
205 | bool dm_pp_notify_wm_clock_changes( |
206 | const struct dc_context *ctx, |
207 | struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); |
208 | |
209 | void dm_pp_get_funcs(struct dc_context *ctx, |
210 | struct pp_smu_funcs *funcs); |
211 | |
212 | /* DAL calls this function to notify PP about completion of Mode Set. |
213 | * For PP it means that current DCE clocks are those which were returned |
214 | * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. |
215 | * |
216 | * If the clocks are higher than before, then PP does nothing. |
217 | * |
218 | * If the clocks are lower than before, then PP reduces the voltage. |
219 | * |
220 | * \returns true - call is successful |
221 | * false - call failed |
222 | */ |
223 | bool dm_pp_apply_display_requirements( |
224 | const struct dc_context *ctx, |
225 | const struct dm_pp_display_configuration *pp_display_cfg); |
226 | |
227 | bool dm_pp_apply_power_level_change_request( |
228 | const struct dc_context *ctx, |
229 | struct dm_pp_power_level_change_request *level_change_req); |
230 | |
231 | bool dm_pp_apply_clock_for_voltage_request( |
232 | const struct dc_context *ctx, |
233 | struct dm_pp_clock_for_voltage_req *clock_for_voltage_req); |
234 | |
235 | bool dm_pp_get_static_clocks( |
236 | const struct dc_context *ctx, |
237 | struct dm_pp_static_clock_info *static_clk_info); |
238 | |
239 | /****** end of PP interfaces ******/ |
240 | |
241 | struct persistent_data_flag { |
242 | bool save_per_link; |
243 | bool save_per_edid; |
244 | }; |
245 | |
246 | bool dm_query_extended_brightness_caps |
247 | (struct dc_context *ctx, enum dm_acpi_display_type display, |
248 | struct dm_acpi_atif_backlight_caps *pCaps); |
249 | |
250 | bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); |
251 | |
252 | /* |
253 | * |
254 | * print-out services |
255 | * |
256 | */ |
257 | #define dm_log_to_buffer(buffer, size, fmt, args)\ |
258 | vsnprintf(buffer, size, fmt, args) |
259 | |
260 | static inline unsigned long long dm_get_timestamp(struct dc_context *ctx) |
261 | { |
262 | return ktime_get_raw_ns(); |
263 | } |
264 | |
265 | unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx, |
266 | unsigned long long current_time_stamp, |
267 | unsigned long long last_time_stamp); |
268 | |
269 | /* |
270 | * performance tracing |
271 | */ |
272 | void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx); |
273 | |
274 | #define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX) |
275 | #define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX) |
276 | |
277 | /* |
278 | * DMUB Interfaces |
279 | */ |
280 | bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); |
281 | bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); |
282 | |
283 | /* |
284 | * Debug and verification hooks |
285 | */ |
286 | |
287 | void dm_dtn_log_begin(struct dc_context *ctx, |
288 | struct dc_log_buffer_ctx *log_ctx); |
289 | void dm_dtn_log_append_v(struct dc_context *ctx, |
290 | struct dc_log_buffer_ctx *log_ctx, |
291 | const char *msg, ...); |
292 | void dm_dtn_log_end(struct dc_context *ctx, |
293 | struct dc_log_buffer_ctx *log_ctx); |
294 | |
295 | char *dce_version_to_string(const int version); |
296 | |
297 | #endif /* __DM_SERVICES_H__ */ |
298 | |