1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DAL_ASIC_ID_H__ |
27 | #define __DAL_ASIC_ID_H__ |
28 | |
29 | /* |
30 | * ASIC internal revision ID |
31 | */ |
32 | |
33 | /* DCE80 (based on ci_id.h in Perforce) */ |
34 | #define CI_BONAIRE_M_A0 0x14 |
35 | #define CI_BONAIRE_M_A1 0x15 |
36 | #define CI_HAWAII_P_A0 0x28 |
37 | |
38 | #define CI_UNKNOWN 0xFF |
39 | |
40 | #define ASIC_REV_IS_BONAIRE_M(rev) \ |
41 | ((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0)) |
42 | |
43 | #define ASIC_REV_IS_HAWAII_P(rev) \ |
44 | (rev >= CI_HAWAII_P_A0) |
45 | |
46 | /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */ |
47 | #define KV_SPECTRE_A0 0x01 |
48 | |
49 | /* KV2 with Spooky GFX core, including downgraded from Spectre core, |
50 | * 3-4-1-1 (CU-Pix-Primitive-RB) */ |
51 | #define KV_SPOOKY_A0 0x41 |
52 | |
53 | /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ |
54 | #define KB_KALINDI_A0 0x81 |
55 | |
56 | /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ |
57 | #define KB_KALINDI_A1 0x82 |
58 | |
59 | /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ |
60 | #define BV_KALINDI_A2 0x85 |
61 | |
62 | /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ |
63 | #define ML_GODAVARI_A0 0xA1 |
64 | |
65 | /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ |
66 | #define ML_GODAVARI_A1 0xA2 |
67 | |
68 | #define KV_UNKNOWN 0xFF |
69 | |
70 | #define ASIC_REV_IS_KALINDI(rev) \ |
71 | ((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN)) |
72 | |
73 | #define ASIC_REV_IS_BHAVANI(rev) \ |
74 | ((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0)) |
75 | |
76 | #define ASIC_REV_IS_GODAVARI(rev) \ |
77 | ((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN)) |
78 | |
79 | /* VI Family */ |
80 | /* DCE10 */ |
81 | #define VI_TONGA_P_A0 20 |
82 | #define VI_TONGA_P_A1 21 |
83 | #define VI_FIJI_P_A0 60 |
84 | |
85 | /* DCE112 */ |
86 | #define VI_POLARIS10_P_A0 80 |
87 | #define VI_POLARIS11_M_A0 90 |
88 | #define VI_POLARIS12_V_A0 100 |
89 | #define VI_VEGAM_A0 110 |
90 | |
91 | #define VI_UNKNOWN 0xFF |
92 | |
93 | #define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \ |
94 | (eChipRev < 40)) |
95 | #define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \ |
96 | (eChipRev < 80)) |
97 | |
98 | #define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \ |
99 | (eChipRev < VI_POLARIS11_M_A0)) |
100 | #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \ |
101 | (eChipRev < VI_POLARIS12_V_A0)) |
102 | #define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \ |
103 | (eChipRev < VI_VEGAM_A0)) |
104 | #define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0) |
105 | |
106 | /* DCE11 */ |
107 | #define CZ_CARRIZO_A0 0x01 |
108 | |
109 | #define STONEY_A0 0x61 |
110 | #define CZ_UNKNOWN 0xFF |
111 | |
112 | #define ASIC_REV_IS_STONEY(rev) \ |
113 | ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) |
114 | |
115 | /* DCE12 */ |
116 | #define AI_UNKNOWN 0xFF |
117 | |
118 | #define AI_GREENLAND_P_A0 1 |
119 | #define AI_GREENLAND_P_A1 2 |
120 | #define AI_UNKNOWN 0xFF |
121 | |
122 | #define AI_VEGA12_P_A0 20 |
123 | #define AI_VEGA20_P_A0 40 |
124 | #define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0) |
125 | #define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0) |
126 | |
127 | #define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0)) |
128 | #define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) |
129 | |
130 | /* DCN1_0 */ |
131 | #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ |
132 | #define RAVEN_A0 0x01 |
133 | #define RAVEN_B0 0x21 |
134 | #define PICASSO_A0 0x41 |
135 | #if defined(CONFIG_DRM_AMD_DC_DCN1_01) |
136 | /* DCN1_01 */ |
137 | #define RAVEN2_A0 0x81 |
138 | #endif |
139 | #define RAVEN_UNKNOWN 0xFF |
140 | |
141 | #if defined(CONFIG_DRM_AMD_DC_DCN1_01) |
142 | #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0)) |
143 | #endif /* DCN1_01 */ |
144 | #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) |
145 | #define RAVEN1_F0 0xF0 |
146 | #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) |
147 | |
148 | |
149 | #define FAMILY_RV 142 /* DCN 1*/ |
150 | |
151 | /* |
152 | * ASIC chip ID |
153 | */ |
154 | /* DCE80 */ |
155 | #define DEVICE_ID_KALINDI_9834 0x9834 |
156 | #define DEVICE_ID_TEMASH_9839 0x9839 |
157 | #define DEVICE_ID_TEMASH_983D 0x983D |
158 | |
159 | /* Asic Family IDs for different asic family. */ |
160 | #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */ |
161 | #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */ |
162 | #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ |
163 | #define FAMILY_CZ 135 /* Carrizo */ |
164 | |
165 | #define FAMILY_AI 141 |
166 | |
167 | #define FAMILY_UNKNOWN 0xFF |
168 | |
169 | |
170 | |
171 | #endif /* __DAL_ASIC_ID_H__ */ |
172 | |