1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DAL_DPCD_DEFS_H__ |
27 | #define __DAL_DPCD_DEFS_H__ |
28 | |
29 | #include <drm/display/drm_dp_helper.h> |
30 | #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h |
31 | #define DP_SINK_HW_REVISION_START 0x409 |
32 | #endif |
33 | |
34 | enum dpcd_revision { |
35 | DPCD_REV_10 = 0x10, |
36 | DPCD_REV_11 = 0x11, |
37 | DPCD_REV_12 = 0x12, |
38 | DPCD_REV_13 = 0x13, |
39 | DPCD_REV_14 = 0x14 |
40 | }; |
41 | |
42 | /* these are the types stored at DOWNSTREAMPORT_PRESENT */ |
43 | enum dpcd_downstream_port_type { |
44 | DOWNSTREAM_DP = 0, |
45 | DOWNSTREAM_VGA, |
46 | DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */ |
47 | DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ |
48 | }; |
49 | |
50 | enum dpcd_link_test_patterns { |
51 | LINK_TEST_PATTERN_NONE = 0, |
52 | LINK_TEST_PATTERN_COLOR_RAMP, |
53 | LINK_TEST_PATTERN_VERTICAL_BARS, |
54 | LINK_TEST_PATTERN_COLOR_SQUARES |
55 | }; |
56 | |
57 | enum dpcd_test_color_format { |
58 | TEST_COLOR_FORMAT_RGB = 0, |
59 | TEST_COLOR_FORMAT_YCBCR422, |
60 | TEST_COLOR_FORMAT_YCBCR444 |
61 | }; |
62 | |
63 | enum dpcd_test_bit_depth { |
64 | TEST_BIT_DEPTH_6 = 0, |
65 | TEST_BIT_DEPTH_8, |
66 | TEST_BIT_DEPTH_10, |
67 | TEST_BIT_DEPTH_12, |
68 | TEST_BIT_DEPTH_16 |
69 | }; |
70 | |
71 | /* PHY (encoder) test patterns |
72 | The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) |
73 | */ |
74 | enum dpcd_phy_test_patterns { |
75 | PHY_TEST_PATTERN_NONE = 0, |
76 | PHY_TEST_PATTERN_D10_2, |
77 | PHY_TEST_PATTERN_SYMBOL_ERROR, |
78 | PHY_TEST_PATTERN_PRBS7, |
79 | PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ |
80 | PHY_TEST_PATTERN_CP2520_1, |
81 | PHY_TEST_PATTERN_CP2520_2, |
82 | PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */ |
83 | PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8, |
84 | PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10, |
85 | PHY_TEST_PATTERN_PRBS9 = 0x18, |
86 | PHY_TEST_PATTERN_PRBS11 = 0x20, |
87 | PHY_TEST_PATTERN_PRBS15 = 0x28, |
88 | PHY_TEST_PATTERN_PRBS23 = 0x30, |
89 | PHY_TEST_PATTERN_PRBS31 = 0x38, |
90 | PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40, |
91 | PHY_TEST_PATTERN_SQUARE = 0x48, |
92 | PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49, |
93 | PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A, |
94 | PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B, |
95 | }; |
96 | |
97 | enum dpcd_test_dyn_range { |
98 | TEST_DYN_RANGE_VESA = 0, |
99 | TEST_DYN_RANGE_CEA |
100 | }; |
101 | |
102 | enum dpcd_audio_test_pattern { |
103 | AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ |
104 | AUDIO_TEST_PATTERN_SAWTOOTH |
105 | }; |
106 | |
107 | enum dpcd_audio_sampling_rate { |
108 | AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ |
109 | AUDIO_SAMPLING_RATE_44_1KHZ, |
110 | AUDIO_SAMPLING_RATE_48KHZ, |
111 | AUDIO_SAMPLING_RATE_88_2KHZ, |
112 | AUDIO_SAMPLING_RATE_96KHZ, |
113 | AUDIO_SAMPLING_RATE_176_4KHZ, |
114 | AUDIO_SAMPLING_RATE_192KHZ |
115 | }; |
116 | |
117 | enum dpcd_audio_channels { |
118 | AUDIO_CHANNELS_1 = 0,/* direct HW translation */ |
119 | AUDIO_CHANNELS_2, |
120 | AUDIO_CHANNELS_3, |
121 | AUDIO_CHANNELS_4, |
122 | AUDIO_CHANNELS_5, |
123 | AUDIO_CHANNELS_6, |
124 | AUDIO_CHANNELS_7, |
125 | AUDIO_CHANNELS_8, |
126 | |
127 | AUDIO_CHANNELS_COUNT |
128 | }; |
129 | |
130 | enum dpcd_audio_test_pattern_periods { |
131 | DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ |
132 | DPCD_AUDIO_TEST_PATTERN_PERIOD_3, |
133 | DPCD_AUDIO_TEST_PATTERN_PERIOD_6, |
134 | DPCD_AUDIO_TEST_PATTERN_PERIOD_12, |
135 | DPCD_AUDIO_TEST_PATTERN_PERIOD_24, |
136 | DPCD_AUDIO_TEST_PATTERN_PERIOD_48, |
137 | DPCD_AUDIO_TEST_PATTERN_PERIOD_96, |
138 | DPCD_AUDIO_TEST_PATTERN_PERIOD_192, |
139 | DPCD_AUDIO_TEST_PATTERN_PERIOD_384, |
140 | DPCD_AUDIO_TEST_PATTERN_PERIOD_768, |
141 | DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 |
142 | }; |
143 | |
144 | /* This enum is for programming DPCD TRAINING_PATTERN_SET */ |
145 | enum dpcd_training_patterns { |
146 | DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ |
147 | DPCD_TRAINING_PATTERN_1, |
148 | DPCD_TRAINING_PATTERN_2, |
149 | DPCD_TRAINING_PATTERN_3, |
150 | DPCD_TRAINING_PATTERN_4 = 7, |
151 | DPCD_128b_132b_TPS1 = 1, |
152 | DPCD_128b_132b_TPS2 = 2, |
153 | DPCD_128b_132b_TPS2_CDS = 3, |
154 | }; |
155 | |
156 | /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus |
157 | It defines the possible PSR states. */ |
158 | enum dpcd_psr_sink_states { |
159 | PSR_SINK_STATE_INACTIVE = 0, |
160 | PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, |
161 | PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, |
162 | PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, |
163 | PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, |
164 | PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, |
165 | }; |
166 | |
167 | #define DP_SOURCE_SEQUENCE 0x30c |
168 | #define DP_SOURCE_TABLE_REVISION 0x310 |
169 | #define DP_SOURCE_PAYLOAD_SIZE 0x311 |
170 | #define DP_SOURCE_SINK_CAP 0x317 |
171 | #define DP_SOURCE_BACKLIGHT_LEVEL 0x320 |
172 | #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 |
173 | #define DP_SOURCE_BACKLIGHT_CONTROL 0x32E |
174 | #define DP_SOURCE_BACKLIGHT_ENABLE 0x32F |
175 | #define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340 |
176 | #define DP_SINK_PR_REPLAY_STATUS 0x378 |
177 | #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 |
178 | #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A |
179 | |
180 | #endif /* __DAL_DPCD_DEFS_H__ */ |
181 | |