1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DAL_LINK_SERVICE_TYPES_H__ |
27 | #define __DAL_LINK_SERVICE_TYPES_H__ |
28 | |
29 | #include "grph_object_id.h" |
30 | #include "dal_types.h" |
31 | #include "irq_types.h" |
32 | |
33 | /*struct mst_mgr_callback_object;*/ |
34 | struct ddc; |
35 | struct irq_manager; |
36 | |
37 | enum dp_power_state { |
38 | DP_POWER_STATE_D0 = 1, |
39 | DP_POWER_STATE_D3 |
40 | }; |
41 | |
42 | enum edp_revision { |
43 | /* eDP version 1.1 or lower */ |
44 | EDP_REVISION_11 = 0x00, |
45 | /* eDP version 1.2 */ |
46 | EDP_REVISION_12 = 0x01, |
47 | /* eDP version 1.3 */ |
48 | EDP_REVISION_13 = 0x02 |
49 | }; |
50 | |
51 | enum { |
52 | LINK_RATE_REF_FREQ_IN_KHZ = 27000, /*27MHz*/ |
53 | BITS_PER_DP_BYTE = 10, |
54 | DATA_EFFICIENCY_8b_10b_x10000 = 8000, /* 80% data efficiency */ |
55 | DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 = 97, /* 97% data efficiency when FEC is enabled */ |
56 | DATA_EFFICIENCY_128b_132b_x10000 = 9641, /* 96.71% data efficiency x 99.7% downspread factor */ |
57 | }; |
58 | |
59 | enum lttpr_mode { |
60 | LTTPR_MODE_UNKNOWN, |
61 | LTTPR_MODE_NON_LTTPR, |
62 | LTTPR_MODE_TRANSPARENT, |
63 | LTTPR_MODE_NON_TRANSPARENT, |
64 | }; |
65 | |
66 | struct link_training_settings { |
67 | struct dc_link_settings link_settings; |
68 | |
69 | /* TODO: turn lane settings below into mandatory fields |
70 | * as initial lane configuration |
71 | */ |
72 | enum dc_voltage_swing *voltage_swing; |
73 | enum dc_pre_emphasis *pre_emphasis; |
74 | enum dc_post_cursor2 *post_cursor2; |
75 | bool should_set_fec_ready; |
76 | /* TODO - factor lane_settings out because it changes during LT */ |
77 | union dc_dp_ffe_preset *ffe_preset; |
78 | |
79 | uint16_t cr_pattern_time; |
80 | uint16_t eq_pattern_time; |
81 | uint16_t cds_pattern_time; |
82 | enum dc_dp_training_pattern pattern_for_cr; |
83 | enum dc_dp_training_pattern pattern_for_eq; |
84 | enum dc_dp_training_pattern pattern_for_cds; |
85 | |
86 | uint32_t eq_wait_time_limit; |
87 | uint8_t eq_loop_count_limit; |
88 | uint32_t cds_wait_time_limit; |
89 | |
90 | bool enhanced_framing; |
91 | enum lttpr_mode lttpr_mode; |
92 | |
93 | /* disallow different lanes to have different lane settings */ |
94 | bool disallow_per_lane_settings; |
95 | /* dpcd lane settings will always use the same hw lane settings |
96 | * even if it doesn't match requested lane adjust */ |
97 | bool always_match_dpcd_with_hw_lane_settings; |
98 | |
99 | /***************************************************************** |
100 | * training states - parameters that can change in link training |
101 | *****************************************************************/ |
102 | /* TODO: Move hw_lane_settings and dpcd_lane_settings |
103 | * along with lane adjust, lane align, offset and all |
104 | * other training states into a new structure called |
105 | * training states, so link_training_settings becomes |
106 | * a constant input pre-decided prior to link training. |
107 | * |
108 | * The goal is to strictly decouple link training settings |
109 | * decision making process from link training states to |
110 | * prevent it from messy code practice of changing training |
111 | * decision on the fly. |
112 | */ |
113 | struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX]; |
114 | union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]; |
115 | }; |
116 | |
117 | /*TODO: Move this enum test harness*/ |
118 | /* Test patterns*/ |
119 | enum dp_test_pattern { |
120 | /* Input data is pass through Scrambler |
121 | * and 8b10b Encoder straight to output*/ |
122 | DP_TEST_PATTERN_VIDEO_MODE = 0, |
123 | |
124 | /* phy test patterns*/ |
125 | DP_TEST_PATTERN_PHY_PATTERN_BEGIN, |
126 | DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN, |
127 | DP_TEST_PATTERN_SYMBOL_ERROR, |
128 | DP_TEST_PATTERN_PRBS7, |
129 | DP_TEST_PATTERN_80BIT_CUSTOM, |
130 | DP_TEST_PATTERN_CP2520_1, |
131 | DP_TEST_PATTERN_CP2520_2, |
132 | DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, |
133 | DP_TEST_PATTERN_CP2520_3, |
134 | DP_TEST_PATTERN_128b_132b_TPS1, |
135 | DP_TEST_PATTERN_128b_132b_TPS2, |
136 | DP_TEST_PATTERN_PRBS9, |
137 | DP_TEST_PATTERN_PRBS11, |
138 | DP_TEST_PATTERN_PRBS15, |
139 | DP_TEST_PATTERN_PRBS23, |
140 | DP_TEST_PATTERN_PRBS31, |
141 | DP_TEST_PATTERN_264BIT_CUSTOM, |
142 | DP_TEST_PATTERN_SQUARE_BEGIN, |
143 | DP_TEST_PATTERN_SQUARE = DP_TEST_PATTERN_SQUARE_BEGIN, |
144 | DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED, |
145 | DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED, |
146 | DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED, |
147 | DP_TEST_PATTERN_SQUARE_END = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED, |
148 | |
149 | /* Link Training Patterns */ |
150 | DP_TEST_PATTERN_TRAINING_PATTERN1, |
151 | DP_TEST_PATTERN_TRAINING_PATTERN2, |
152 | DP_TEST_PATTERN_TRAINING_PATTERN3, |
153 | DP_TEST_PATTERN_TRAINING_PATTERN4, |
154 | DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE, |
155 | DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, |
156 | DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, |
157 | |
158 | /* link test patterns*/ |
159 | DP_TEST_PATTERN_COLOR_SQUARES, |
160 | DP_TEST_PATTERN_COLOR_SQUARES_CEA, |
161 | DP_TEST_PATTERN_VERTICAL_BARS, |
162 | DP_TEST_PATTERN_HORIZONTAL_BARS, |
163 | DP_TEST_PATTERN_COLOR_RAMP, |
164 | |
165 | /* audio test patterns*/ |
166 | DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED, |
167 | DP_TEST_PATTERN_AUDIO_SAWTOOTH, |
168 | |
169 | DP_TEST_PATTERN_UNSUPPORTED |
170 | }; |
171 | |
172 | enum dp_test_pattern_color_space { |
173 | DP_TEST_PATTERN_COLOR_SPACE_RGB, |
174 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR601, |
175 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR709, |
176 | DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED |
177 | }; |
178 | |
179 | enum dp_panel_mode { |
180 | /* not required */ |
181 | DP_PANEL_MODE_DEFAULT, |
182 | /* standard mode for eDP */ |
183 | DP_PANEL_MODE_EDP, |
184 | /* external chips specific settings */ |
185 | DP_PANEL_MODE_SPECIAL |
186 | }; |
187 | |
188 | enum dpcd_source_sequence { |
189 | DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG = 1, /*done in apply_single_controller_ctx_to_hw */ |
190 | DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR, /*done in core_link_enable_stream */ |
191 | DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME, /*done in core_link_enable_stream/dcn20_enable_stream */ |
192 | DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE, /*done in perform_link_training_with_retries/dcn20_enable_stream */ |
193 | DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY, /*done in dp_enable_link_phy */ |
194 | DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN, /*done in dp_set_hw_test_pattern */ |
195 | DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM, /*done in dce110_enable_audio_stream */ |
196 | DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_unblank */ |
197 | DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_blank */ |
198 | DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET, /*done in enc1_stream_encoder_dp_blank */ |
199 | DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM, /*done in dce110_disable_audio_stream */ |
200 | DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY, /*done in dp_disable_link_phy */ |
201 | DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE, /*done in dce110_disable_stream */ |
202 | }; |
203 | |
204 | /* DPCD_ADDR_TRAINING_LANEx_SET registers value */ |
205 | union dpcd_training_lane_set { |
206 | struct { |
207 | #if defined(LITTLEENDIAN_CPU) |
208 | uint8_t VOLTAGE_SWING_SET:2; |
209 | uint8_t MAX_SWING_REACHED:1; |
210 | uint8_t PRE_EMPHASIS_SET:2; |
211 | uint8_t MAX_PRE_EMPHASIS_REACHED:1; |
212 | /* following is reserved in DP 1.1 */ |
213 | uint8_t POST_CURSOR2_SET:2; |
214 | #elif defined(BIGENDIAN_CPU) |
215 | uint8_t POST_CURSOR2_SET:2; |
216 | uint8_t MAX_PRE_EMPHASIS_REACHED:1; |
217 | uint8_t PRE_EMPHASIS_SET:2; |
218 | uint8_t MAX_SWING_REACHED:1; |
219 | uint8_t VOLTAGE_SWING_SET:2; |
220 | #else |
221 | #error ARCH not defined! |
222 | #endif |
223 | } bits; |
224 | |
225 | uint8_t raw; |
226 | }; |
227 | |
228 | |
229 | /* AMD's copy of various payload data for MST. We have two copies of the payload table (one in DRM, |
230 | * one in DC) since DRM's MST helpers can't be accessed here. This stream allocation table should |
231 | * _ONLY_ be filled out from DM and then passed to DC, do NOT use these for _any_ kind of atomic |
232 | * state calculations in DM, or you will break something. |
233 | */ |
234 | |
235 | struct drm_dp_mst_port; |
236 | |
237 | /* DP MST stream allocation (payload bandwidth number) */ |
238 | struct dc_dp_mst_stream_allocation { |
239 | uint8_t vcp_id; |
240 | /* number of slots required for the DP stream in |
241 | * transport packet */ |
242 | uint8_t slot_count; |
243 | }; |
244 | |
245 | /* DP MST stream allocation table */ |
246 | struct dc_dp_mst_stream_allocation_table { |
247 | /* number of DP video streams */ |
248 | int stream_count; |
249 | /* array of stream allocations */ |
250 | struct dc_dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; |
251 | }; |
252 | |
253 | #endif /*__DAL_LINK_SERVICE_TYPES_H__*/ |
254 | |