1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_LINK_SERVICE_TYPES_H__
27#define __DAL_LINK_SERVICE_TYPES_H__
28
29#include "grph_object_id.h"
30#include "dal_types.h"
31#include "irq_types.h"
32
33/*struct mst_mgr_callback_object;*/
34struct ddc;
35struct irq_manager;
36
37enum {
38 MAX_CONTROLLER_NUM = 6
39};
40
41enum dp_power_state {
42 DP_POWER_STATE_D0 = 1,
43 DP_POWER_STATE_D3
44};
45
46enum edp_revision {
47 /* eDP version 1.1 or lower */
48 EDP_REVISION_11 = 0x00,
49 /* eDP version 1.2 */
50 EDP_REVISION_12 = 0x01,
51 /* eDP version 1.3 */
52 EDP_REVISION_13 = 0x02
53};
54
55enum {
56 LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
57};
58
59enum link_training_result {
60 LINK_TRAINING_SUCCESS,
61 LINK_TRAINING_CR_FAIL_LANE0,
62 LINK_TRAINING_CR_FAIL_LANE1,
63 LINK_TRAINING_CR_FAIL_LANE23,
64 /* CR DONE bit is cleared during EQ step */
65 LINK_TRAINING_EQ_FAIL_CR,
66 /* other failure during EQ step */
67 LINK_TRAINING_EQ_FAIL_EQ,
68 LINK_TRAINING_LQA_FAIL,
69};
70
71struct link_training_settings {
72 struct dc_link_settings link_settings;
73 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
74 bool allow_invalid_msa_timing_param;
75};
76
77enum hw_dp_training_pattern {
78 HW_DP_TRAINING_PATTERN_1 = 0,
79 HW_DP_TRAINING_PATTERN_2,
80 HW_DP_TRAINING_PATTERN_3,
81 HW_DP_TRAINING_PATTERN_4
82};
83
84/*TODO: Move this enum test harness*/
85/* Test patterns*/
86enum dp_test_pattern {
87 /* Input data is pass through Scrambler
88 * and 8b10b Encoder straight to output*/
89 DP_TEST_PATTERN_VIDEO_MODE = 0,
90
91 /* phy test patterns*/
92 DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
93 DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
94 DP_TEST_PATTERN_SYMBOL_ERROR,
95 DP_TEST_PATTERN_PRBS7,
96 DP_TEST_PATTERN_80BIT_CUSTOM,
97 DP_TEST_PATTERN_CP2520_1,
98 DP_TEST_PATTERN_CP2520_2,
99 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
100 DP_TEST_PATTERN_CP2520_3,
101
102 /* Link Training Patterns */
103 DP_TEST_PATTERN_TRAINING_PATTERN1,
104 DP_TEST_PATTERN_TRAINING_PATTERN2,
105 DP_TEST_PATTERN_TRAINING_PATTERN3,
106 DP_TEST_PATTERN_TRAINING_PATTERN4,
107 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
108
109 /* link test patterns*/
110 DP_TEST_PATTERN_COLOR_SQUARES,
111 DP_TEST_PATTERN_COLOR_SQUARES_CEA,
112 DP_TEST_PATTERN_VERTICAL_BARS,
113 DP_TEST_PATTERN_HORIZONTAL_BARS,
114 DP_TEST_PATTERN_COLOR_RAMP,
115
116 /* audio test patterns*/
117 DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
118 DP_TEST_PATTERN_AUDIO_SAWTOOTH,
119
120 DP_TEST_PATTERN_UNSUPPORTED
121};
122
123enum dp_panel_mode {
124 /* not required */
125 DP_PANEL_MODE_DEFAULT,
126 /* standard mode for eDP */
127 DP_PANEL_MODE_EDP,
128 /* external chips specific settings */
129 DP_PANEL_MODE_SPECIAL
130};
131
132/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
133union dpcd_training_lane_set {
134 struct {
135#if defined(LITTLEENDIAN_CPU)
136 uint8_t VOLTAGE_SWING_SET:2;
137 uint8_t MAX_SWING_REACHED:1;
138 uint8_t PRE_EMPHASIS_SET:2;
139 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
140 /* following is reserved in DP 1.1 */
141 uint8_t POST_CURSOR2_SET:2;
142#elif defined(BIGENDIAN_CPU)
143 uint8_t POST_CURSOR2_SET:2;
144 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
145 uint8_t PRE_EMPHASIS_SET:2;
146 uint8_t MAX_SWING_REACHED:1;
147 uint8_t VOLTAGE_SWING_SET:2;
148#else
149 #error ARCH not defined!
150#endif
151 } bits;
152
153 uint8_t raw;
154};
155
156
157/* DP MST stream allocation (payload bandwidth number) */
158struct dp_mst_stream_allocation {
159 uint8_t vcp_id;
160 /* number of slots required for the DP stream in
161 * transport packet */
162 uint8_t slot_count;
163};
164
165/* DP MST stream allocation table */
166struct dp_mst_stream_allocation_table {
167 /* number of DP video streams */
168 int stream_count;
169 /* array of stream allocations */
170 struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
171};
172
173#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
174